1. Add support for RGBX_8888 UBWC in display engine and gralloc APIs.
2. Set the appropriate rotator output format for RGB* UBWC formats.
3. Move the UBWC aligned format enums in their appropriate range.
Change-Id: I0107f10894f9edbe657fce29b99f6e909c675150
Add support for new secure system heap and corresponding flags
for all pixel buffers. Keep the old mm heap for secure display
buffers.
Change-Id: Ic0ee7783a2d1ff420c34396f7cc4bd5ac3058c44
1. Reclaim some old gralloc flags.
2. System heap allocation happens by default.
3. Remove some unused private flags.
4. Add heapid member to alloc_data to better line up with ion
header
5. Remove check for MDSS_TARGET
Change-Id: I37be0a2fcd5fd4a14bb9ca235fcae41f6f3ec19e
Add support for NV12_UBWC HAL pixel format in getYUVPlaneInfo api to
enable GRALLOC_MODULE_PERFORM_GET_YUV_PLANE_INFO for this format.
Change-Id: I94389ddc45cba94124b36fb3ecb0b947250c0681
1. It helps in checking gralloc private usage flags at compile time.
2. Define GRALLOC_MODULE_PERFORM_GET_UBWC_FLAG to enable client to
query the value of "PRIV_FLAGS_UBWC_ALIGNED" flag at run time.
3. Add ADRENO_PIXELFORMAT_NV12_EXT in defined Adreno Pixel formats
to fix NV12_UBWC HAL pixel format conversion to Adreno format.
Change-Id: I78ccac98f1bd1bfbd2aa596ceb7a293f3d2e5f6e
1. Allow UBWC allocation, if client is using an explicitly defined
UBWC HAL pixel format OR if client sets UBWC gralloc usage flag and
GPU supports the format.
2. EGL wants gralloc to set PRIV_FLAGS_UBWC_ALIGNED bit in private
handle flags, only if GPU supports UBWC for that format.
Change-Id: I4194a046217cbc4c0a8ac2b2fb4b73ebd5076fc2
Modify getYUVPlaneInfo to return data from metadata
as well, if the geometry has changed, and align it
according to the format.
Change-Id: I119a1719c214c87e542b471c9cd9a20b01e2bf5e
Add adreno_utils header to define Adreno pixel formats, which are
needed by gralloc to map HAL format to corresponding Adreno format.
Change-Id: I6d38f34583955e3990393801f1dca0dd9aa2013b
1. Add support for UBWC allocation in the Gralloc APIs for aligned
width, aligned height and buffer size. A client can request for UBWC
allocation by sending UBWC specific HAL pixel format or by setting
GRALLOC_USAGE_PRIVATE_ALLOC_UBWC flag in the usage flags.
2. Gralloc allocates UBWC aligned buffer, only if format is supported
by GPU and MDP and no CPU usage flags are set. Otherwise it allocates
linear buffer.
3. If UBWC conditions are met, gralloc sets PRIV_FLAGS_UBWC_ALIGNED
in private handle flags to tell client that allocated buffer has UBWC
alignment. This flag remains unset by default.
4. Add helper functions in gralloc to calculate UBWC meta buffer size
for RGB* formats.
5. Add UBWC HAL pixel format HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS_UBWC
which has been defined by Video module.
6. Add AdrenoMemInfo api to query, if GPU supports UBWC for a format.
7.MDP driver expects UBWC specific pixel format defined by MDP header.
Change-Id: I5b4344bc90aa498dbdb7bb8100e70ed7728e6ea5
Remove the unused gralloc flag: GRALLOC_USAGE_PRIVATE_UI_CONTIG_HEAP.
It was only used when we had ION carveout allocations for UI. It is
not needed anymore and no module is using it.
Change-Id: I46ec5758ec3c753ee20426c258aa2a0a46f6a4ac
Allocate gralloc buffers cached by default unless clients specify
uncached using PRIVATE_UNCACHED or READ_RARELY or WRITE_RARELY at
allocation time. Some clients could use gralloc for allocation but
later won't use lock()/unlock() for CPU operations and likely use
their own caching methods. Cached by default helps such clients.
SW usage flags are not defined as bit values, so do not use bitops
on those flags.
Change-Id: Id371de2ec6efbfa0ed84172b3540f3ebc8f5d459
Pass a flag to ion to allow non-contiguous allocations with a sg
(scatter gather) list of 1MB chunks for all secure buffers except
secure display.
Change-Id: Ife2709e94571ab7603b29da17805a857ba73fd72
For PROTECTED but NON SECURE layers set MDP_SMP_FORCE_ALLOC flag
to allow SMP allocation and prevent GPU fallback
In Such cases if video resolution changes dynamically
it fails to display layer due to GPU fallback.
Use this flag for FB layer composition and depricate
MDP_BACKEND_COMPOSITION flag.
Change-Id: I9ab7cbdd2e12b56dfa67d5b4b3ff6b2dcd0096be
-Clients not having WRITE_OFTEN or READ_OFTEN are uncached.
-Invalidate cache on lock only if CPU needs to read and there
are non-CPU writers in system (camera,gpu etc)
-Flush cache on unlock only if CPU writes. Since all buffers will be
read in HWC(MDP) there is no need to check if readers exist.
Change-Id: Icd114e60b7456bd71592b81016892e806c37cb22
- Use proper alignment for cstride while calculating the
ycbcr info for YV12 format
- This fixes the corruption issue when the video is composed
using GPU
CRs-fixed: 711696
Change-Id: I776cc6c5ce781ea3de25b5d8427345b512a8305a
Graphics requires 32 pixel alignment and camera driver is being
updated to this.
Change-Id: I00fe659f7a16abeb8f65d9bbf41a24a7c8113bfb
CRs-fixed: 476475
NV12 spec says that the chroma stride is the same as the luma
stride. The camera hardware produces YUV data per this spec.
NV21 has the same behaviour with the chroma samples reversed.
Venus also conforms to this.
Change-Id: I6e107b2a3ba6f51e135348bd147a9c26be003bb2
Remove opaque types like size_t, uintptr_t, intptr_t to support
32bit and 64bit processes together.
When a 64bit process creates a handle and a 32bit process validates
the incoming ints against expected ints, opaque types lead to
different and mismatching values.
Always use unit64_t for base address for 32bit and 64bit SF.
Use unsigned int for offset and size, since ION uses that.
Change-Id: I7db5544556a8924f98010b965f837592e9f0b4ca
The android_ycbcr structure in graphics.h is populated to give
the luma and chroma addresses. Use the same structure to give
this information to graphics via a gralloc perform call.
Change-Id: Ib42866a9ea90873886dcb60a1aac6cb375292642
Remove all klockwork warnings and errors for libgralloc,
libhwcomposer, liboverlay, libqdutils, libqservice, libvirtual,
libexternal libraries to avoid buffer overflow and memory leaks.
Change-Id: I078143bcbcf5e4b342156bd8305a644566f7cc4b
getSize was incorrectly modifying aligned height and allocating
a buffer of lesser than expected size.
All alignments should be done in getAlignedWidthAndHeight so as not
to break the GRALLOC_PERFORM functions.
getSize()'s return type is unsigned, but a signed value is returned.
Instead on error, a size of 0 should be reported.
Change-Id: Ifae5e758de8e689701cd43892324ccc0140675cd
Macro tile is enabled only if all the conditions are met:
1. GPU hardware should support Macro Tiling.
2. MDSS hardware should support Macro Tiling.
3. USAGE flags shouldnt contain GRALLOC_USAGE_SW_READ_OFTEN and
GRALLOC_USAGE_SW_WRITE_OFTEN.
4. RGB 16bit and 32bit formats.
5. persist.hwc.macro_tile_enable flag should be enabled.
PRIV_FLAGS_TILE_RENDERED flag is added to indicate whether the layer
is rendered/composited in Macro Tiling or Linear format.
Change-Id: Ie3139839c84d76c5d1a2300f33910a09eb7336f4
Use new GFX API compute_aligned_width_and_height to get the stride
value for RGB surfaces.
Backward compatible with GFX old API when old GFX library is used.
Change-Id: I15b0954602b816bf4e88f48622494144fc77c14f
As sRGB_888 is not defined, replace it with sRGB_X_8888
Change-Id: Ie7e27ffea1ca6ec99de8e746c0f784e5fc9a4e53
(cherry picked from commit b81796dc9a0c4178004ae947e9d756c5cae6967a)
Refer to graphics.h for the definition of these new formats.
The HWC doesn't yet support output to these formats.
Change-Id: I14dade3412d262d853d3783ba77d559c76d331bf
(cherry picked from commit 3a63837a3d006aee3d176d379409bf3134f6189b)
YUV 420 buffers have the chroma starting at consecutive bytes
but end at the same byte. This results in the second chroma size
being one byte shorter in size. This isn't a problem for
hardware, however, the gralloc lock_ycbcr API expects to read the
same number of bytes based on the cstride for both chroma
components. This could lead to it accessing memory beyond what is
allocated leading to a crash in the calling process especially
when the size aligns exactly to the page size. Add one byte
padding when allocating YUV buffers to make sure the users of
this gralloc API get enough bytes to read.
Bug: 10787131
Change-Id: Id18e0739f9fdc2c7a4fbe7724be668a989f1a4a1
(cherry picked from commit ca07ffae967e7137fb0d97fb9999a11c09b4a7b5)
Add Support to HAL_PIXEL_FORMAT_NV21_ZSL format in gralloc for
camera capture usecase.
This support is required because, CPP module requires 64 byte
aligned width and height to resolve corruption in bottom/left edge
of the landscape/portrait buffer.
Change-Id: Id3e0e5f3d695d5111f3469f78a1d52aad9bea4f4
(cherry picked from commit 512ee1dcef6fa47dfdcf3990fea29bd85f967f02)
This changes removes the use of 5551 and 4444 pixel formats
as its not supported anymore
Change-Id: I817510c3c7c0c3d95924c2ffc79e5727a6d6c48f
(cherry picked from commit 1fbd4a9662b07d53a3f220c91b3e85ca571a4938)
MM HEAP will be used only for Widevine Level-1 secure playback.
Since Video component assures of using MM HEAP flags only for
WV Level-1 and Level-3 will not be marked with MM HEAP it is
possible to allow supporting both of these protection levels
co existing in a device.
Change-Id: I153eeebf20bdab0c2ce930a5a124369a2b3249a6
CRs-fixed: 562601
Adding support for interleaved HAL_PIXEL_FORMAT_YCbCr_422_I and
HAL_PIXEL_FORMAT_YCrCb_422_I format in display HAL.
Change-Id: Ib87d9bf481c20bf6a92293dd04746719b1d928c1
GRALLOC_USAGE_SW_WRITE_RARELY and GRALLOC_USAGE_SW_READ_RARELY
need to be compared directly since they share bits with
GRALLOC_USAGE_SW_WRITE_OFTEN and GRALLOC_USAGE_SW_READ_OFTEN.
Change-Id: I52692027033e1036e3ad960b9e03dd8ee60b4111
Targets having the venus core have the same allocation and stride
requirements for HAL_PIXEL_FORMAT_NV12_ENCODEABLE as the
HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS format.
Change-Id: Ie5ab8db6639dfa791c5be0161cde6140c3dae779
- Adds flag GRALLOC_USAGE_PRIVATE_CAMERA_HEAP to use the dedicated
CAMERA_HEAP
- Remove GRALLOC_USAGE_PRIVATE_CP_BUFFER which is not used anymore
Change-Id: Iefea88d9a67d2fa0ca74492f508e1d5508d08983
