For MDP3 we cannot support scaling more/less then 4 times. Copybit
will use intermediate buffer to run scaling operation between 4
and 16, by going through MDP3 twice. But will not continue to do
so for scaling factors greater than 16 because operation takes too
long. It is in this case that we will fallback to gpu composition.
Change-Id: I99c05f6c70307823d0497cc8f9469bcc15178fea
Fixing array size to hold fence fd to count of render
buffers used in copybit and use it to store
fence of corresponding render buffer at the index.
Change-Id: Ic5e7f264c2a81ded2a0f61ef138e59a093b0023a
1. Color layer has a destination rectangle, RGBA color and plane
alpha. There is no gralloc buffer. Layer flag HWC_COLOR_FILL
denotes color layer. MDP BLIT happens via MDP_SOLID_FILL mode.
2. There is no color member in HWC layer, so RGBA color value is
passed via "tranform" member from framework to HAL.
3. Update HWC query to enable framework to query for Color layer
support in HAL, at run-time.
Change-Id: I2c698007c1689779fe86d549093bb5285432dc5f
Some applications send RGBA layer with constant alpha 0xFF and
isOpaque=1. For these types of layer we don't get any wormHole
regions. Hence we see the previous content (framebuffer) due to
wrong selection of blending logic at kernel side.
To fix these kind of issues on MDP3 we make layer with Z order
zero as FG layer. This makes sure that proper blending logic
is chosen in kernel.
CRs-fixed: 521638
CRs-fixed: 517944
Change-Id: I172a46c3284916264a1413a6a16875afea2b1aad
On 8x10, ppp composition is enabled. For PPP blending operation,
it can take around 14-15ms. This results that when the frame is
given to the display for rendering, it can happen around the
vsync boundary. While DMA does the page flipping, it makes sure
it happens on vsync boundary. However, in the ppp case, the vsync
can be from the previous frame, not the new frame just delivered.
Because of that, there will be tearing. Increase the buffer count
to 3 will resolve this issue, and improve the frame rate as well.
Change-Id: I53bff1a61b38eaecd286fdbe8a069522e28df6ba
copybit blit may not be effective if data for composition
is high. Add configurable threshold support beyond which
we can avoid copybit blit. set default threshold value to
2 times of fb resolution.
CRs-fixed: 462450
Change-Id: I0ee77ea1d761dc370d82ade1724caefbecfa01f5
When blending translucent layers or transitioning with c2d,
sometimes the frame is blended with stale framebuffer content.
Clear the frame with C2D fill surface before drawing.
CRs-fixed: 462461
Change-Id: I1dca477fe88d77f4f0fa4846b155404f348e911d
The earlier copybit solution involved blitting directly into
the SurfaceFlinger's framebuffer target. That solution involved
unnecessary framework changes and caused issues when the
framebuffer was being written to both by GL and copybit.
Update hwc_copybit to use our own buffers for this purpose.
We also make sure we display only the region we're interested in
so that unnecessary artifacts from previous blits do not show up
on the display. This way, we can avoid clearing the intermediate
buffers every frame.
Change-Id: I713b3fc606e0768444c621af76853ece41964da1
- Add CopybitEngine to hwc_context
- draw the layer on the HWC_FRAMEBUFFER_TARGET using
copybit(c2d) if it qualifies for C2D composition.
- use fence returned from the copybit during c2d
composition
Change-Id: I052da015cd031f7abd6411d83d7944c335caeff7
* Use the vsync uevents from the kernel to start
surfaceflinger composition.
* This patch also does some code cleanup
- Move copybit specific functions to copybit files.
- Cleanup verbose logging.
Change-Id: I36936e4b0a082cfb0347d8ee7d2bc936e01808e6
This change add support for copybit composition in display HAL
for MDP3 targets.
Change-Id: I9bc8e40f624b0760f4faa223cb03a13695611bb3
Acked-by: Sravan Kumar D.V.N <sravank1@codeaurora.org>
