Whether or not an update is small (conservatively set to < 5% of
screen) is checked using total dirty areas of layers and GPU is
used to compose. This is because a smaller update also means GPU
had less front end work and the MDP can avoid fetching data from
all layers until idle timeout.
Change-Id: I1ccd8913f2a1c760f570b225fdfb29f6a20b5a8d
- Populate frame_rate in rotator set, so that driver
can vote for honest BW for rotator based on frame rate.
- If metadata contains source fps, frame_rate will be set
to source fps, else it will be set to primary refresh rate.
- frame_rate will be populated for primary with
source fps from metada, only when secondary is not active.
Change-Id: Icaacd0ed67ec09591d31868591680d2e86fe54a2
- All secure layers are marked with GRALLOC_USAGE_PROTECTED,
irrespective of L1/L3, which should not fallback to GPU.
- In HWC, treat this layer as secure so that any fallbacks
will be avoided.
Change-Id: I399740bfb5910f3fda4c4f395e2f7b49ea8619a9
Crs-fixed: 842071
In early return calls of prepare, reset the refresh rate
irrespective of layer properties to avoid stack corruption.
Change-Id: I5a04e111b1f10a6cb807459c7693d049c454edaa
CRs-Fixed: 838902
Earlier, for targets with #pipes less than 8, padding
round was not getting triggered when DMA state
changes from LINE to BLOCK Mode. Fix that now.
Change-Id: I46cb817fcf4e4027d5a7d20a8e887088ef6411b5
In low end targets with one VG pipe, when there are more than one
YUV layer in the layer list, configure one YUV layer (bottom most)
to VG pipe, instead of falling back to GPU completely.
Change-Id: I5c78613573c4ebfbda3a729245092cc635ef8b98
Short story: This missing initialization fixes a crash in SF during
bootup on video mode panels with idle timeout.
Long story: SF creates HWC which registers a timeout handler. The
driver triggers this without even a composition round happening.
The junk value in mode tracking in MDPComp allows this timeout to
get translated into an invalidate() on SF. At this point SF may
not have fully created its EventThread (timing issue), which causes
a crash during bootup.
Change-Id: Icc91391399b2c0a027957be0689a226b5b1da783
- In targets with fewer pipes, composition switch can happen
continuously for a layer based on whether it is updating or not.
If that updating layer requires downscaling, because of the
difference in the downscale filters between MDP and GPU,
the output of MDP and GPU will differ. This difference could be
perceived as flicker. To avoid this flicker, mark RGB downscaled layer
with downscale more than threshold to GPU always.
- property persist.hwc.downscale_threshold defines the threshold value
for downscale beyond which the layer will be marked for GPU composition.
Change-Id: Ifd26d7eb1eff0096b0391a0552d0fd97386c1a19
When external is active and primary has all ViG pipes, a video
playback may be starved of pipes on external. Use one GPU comp.
round for high-end targets as well.
Change-Id: I7f2e1d4a6a98a04e0fc1ec917ecedbb6ce56d067
* On Low end targets which has constraint on the #pipes, avoid
fullMDPComp and fullMDPCompWithPTOR on primary
when secondary is connected and secondary has a YUV layer.
* This helps in secondary have sufficient number of RGB or DMA pipes
to handle sudden increase in #layers.
Change-Id: Ie848300c86f756125146482dc027c1c5872de7a6
- Retrieve cursor pipe info from driver
- Configure the layer marked with flag HWC_IS_CURSOR_LAYER to the
HWCursor using the fb_cursor ioctl.
- The config happens only when it satisfies the hw limitions of
cursor
- HWCursor is supported on primary display
- Since cursor configuration happens first, make use of drop
layer/count to handle other composition strategies
- Add support for hwc_setCursorPositionAsync as per HWC 1.4
Change-Id: I8663b6da89b0c2dd9b48af96d64a433b2b8a302c
There could be scenarios where the bottom layers are RGB, which could
take up all ViG pipes as well, leaving no pipes for videos. Using
mixed mode may not help if those RGB layers are updating, since GPU
will be continuously invoked.
This patch reserves pipes for videos instead of serial order.
Change-Id: Ia5e25294ecc18a54dc36923a930cb23914d9475b
Reset PTOR info in HWC reset to make sure that Copybit does not draw
any Overlap region, even if there is no App layer in HWC layer list.
Change-Id: Ie2fb3408ba0171fd098a6b2627f4b9d59ae94ee6
* Until now, it was the assumption that when display animation
is in progress and there is a video rotation involved, the yuv-layer
would be marked as skip till completion of display animation.
But this is not always the case.
* On low-end targets, there is a constraint on #VG-pipes and
during video playback, video on primary is composed using GPU
where as video on secondary is composed using MDP. When display
animation is in progress, in such usecase, ensure that MDP is
is completely avoided so that VG pipe is available to secondary
once display animation is done.
* On high-end targets, video on both primary and secondary are
composed using MDP due to sufficient VG pipes. When display
animation is in progress, in such usecase, ensure to skip
fullMDP and partialMDP composition strategies so that
VG pipe that was supposed to be available for secondary is not
used for RGB layers on primary.
Change-Id: I841de1d902b627dd6e625251bf384c38b2db816e
Crop width and crop height should be even for yuv layer, so fallback
to GPU composition if the values are less than 2.
Change-Id: I8677dd32bfd88e5509b8890377afd82e83b07e45
- Instead of assuming the default format(RGBA_8888),
read FB format from driver and pass the info to SF
- For now, this is limited to primary and HDMI only.
WB FBformat is assumed to be in RGBA_8888
- If FB doesn't have alpha channel, disable mixed mode
Change-Id: Iefc0080819749b541483ea47357bb37ec150c544
* When the ambient light changes, pp-daemon will invoke multiple
screen-refresh cycles for LUT convergence needed for
PP algorithms.
* When this happens during static screen usecase, there would
be frequent switches from gpu-comp(due to idlescreen-fallback)
to mdpcomp and back. This results in increase in power numbers
due to increased composition cycles.
* To resolve this, do the following:
a) If frame 'n' is composed using GPU and frame 'n+1' is same
as frame 'n' in terms of input layers contents, avoid any
composition needed for frame 'n+1'. Mark the composition type
for all the layers as HWC_OVERLAY and push the GPU composed
content of frame 'n' for 'n+1' too.
b) Donot do (a) if the any of the incoming layers is marked as
skip or HWC_GEOMETRY_CHANGED flag is set in layer list.
c) Limit (a) to only primary and when secondary is not connected
so that display output expectations during secondary pause-resume
can be met.
* This saves ~10ma during static screen usecase when ambient
light is frequently changing.
Change-Id: I6ca4ab3bf194ffe71191cc661086a14d3e2c26b3
When client prefer to enable PU(partial update) over PP(post
processing), delay enabling PU until PP turns off its
features completely. This change introduces hand shaking flags
between PP and HWC through binder calls. When requested to turn
on PU, we notify PP through the sys_fs node. When PP is done
shutting off it features, it acknowledges back to HWC to actually
turn on PU.
Change-Id: I72008f2313b93497f55c0435367ef62cd772c2c4
split.
1) When source split is enabled, both the panels are calibrated
in a single coordinate system. So only one ROI is generated
for the whole panel extending equally from the midpoint and
populated for the left side.
2) Fixes a bug in mdpcomp where ROI generated for the frame is
reset when a strategy fails.
Change-Id: I47fa0e827985dd76d06dcbe464ef832cfc57a671
Perf lock acquire would fail during the boot up as the perfd
service is not up yet.
Its harmless to remove these logs which cause false alarm
Change-Id: Id305f3122a77ebe70819e4b3edfaf405c3a87d70
1. Add support to set HDMI to 3D mode
2. Add binder API to force 3D mode
3. Switch to 3D mode based on metadata
4. Configure pipes appropriately
5. Only side-by-side and top-bottom formats are currently supported
Change-Id: Iae579ecfa45aae088ff543d4143e5025e8c682fa
If rotator downscale is able to reduce output dimensions below
MDP's pipe limits, then use only 1 pipe if possible in source split
cases.
Change-Id: I6739a1fcd32b1047ce266d60c0123961c9daa657
ping-pong split needs source split to be enabled to stage two
pipes of a layer in the same Z order. This change adds partial
update support to generate ROI when source split is enabled.
When configured, ping-pong-split splits the layer mixer output equally
across two DSI's. To meet this limitation, the generated ROI is
adjusted to have equal widths from the panel mid point.
Change-Id: Ic307a1d5b902af9e352b0dfc6f5ab474ecd9c8a4
* Explore cachebased and loadbased composition strategies
eventhough skip layer is present in the layer list.
* Prioritize loadBasedComp over cacheBasedComp in such case.
* Invoke redraw of FB for every-frame as long as skip-layer
is present to comply with the spec.
Change-Id: If105ae8af4888a1e0b0fb824c526ef5a1adaedd8
With source split enabled:
1) When both LEFT and RIGHT pipes gets reused pipes, we use their
pipe id's to compare their priority and swap them as needed.
2) When both LEFT and RIGHT pipes needs to be newly allocated, we
let driver take care of the priority as long as both pipes are
of same type. If different, we swap them according to the pipe
type priority.
3) When LEFT is reused and RIGHT needs new allocation, we swap
them only when they need same pipe type and LEFT has the
pipe with lowest priority.
4) When RIGHT is reused and LEFT needs new allocation, we swap
them only when they need same pipe type and RIGHT has the
pipe with highest priority.
Change-Id: I320285aaca7ffc032e3b3b0832380a9c705bc4fc
Reset ROI in when we are unable to proceed with full MDP comp.
Do not use dirtyRect for video use-cases to address some
corner cases
Change-Id: Id1ea6c1515f4441f0f35c0d08828e9c361bcbc86
1. Add support for UBWC allocation in the Gralloc APIs for aligned
width, aligned height and buffer size. A client can request for UBWC
allocation by sending UBWC specific HAL pixel format or by setting
GRALLOC_USAGE_PRIVATE_ALLOC_UBWC flag in the usage flags.
2. Gralloc allocates UBWC aligned buffer, only if format is supported
by GPU and MDP and no CPU usage flags are set. Otherwise it allocates
linear buffer.
3. If UBWC conditions are met, gralloc sets PRIV_FLAGS_UBWC_ALIGNED
in private handle flags to tell client that allocated buffer has UBWC
alignment. This flag remains unset by default.
4. Add helper functions in gralloc to calculate UBWC meta buffer size
for RGB* formats.
5. Add UBWC HAL pixel format HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS_UBWC
which has been defined by Video module.
6. Add AdrenoMemInfo api to query, if GPU supports UBWC for a format.
7.MDP driver expects UBWC specific pixel format defined by MDP header.
Change-Id: I5b4344bc90aa498dbdb7bb8100e70ed7728e6ea5
MDPOnly composition needs to cater for the use case when we have
secure RGB layers that require MDP composition. For non-secure RGB
layers we can afford to send them for GPU composition. This is
especially needed for the following use case: full MDP composition
on primary (including YUV layers), followed by external connection.
For the mentioned use case, we need to fall back to Video and then
GPU composition in in order to reclaim pipe resources for external
usage.
Change-Id: I6da3ca48cf6e38e767fecfbfee6b06e82ba00a51
- Set the perf hint when there is only one updating layer, which helps
in reducing cpu params and thus reduce power.
- This feature is enabled with the property persist.mdpcomp_perfhint,
which is set to a positive value, which will be the window of frames
before the perf hint is set
CRs-fixed: 765460
Change-Id: Ie21e1cd201afab16bedd3c750ea3b0230769969a
