1. Define LINEAR_FORMAT operation in MetaData.
2. VENUS ouput buffer is linear for NV12_UBWC Interlaced video playback.
So Video module performs LINEAR_FORMAT operation to set "linearFormat"
metadata member to NV12 linear format in case of Interlaced video.
3. Handle LINEAR_FORMAT metadata operation in HWC wrapper and gralloc.
CRs-Fixed: 855474
Change-Id: I77dd72bec26f225de75adb6c214ccd90db239e3e
1. Fix the missed ALIGN in getUBwcMetaBufferSize api.
2. Fix de-reference of data address pointer in getRgbDataAddress api.
Change-Id: I5dae2b6f449bb9a5b0dcc23110a2efce36060a42
Change I86300a1b4e3008f9d0884940420e9036c47a016f introduces a
regression by mapping metadata part of secure buffers, but not
unmapping that. This change fixes the map/unmap asymmetry.
Change-Id: I078eef1139642bd6d8a01145ab1c81060621fb8d
A client can call GRALLOC_MODULE_PERFORM_GET_RGB_DATA_ADDRESS api
to get RGB data address for any linear or UBWC aligned RGB buffer.
Change-Id: I3a7d25f504b7ba1dec79cc872cafbb38ddbb6bd2
1. Reclaim some old gralloc flags.
2. System heap allocation happens by default.
3. Remove some unused private flags.
4. Add heapid member to alloc_data to better line up with ion
header
5. Remove check for MDSS_TARGET
Change-Id: I37be0a2fcd5fd4a14bb9ca235fcae41f6f3ec19e
1. It helps in checking gralloc private usage flags at compile time.
2. Define GRALLOC_MODULE_PERFORM_GET_UBWC_FLAG to enable client to
query the value of "PRIV_FLAGS_UBWC_ALIGNED" flag at run time.
3. Add ADRENO_PIXELFORMAT_NV12_EXT in defined Adreno Pixel formats
to fix NV12_UBWC HAL pixel format conversion to Adreno format.
Change-Id: I78ccac98f1bd1bfbd2aa596ceb7a293f3d2e5f6e
1. Add support for UBWC allocation in the Gralloc APIs for aligned
width, aligned height and buffer size. A client can request for UBWC
allocation by sending UBWC specific HAL pixel format or by setting
GRALLOC_USAGE_PRIVATE_ALLOC_UBWC flag in the usage flags.
2. Gralloc allocates UBWC aligned buffer, only if format is supported
by GPU and MDP and no CPU usage flags are set. Otherwise it allocates
linear buffer.
3. If UBWC conditions are met, gralloc sets PRIV_FLAGS_UBWC_ALIGNED
in private handle flags to tell client that allocated buffer has UBWC
alignment. This flag remains unset by default.
4. Add helper functions in gralloc to calculate UBWC meta buffer size
for RGB* formats.
5. Add UBWC HAL pixel format HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS_UBWC
which has been defined by Video module.
6. Add AdrenoMemInfo api to query, if GPU supports UBWC for a format.
7.MDP driver expects UBWC specific pixel format defined by MDP header.
Change-Id: I5b4344bc90aa498dbdb7bb8100e70ed7728e6ea5
Allocate gralloc buffers cached by default unless clients specify
uncached using PRIVATE_UNCACHED or READ_RARELY or WRITE_RARELY at
allocation time. Some clients could use gralloc for allocation but
later won't use lock()/unlock() for CPU operations and likely use
their own caching methods. Cached by default helps such clients.
SW usage flags are not defined as bit values, so do not use bitops
on those flags.
Change-Id: Id371de2ec6efbfa0ed84172b3540f3ebc8f5d459
lock() can be called from a CpuConsumer with only the READ_OFTEN flag
so relying only on that makes gralloc assume there are no non cpu
writers.
Store the writer information during allocation in private flags of
handle and refer to those during lock()
Change-Id: Ifbf25ebc74dbf4e422a2fdec52ec000cd75e549b
- The client sets this metadata to inform GPU to map the CP buffer
- GPU will check the PRIV_FLAG_SECURE and this metadata to map the CP buffer
- If this field is not set on the buffer handle, then GPU will not map
the CP buffer
- Allow mapping of metadata for SECURE_BUFFERS also
Change-Id: I86300a1b4e3008f9d0884940420e9036c47a016f
-Clients not having WRITE_OFTEN or READ_OFTEN are uncached.
-Invalidate cache on lock only if CPU needs to read and there
are non-CPU writers in system (camera,gpu etc)
-Flush cache on unlock only if CPU writes. Since all buffers will be
read in HWC(MDP) there is no need to check if readers exist.
Change-Id: Icd114e60b7456bd71592b81016892e806c37cb22
Update buffer geometry is supported through metadata, hence remove
GRALLOC_MODULE_PERFORM_UPDATE_BUFFER_GEOMETRY support
Change-Id: I349a966c383e16600126634723da15f4137a30d8
Remove opaque types like size_t, uintptr_t, intptr_t to support
32bit and 64bit processes together.
When a 64bit process creates a handle and a 32bit process validates
the incoming ints against expected ints, opaque types lead to
different and mismatching values.
Always use unit64_t for base address for 32bit and 64bit SF.
Use unsigned int for offset and size, since ION uses that.
Change-Id: I7db5544556a8924f98010b965f837592e9f0b4ca
The android_ycbcr structure in graphics.h is populated to give
the luma and chroma addresses. Use the same structure to give
this information to graphics via a gralloc perform call.
Change-Id: Ib42866a9ea90873886dcb60a1aac6cb375292642
The custom stride and height can be set by video
decoder for smooth streaming. Return this in
perform so that graphics can use it
Change-Id: I44c814b2bae1f61d3ec5c36a22d1c6119542b10a
Fill the android_ycbcr struct for HAL_PIXEL_FORMAT_YCbCr_*_888
formats.
This is a flexible YUV format that allows gralloc to set a
hardware specific YUV format based on the usage flags passed in.
Here we set the format similar to how we set the implementation
defined format and set the android_ycbcr structure to point to
the appropriate plane offsets.
Reference: HAL_PIXEL_FORMAT_YCbCr_420_888 definition in
system/core/include/system/graphics.h
Change-Id: If0c7abf5e206bf982ad333da2dae57cbac302733
Macro tile is enabled only if all the conditions are met:
1. GPU hardware should support Macro Tiling.
2. MDSS hardware should support Macro Tiling.
3. USAGE flags shouldnt contain GRALLOC_USAGE_SW_READ_OFTEN and
GRALLOC_USAGE_SW_WRITE_OFTEN.
4. RGB 16bit and 32bit formats.
5. persist.hwc.macro_tile_enable flag should be enabled.
PRIV_FLAGS_TILE_RENDERED flag is added to indicate whether the layer
is rendered/composited in Macro Tiling or Linear format.
Change-Id: Ie3139839c84d76c5d1a2300f33910a09eb7336f4
Use new GFX API compute_aligned_width_and_height to get the stride
value for RGB surfaces.
Backward compatible with GFX old API when old GFX library is used.
Change-Id: I15b0954602b816bf4e88f48622494144fc77c14f
The custom stride can be set by video for smooth streaming.
Return this in perform so that graphics can use it.
Change-Id: I798fc0894b8d9662e93769a53a540cb61b527a44
Check that the buffer is actually an ion buffer
before calling clean. This is needed for the case
where the physically contiguous framebuffer is mapped.
That framebuffer memory is used for bringup.
Change-Id: I2db84d4bfc3465d995f12e0860be3cafa0d4a81b
genlock is no-op from Android 4.2 onwards since the sync framework
is used for explicit synchronization.
Change-Id: Idd1df589516534a683e0fa1ef0cfbb7f0e411f67
- Introduce a new class to Get the Adreno computed stride information.
This class has been added to allow adreno library computed strides to
be propagated to the allocation function as well as those clients
requesting it.
- Add a new Perform function to get the stride. The width and the format
can be passed from the calling functions (like EGL) to get the stride of
the buffer.
Change-Id: I4c2b4a02deff327f0ea5558c478997527fe9d3cf
Make the display HALs compile with/without the Qualcomm BSP
specific features so they can work with pure AOSP.
Change-Id: I1ad7282c4fe1fe7e3309afb530a07735f165ffbe
Initialize metadata pointer in the buffer handle to NULL after
unmapping the buffer pointer
Change-Id: I930a2d21a6f259426949d7aa58bd07f1f58839c0
CRs-Fixed: 434388
Allocate extra space for metadata in buffer handles
Provide api to map this space in client process and set the metadata
Change-Id: I8bca8448670d4aa88d439320faf402dae30458f8
Add case GRALLOC_MODULE_PERFORM_UPDATE_BUFFER_GEOMETRY in
gralloc_perform function to update the new buffer dimensions.
Change-Id: I7a855dc017dd042dda2abdc28c51ce5ec919fceb
- Update the display HAL from Code Aurora Forum
- Add updated overlay library
- Enable HWC with basic video going through overlay
- Cleanup some files
Change-Id: I65c687c51be458cee71213c79e03eeda962d9086
