For MDP3 we cannot support scaling more/less then 4 times. Copybit
will use intermediate buffer to run scaling operation between 4
and 16, by going through MDP3 twice. But will not continue to do
so for scaling factors greater than 16 because operation takes too
long. It is in this case that we will fallback to gpu composition.
Change-Id: I99c05f6c70307823d0497cc8f9469bcc15178fea
For copybit cases we should clear wormhole region
rather than nonwormhole. Adding support to calculate
and clear the same.
Change-Id: Ie85d1b484174199e35f43ce95b30de1fac9c30b2
We are using the solid fill feature for
clearing the wormhole region using black
color.
Using the src buffer same as dst buffer to
avoid kernel checks for this use case.
Change-Id: Ia46aded9b067ece83c9df1f2c2cdd6b017fa64ea
Fixing array size to hold fence fd to count of render
buffers used in copybit and use it to store
fence of corresponding render buffer at the index.
Change-Id: Ic5e7f264c2a81ded2a0f61ef138e59a093b0023a
1. Color layer has a destination rectangle, RGBA color and plane
alpha. There is no gralloc buffer. Layer flag HWC_COLOR_FILL
denotes color layer. MDP BLIT happens via MDP_SOLID_FILL mode.
2. There is no color member in HWC layer, so RGBA color value is
passed via "tranform" member from framework to HAL.
3. Update HWC query to enable framework to query for Color layer
support in HAL, at run-time.
Change-Id: I2c698007c1689779fe86d549093bb5285432dc5f
Increment hwc version to 1.3.
Create and use a converter from float source crop to integers.
Change-Id: I5e185195c975b3a9434c5d9dce9ae4757ff98739
(cherry picked from commit 7e5637c850bcdbe21784ca3bfa9668870306adff)
Since mdp3 only has one dma pipe for overlay, which in the driver
is just a sw overlay, there is no need to force a overlay_set call
when HWC_GEOMETRY_CHANGED is set.
Also we are moving the wait for distination buffer fence to
wait inside the blit call for mdp3.
Change-Id: Id0aed8732dc49b1041d8174a5ff38703c8023abf
update the source video width and height set by the video decoder
for secure video smooth streaming usecase from metadata.
Change-Id: I73a3804d90557034604142481a232787dbc08f23
1.Framework notifies HAL with "HWC_FORMAT_RB_SWAP" layer flag to handle
a limitation where R and B components were swapped in Rendering phase.
2.Add "R/B swap" in hwc query to enable framework to query for support
in display HAL, at run-time.
Change-Id: I3b44d15b51b4f24939048fee9d1bac2b9009c97c
There was an error message that should just be a warning messages.
These error logs can cause automation testing to fail.
Change-Id: Ifb205d9f893012e9693628fcd24b2493d7ea51b8
A sw workaround was created in mdp3 so composition of layers with
rotation and roi that is not divisible by 16 is now possible to
be done by ppp.
Change-Id: Iada3707da1b85e58dad398b8271d7a26725e0d22
In case of non overlay target composition of the video
layer should be based on composition of UI layer as well.
(if taget has dynamic composition)
Change-Id: I6f312978f9168dddcf6ad0b1ac72f347b94d6920
CRs-fixed: 516630
When flip and rotation(90) are present alter the flip,
as GPU is doing the flip and rotation in opposite order
to that of MDP3.0
For 270 degrees, we get 90 + (H+V) which is same as doing
flip first and then rotation (H+V) + 90
Change-Id: I89fb4633342ae71bfdaa21837b0f16784e439147
Fall back to GPU on MDP3 when Non WormholeRegion is
not of frame buffer size as artifact is seen in
WormholeRegion of previous frame.
CRs-fixed: 531081
Change-Id: Ic597ee9f75178276dd5498400648bfefc990188f
Some applications send RGBA layer with constant alpha 0xFF and
isOpaque=1. For these types of layer we don't get any wormHole
regions. Hence we see the previous content (framebuffer) due to
wrong selection of blending logic at kernel side.
To fix these kind of issues on MDP3 we make layer with Z order
zero as FG layer. This makes sure that proper blending logic
is chosen in kernel.
CRs-fixed: 521638
CRs-fixed: 517944
Change-Id: I172a46c3284916264a1413a6a16875afea2b1aad
There were error message that should just be debug messages.
These error logs can cause automation testing to fail.
Change-Id: I4ba681a737e8324da9ef8e7984efa57f70ee8637
MDP3 doesn't support plane alpha. So falling back to
gpu whenever there is plane alpha in the list of layers.
Change-Id: Iec40e5160f4320b7393d937444645d1a243bd83b
Mdp3 has a hw issue where it cannot handle rotation and blending,
when roi height or width is not divisible by 16. When roi is not
divisible by 16 mdp3 would read memory that it is beyond the
image. This leads to page faults, which further leads to poor
performance.
Change-Id: I2cd1b77c21c407503399630cdb702b575aa4e64e
When image was being up scaled beyond 4 times and intermediate
buffer is used, alpha value would be 0 in intermediate buffer.
This would then be blitted onto final buffer that contained alpha
value. Since fg had alpha value of 0 entire image would be blended
out.
Change-Id: I6daf03e93719212ee597c218655ae8692ae79e72
The counter that was incremented when an acquire fence was provided
was not the counter that was passed into the blit call. Due to
blit requests being processed in order that it is submitted, it is
not need to pass in previous release fence as acquire fence for
next blit request.
Change-Id: Ic259af24b33e5e69440d481c92788107ff639bed
- Check for MAX_NUM_APP_LAYERS before updating yuv indices array.
- Fall back to GPU composition when number of app layers exceeds
MAX_NUM_APP_LAYERS to avoid heap corruption.
Change-Id: Ieb91b705a0a5f50ce2f8829d1f1ee048d44b7d2e
Since mdp composition is now an async call, the waiting for fences
is now no longer needed inside copybit. In addition, how
composition ioctl is called is slightly different as a result
needing to pass in aquire fences device performing compsition
Change-Id: Ia12dfb2960ba2fc78b14e776984ffe0c3fe45fdb
In dynamic composition, While calculating total render area of
application layers to decide on which composition to choose,
FrameBuffer layer area shall not be added to the total render area.
Change-Id: Ibfa23130864ebae514ab94e75813bfaa4a61528c
This change is the hwc and copybit changes need to enable
composition to go through mdp on msm8610.
Change-Id: If0df3a247c5f4f4310966d14fe8fd839bf84b9d5
Add check in copybit for Max. layers supported by HWC. Increase
max. RGB surfaces to MAX_NUM_LAYERS to support known use cases.
CRs-Fixed: 481226
Change-Id: Ie30ab0ef3047a304133cb547902ae11fecc5db22
copybit blit may not be effective if data for composition
is high. Add configurable threshold support beyond which
we can avoid copybit blit. set default threshold value to
2 times of fb resolution.
CRs-fixed: 462450
Change-Id: I0ee77ea1d761dc370d82ade1724caefbecfa01f5
When blending translucent layers or transitioning with c2d,
sometimes the frame is blended with stale framebuffer content.
Clear the frame with C2D fill surface before drawing.
CRs-fixed: 462461
Change-Id: I1dca477fe88d77f4f0fa4846b155404f348e911d
The earlier copybit solution involved blitting directly into
the SurfaceFlinger's framebuffer target. That solution involved
unnecessary framework changes and caused issues when the
framebuffer was being written to both by GL and copybit.
Update hwc_copybit to use our own buffers for this purpose.
We also make sure we display only the region we're interested in
so that unnecessary artifacts from previous blits do not show up
on the display. This way, we can avoid clearing the intermediate
buffers every frame.
Change-Id: I713b3fc606e0768444c621af76853ece41964da1
Make the display HALs compile with/without the Qualcomm BSP
specific features so they can work with pure AOSP.
Change-Id: I1ad7282c4fe1fe7e3309afb530a07735f165ffbe
- Add CopybitEngine to hwc_context
- draw the layer on the HWC_FRAMEBUFFER_TARGET using
copybit(c2d) if it qualifies for C2D composition.
- use fence returned from the copybit during c2d
composition
Change-Id: I052da015cd031f7abd6411d83d7944c335caeff7
