mirror of
https://github.com/oplus-giulia-dev/android_kernel_oneplus_sm8650-devicetrees
synced 2025-11-05 23:36:42 +08:00
Add 'qcom/graphics/' from commit '3fdf0e5c8cd8aaddf897363301ae23e559faa2b1'
git-subtree-dir: qcom/graphics git-subtree-mainline:483309a856git-subtree-split:3fdf0e5c8c
This commit is contained in:
Arian
96
qcom/graphics/Kbuild
Normal file
96
qcom/graphics/Kbuild
Normal file
@@ -0,0 +1,96 @@
|
||||
ifeq ($(CONFIG_ARCH_WAIPIO), y)
|
||||
dtbo-y += gpu/waipio-gpu.dtbo \
|
||||
gpu/waipio-v2-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_KALAMA), y)
|
||||
dtbo-y += gpu/kalama-gpu.dtbo \
|
||||
gpu/kalama-v2-gpu.dtbo \
|
||||
gpu/kalama-iot-gpu.dtbo \
|
||||
gpu/kalamap-hhg-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
|
||||
dtbo-y += gpu/pineapple-gpu.dtbo \
|
||||
gpu/pineapple-v2-gpu.dtbo \
|
||||
gpu/pineapple-v2-sg-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_SA8155), y)
|
||||
dtbo-y += gpu/sa8155-v2-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_KHAJE), y)
|
||||
dtbo-y += gpu/khaje-gpu.dtbo \
|
||||
gpu/khajep-gpu.dtbo \
|
||||
gpu/khajeq-gpu.dtbo \
|
||||
gpu/khajeg-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_SA8195), y)
|
||||
dtbo-y += gpu/sa8195p-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_SA6155), y)
|
||||
dtbo-y += gpu/sa6155p-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_MONACO), y)
|
||||
dtbo-y += gpu/monaco-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_LEMANS), y)
|
||||
dtbo-y += gpu/lemans-gpu.dtbo \
|
||||
gpu/lemans-gpu-ivi-adas-star.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_KONA), y)
|
||||
dtbo-y += gpu/kona-gpu.dtbo \
|
||||
gpu/kona-v2-gpu.dtbo \
|
||||
gpu/kona-v2.1-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_BLAIR), y)
|
||||
dtbo-y += gpu/blair-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_TRINKET), y)
|
||||
dtbo-y += gpu/trinket-gpu.dtbo \
|
||||
gpu/trinketp-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_HOLI), y)
|
||||
dtbo-y += gpu/holi-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_QCS405), y)
|
||||
dtbo-y += gpu/qcs405-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_PITTI), y)
|
||||
dtbo-y += gpu/pitti-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_CLIFFS), y)
|
||||
dtbo-y += gpu/cliffs-gpu.dtbo \
|
||||
gpu/cliffs7-gpu.dtbo
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_VOLCANO), y)
|
||||
dtbo-y += gpu/volcano-gpu.dtbo
|
||||
dtbo-y += gpu/volcano6-gpu.dtbo
|
||||
dtbo-y += gpu/volcano6p-gpu.dtbo
|
||||
|
||||
dtbo-y += gpu/volcano6i-fp1-gpu.dtbo
|
||||
dtbo-y += gpu/volcano6i-fp2-gpu.dtbo
|
||||
dtbo-y += gpu/volcano6i-fp3-gpu.dtbo
|
||||
dtbo-y += gpu/volcano6i-fp4-gpu.dtbo
|
||||
dtbo-y += gpu/volcano6ip-fp1-gpu.dtbo
|
||||
dtbo-y += gpu/volcano6ip-fp2-gpu.dtbo
|
||||
dtbo-y += gpu/volcano6ip-fp3-gpu.dtbo
|
||||
dtbo-y += gpu/volcano6ip-fp4-gpu.dtbo
|
||||
endif
|
||||
|
||||
always-y := $(dtb-y) $(dtbo-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
clean-files := *.dtb *.dtbo
|
||||
9
qcom/graphics/Makefile
Normal file
9
qcom/graphics/Makefile
Normal file
@@ -0,0 +1,9 @@
|
||||
KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=.
|
||||
|
||||
all: dtbs
|
||||
|
||||
clean:
|
||||
$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
|
||||
|
||||
%:
|
||||
$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)
|
||||
16
qcom/graphics/bindings/adreno-busmon.txt
Normal file
16
qcom/graphics/bindings/adreno-busmon.txt
Normal file
@@ -0,0 +1,16 @@
|
||||
Adreno bus monitor device
|
||||
|
||||
kgsl-busmon is a pseudo device that represents a devfreq bus bandwidth
|
||||
governor. If this device is present then two different governors are used
|
||||
for GPU DCVS and bus DCVS.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "qcom,kgsl-busmon"
|
||||
- label: Device name used for sysfs entry.
|
||||
|
||||
Example:
|
||||
|
||||
qcom,kgsl-busmon {
|
||||
compatible = "qcom,kgsl-busmon";
|
||||
label = "kgsl-busmon";
|
||||
};
|
||||
115
qcom/graphics/bindings/adreno-gmu.txt
Normal file
115
qcom/graphics/bindings/adreno-gmu.txt
Normal file
@@ -0,0 +1,115 @@
|
||||
Qualcomm Technologies, Inc. GPU Graphics Management Unit (GMU)
|
||||
|
||||
Required properties:
|
||||
- compatible :
|
||||
- "qcom,gpu-gmu"
|
||||
- "qcom,gpu-gmu-hwsched"
|
||||
- "qcom,gpu-rgmu"
|
||||
- "qcom,gen7-gmu"
|
||||
- "qcom,gen7-gmu-hwsched"
|
||||
- reg: Specifies the GMU register base address and size.
|
||||
- reg-names: Resource names used for the physical address
|
||||
and length of GMU registers.
|
||||
- interrupts: Interrupt mapping for GMU and HFI IRQs.
|
||||
- interrupt-names: String property to describe the name of each interrupt.
|
||||
|
||||
Bus Scaling Data:
|
||||
qcom,msm-bus,name: String property to describe the name of bus client.
|
||||
qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property.
|
||||
qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase.
|
||||
qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is:
|
||||
<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 1
|
||||
<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 2
|
||||
<.. .. .. ..>, <.. .. .. ..>; // For Bus Scaling Usecase n
|
||||
This property is a series of all vectors for all Bus Scaling Usecases.
|
||||
Each set of vectors for each usecase describes bandwidth votes for a combination
|
||||
of src/dst ports. The driver will set the desired use case based on the selected
|
||||
power level and the desired bandwidth vote will be registered for the port pairs.
|
||||
|
||||
GMU GDSC/regulators:
|
||||
- regulator-names: List of regulator name strings
|
||||
- vddcx-supply: Phandle for vddcx regulator device node.
|
||||
- vdd-supply: Phandle for vdd regulator device node.
|
||||
|
||||
- clock: List of clocks to be used for GMU register access and DCVS. See
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
for information about the format. For each clock specified
|
||||
here, there must be a corresponding entry in clock-names
|
||||
(see below).
|
||||
|
||||
- clock-names: List of clock names corresponding to the clocks specified in
|
||||
the "clocks" property (above). See
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
for more info. Currently GMU required these clock names:
|
||||
"gmu_clk", "ahb_clk", "cxo_clk", "axi_clk", "memnoc_clk",
|
||||
"rbcpr_clk"
|
||||
|
||||
- qcom,gmu-freq-table: List of frequencies the GMU clock can run at with their corresponding
|
||||
voltage levels.
|
||||
|
||||
- List of sub nodes, one for each of the translation context banks needed
|
||||
for GMU to access system memory in different operating mode. Currently
|
||||
supported names are:
|
||||
- gmu_user: used for GMU 'user' mode address space.
|
||||
- gmu_kernel: used for GMU 'kernel' mode address space.
|
||||
Each sub node has the following required properties:
|
||||
|
||||
- compatible : "qcom,smmu-gmu-user-cb" or "qcom,smmu-gmu-kernel-cb"
|
||||
- iommus : Specifies the SID's used by this context bank, this
|
||||
needs to be <kgsl_smmu SID> pair, kgsl_smmu is the string
|
||||
parsed by iommu driver to match this context bank with the
|
||||
kgsl_smmu device defined in iommu device tree. On targets
|
||||
where the msm iommu driver is used rather than the arm smmu
|
||||
driver, this property may be absent.
|
||||
|
||||
- qcom,ipc-core: <baseAddr size>
|
||||
baseAddr - base address of the IPC region
|
||||
size - size of the IPC region
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
gmu: qcom,gmu@2c6a000 {
|
||||
label = "kgsl-gmu";
|
||||
compatible = "qcom,gpu-gmu";
|
||||
|
||||
reg = <0x2c6a000 0x30000>;
|
||||
reg-names = "kgsl_gmu_reg";
|
||||
|
||||
interrupts = <0 304 0>, <0 305 0>;
|
||||
interrupt-names = "kgsl_gmu_irq", "kgsl_hfi_irq";
|
||||
|
||||
qcom,msm-bus,name = "cnoc";
|
||||
qcom,msm-bus,num-cases = <2>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<26 10036 0 0>, // CNOC off
|
||||
<26 10036 0 100>; // CNOC on
|
||||
|
||||
regulator-name = "vddcx", "vdd";
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
clocks = <&clock_gpugcc clk_gcc_gmu_clk>,
|
||||
<&clock_gcc GCC_GPU_CFG_AHB_CLK>,
|
||||
<&clock_gpucc GPU_CC_CXO_CLK>,
|
||||
<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&clock_gpucc GPU_CC_RBCPR_CLK>;
|
||||
|
||||
clock-names = "gmu_clk", "ahb_clk", "cxo_clk",
|
||||
"axi_clk", "memnoc_clk", "rbcpr_clk";
|
||||
|
||||
qcom,gmu-freq-table = <200000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
|
||||
<500000000 RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
gmu_user: gmu_user {
|
||||
compatible = "qcom,smmu-gmu-user-cb";
|
||||
iommus = <&kgsl_smmu 4>;
|
||||
};
|
||||
|
||||
gmu_kernel: gmu_kernel {
|
||||
compatible = "qcom,smmu-gmu-kernel-cb";
|
||||
iommus = <&kgsl_smmu 5>;
|
||||
};
|
||||
};
|
||||
81
qcom/graphics/bindings/adreno-iommu.txt
Normal file
81
qcom/graphics/bindings/adreno-iommu.txt
Normal file
@@ -0,0 +1,81 @@
|
||||
Qualcomm Technologies, Inc. GPU IOMMU
|
||||
|
||||
Required properties:
|
||||
|
||||
Required properties:
|
||||
- compatible : one of:
|
||||
- "qcom,kgsl-smmu-v1"
|
||||
- "qcom,kgsl-smmu-v2"
|
||||
|
||||
- reg : Base address and size of the SMMU.
|
||||
|
||||
- clocks : List of clocks to be used during SMMU register access. See
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
for information about the format. For each clock specified
|
||||
here, there must be a corresponding entry in clock-names
|
||||
(see below).
|
||||
|
||||
- clock-names : List of clock names corresponding to the clocks specified in
|
||||
the "clocks" property (above). See
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
for more info.
|
||||
- qcom,protect : The GPU register region which must be protected by a CP
|
||||
protected mode. On some targets this region must cover
|
||||
the entire SMMU register space, on others there
|
||||
is a separate aperture for CP to program context banks.
|
||||
|
||||
Optional properties:
|
||||
- qcom,retention : A boolean specifying if retention is supported on this target
|
||||
- qcom,global_pt : A boolean specifying if global pagetable should be used.
|
||||
When not set we use per process pagetables
|
||||
- qcom,hyp_secure_alloc : A bool specifying if the hypervisor is used on this target
|
||||
for secure buffer allocation
|
||||
|
||||
- List of sub nodes, one for each of the translation context banks supported.
|
||||
The driver uses the names of these nodes to determine how they are used,
|
||||
currently supported names are:
|
||||
- gfx3d_user : Used for the 'normal' GPU address space.
|
||||
- gfx3d_secure : Used for the content protection address space.
|
||||
- gfx3d_secure_alt : Used for the content protection address space for alternative SID.
|
||||
|
||||
Each sub node has the following required properties:
|
||||
|
||||
- compatible : "qcom,smmu-kgsl-cb"
|
||||
- iommus : Specifies the SID's used by this context bank, this needs to be
|
||||
<kgsl_smmu SID> pair, kgsl_smmu is the string parsed by iommu
|
||||
driver to match this context bank with the kgsl_smmu device
|
||||
defined in iommu device tree. On targets where the msm iommu
|
||||
driver is used rather than the arm smmu driver, this property
|
||||
may be absent.
|
||||
|
||||
Example:
|
||||
|
||||
msm_iommu: qcom,kgsl-iommu@2ca0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
reg = <0x2ca0000 0x10000>;
|
||||
qcom,protect = <0xa0000 0xc000>;
|
||||
clocks = <&clock_mmss clk_gpu_ahb_clk>,
|
||||
<&clock_gcc clk_gcc_mmss_bimc_gfx_clk>,
|
||||
<&clock_mmss clk_mmss_mmagic_ahb_clk>,
|
||||
<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>;
|
||||
clock-names = "gpu_ahb_clk", "bimc_gfx_clk", "mmagic_ahb_clk", "mmagic_cfg_ahb_clk";
|
||||
qcom,secure_align_mask = <0xfff>;
|
||||
qcom,retention;
|
||||
qcom,global_pt;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0>,
|
||||
<&kgsl_smmu 1>;
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 2>;
|
||||
};
|
||||
|
||||
gfx3d_secure_alt: gfx3d_secure_alt {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 2>, <&kgsl_smmu 1>;
|
||||
};
|
||||
};
|
||||
94
qcom/graphics/bindings/adreno-pwrlevels.txt
Normal file
94
qcom/graphics/bindings/adreno-pwrlevels.txt
Normal file
@@ -0,0 +1,94 @@
|
||||
Qualcomm Technologies, Inc. GPU powerlevels
|
||||
|
||||
Powerlevels are defined in sets by qcom,gpu-pwrlevels. Multiple sets (bins)
|
||||
can be defined within qcom,gpu-pwrelvel-bins. Each powerlevel defines a
|
||||
voltage, bus, bandwidth level, and a DVM value.
|
||||
|
||||
- qcom,gpu-pwrlevel-bins: Contains one or more qcom,gpu-pwrlevels sets
|
||||
|
||||
Properties:
|
||||
- compatible: Must be qcom,gpu-pwrlevel-bins
|
||||
- qcom,gpu-pwrlevels: Defines a set of powerlevels
|
||||
|
||||
Properties:
|
||||
- qcom,speed-bin: Speed bin identifier for the set - if present
|
||||
must match the value read from the hardware
|
||||
|
||||
- qcom,sku-codes: List of SKU versions specified by P-Code and
|
||||
Feature Code that can support this set of
|
||||
powerlevels. An entry of 0 in this list matches
|
||||
any SKU and can be used as a fallback if other
|
||||
powerlevel sets are not matched
|
||||
|
||||
- qcom,initial-pwrlevel: GPU wakeup powerlevel
|
||||
- qcom,initial-min-pwrlevel: Initial minimum available GPU powerlevel
|
||||
|
||||
- qcom,gpu-pwrlevel: A single powerlevel
|
||||
|
||||
- qcom,ca-target-pwrlevel:
|
||||
This value indicates which qcom,gpu-pwrlevel
|
||||
to jump on in case of context aware power level
|
||||
jump.
|
||||
Required Properties:
|
||||
- reg: Index of the powerlevel (0 = highest perf)
|
||||
- qcom,gpu-freq GPU frequency for the powerlevel (in Hz)
|
||||
- qcom,bus-freq Index to a bus level (defined by the bus
|
||||
settings).
|
||||
|
||||
- qcom,bus-freq-ddrX If specified, define the DDR specific bus
|
||||
frequency for the power level. X will be the
|
||||
return value from of_fdt_get_ddrtype().
|
||||
|
||||
Optional Properties:
|
||||
- qcom,bus-min Minimum bus level to set for the power level
|
||||
|
||||
- qcom,bus-min-ddrX If specified, define the DDR specific minimum
|
||||
bus level for the power level. X will be the
|
||||
return value from of_fdt_get_ddrtype().
|
||||
|
||||
- qcom,bus-max maximum bus level to set for the power level
|
||||
|
||||
- qcom,bus-max-ddrX If specified, define the DDR specific maximum
|
||||
bus level for the power level. X will be the
|
||||
return value from of_fdt_get_ddrtype().
|
||||
|
||||
- qcom,acd-level: Value that is used as a register setting for
|
||||
the ACD power feature. It helps to determine
|
||||
the threshold for when ACD activates. Zero is
|
||||
the default value, and the setting where ACD
|
||||
will never activate.
|
||||
|
||||
- qcom,cx-level: Specifies the CX vote required for each GPU power
|
||||
level.
|
||||
|
||||
Example:
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
qcom,acd-level = <0xffffffff>;
|
||||
qcom,cx-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
Example for DDR4/DDR5 specific part:
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <480000000>;
|
||||
qcom,cx-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
/* DDR5 */
|
||||
qcom,bus-freq-ddr8 = <10>;
|
||||
qcom,bus-min-ddr8 = <9>;
|
||||
qcom,bus-max-ddr8 = <11>;
|
||||
|
||||
/* DDR 4 */
|
||||
qcom,bus-freq-ddr7 = <9>;
|
||||
qcom,bus-min-ddr7 = <7>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
qcom,acd-level = <0xffffffff>;
|
||||
};
|
||||
535
qcom/graphics/bindings/adreno.txt
Normal file
535
qcom/graphics/bindings/adreno.txt
Normal file
@@ -0,0 +1,535 @@
|
||||
Qualcomm Technologies, Inc. GPU
|
||||
|
||||
Qualcomm Technologies, Inc. Adreno GPU
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "qcom,kgsl-3d0".
|
||||
May also includes "qcom,adreno-gpu-*" for few targets.
|
||||
Must include "qcom,adreno-gpu-a610" for Bengal target.
|
||||
Must include "qcom,adreno-gpu-a611" for Pitti target.
|
||||
Must include "qcom,adreno-gpu-a619-holi" for Holi target.
|
||||
Must include "qcom,adreno-gpu-a621" for Neo target.
|
||||
Must include "qcom,adreno-gpu-a660-shima" for Shima target.
|
||||
Must include "qcom,adreno-gpu-gen7-0-0" for Waipio target.
|
||||
Must include "qcom,adreno-gpu-gen7-0-1" for Waipio V2 target.
|
||||
Must include "qcom,adreno-gpu-gen7-2-0" for Kalama target.
|
||||
Must include "qcom,adreno-gpu-gen7-2-1" for Kalama V2 target.
|
||||
Must include "qcom,adreno-gpu-gen7-4-0" for Cape target.
|
||||
Must include "qcom,adreno-gpu-gen7-3-0" for Parrot target.
|
||||
Must include "qcom,adreno-gpu-gen7-9-0" for Pineapple target.
|
||||
Must include "qcom,adreno-gpu-gen7-9-1" for Pineapple V2 target.
|
||||
Must include "qcom,adreno-gpu-gen7-11-0" for Cliffs target.
|
||||
Must include "qcom,adreno-gpu-gen8-3-0" for Volcano target.
|
||||
- reg: Specifies the list of register regions for the device.
|
||||
- reg-names: Resource names used for the register regions specified
|
||||
in reg.
|
||||
- interrupts: Interrupt mapping for GPU nterrupts.
|
||||
- interrupt-names: String property to describe the names of the interrupts.
|
||||
- qcom,gpu-bimc-interface-clk-freq:
|
||||
GPU-BIMC interface clock needs to set to this value for
|
||||
targets where B/W requirements does not meet GPU Turbo
|
||||
use cases.
|
||||
- clocks: List of phandle and clock specifier pairs, one pair
|
||||
for each clock input to the device.
|
||||
- clock-names: List of clock input name strings sorted in the same
|
||||
order as the clocks property.
|
||||
|
||||
- qcom,base-leakage-coefficient: Dynamic leakage coefficient.
|
||||
- qcom,lm-limit: Current limit for GPU limit management.
|
||||
- qcom,isense-clk-on-level: below or equal this power level isense clock is at XO rate,
|
||||
above this powerlevel isense clock is at working frequency.
|
||||
|
||||
Bus Scaling Data:
|
||||
- qcom,gpu-bus-table: Defines a bus voting table with the below properties. Multiple sets of bus
|
||||
voting tables can be defined for given platform based on the type of ddr system.
|
||||
|
||||
Properties:
|
||||
- compatible: Must be "qcom,gpu-bus-table". Additionally, "qcom,gpu-bus-table-ddr" must also
|
||||
be provided, with the ddr type value(integer) appended to the string.
|
||||
- qcom,msm-bus,name: String property to describe the name of the 3D graphics processor.
|
||||
- qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property.
|
||||
- qcom,msm-bus,active-only: A boolean flag indicating if it is active only.
|
||||
- qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase.
|
||||
- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is:
|
||||
<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 1
|
||||
<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 2
|
||||
<.. .. .. ..>, <.. .. .. ..>; // For Bus Scaling Usecase n
|
||||
This property is a series of all vectors for all Bus Scaling Usecases.
|
||||
Each set of vectors for each usecase describes bandwidth votes for a combination
|
||||
of src/dst ports. The driver will set the desired use case based on the selected
|
||||
power level and the desired bandwidth vote will be registered for the port pairs.
|
||||
Current values of src are:
|
||||
0 = MSM_BUS_MASTER_GRAPHICS_3D
|
||||
1 = MSM_BUS_MASTER_GRAPHICS_3D_PORT1
|
||||
2 = MSM_BUS_MASTER_V_OCMEM_GFX3D
|
||||
Current values of dst are:
|
||||
0 = MSM_BUS_SLAVE_EBI_CH0
|
||||
1 = MSM_BUS_SLAVE_OCMEM
|
||||
ab: Represents aggregated bandwidth. This value is 0 for Graphics.
|
||||
ib: Represents instantaneous bandwidth. This value has a range <0 8000 MB/s>
|
||||
|
||||
- qcom,ocmem-bus-client: Container for another set of bus scaling properties
|
||||
qcom,msm-bus,name
|
||||
qcom,msm-bus,num-cases
|
||||
qcom,msm-bus,num-paths
|
||||
qcom,msm-bus,vectors-KBps
|
||||
to be used by ocmem msm bus scaling client.
|
||||
|
||||
GDSC Oxili Regulators:
|
||||
- regulator-names: List of regulator name strings sorted in power-on order
|
||||
- vddcx-supply: Phandle for vddcx regulator device node.
|
||||
- vdd-supply: Phandle for vdd regulator device node.
|
||||
- vdd-parent-supply: Phandle for vdd parent regulator device node.
|
||||
- vdd-parent-min-corner: Minimum voltage corner value to set vdd parent supply.
|
||||
|
||||
IOMMU Data:
|
||||
- iommu: Phandle for the KGSL IOMMU device node
|
||||
|
||||
GPU Power levels:
|
||||
- qcom,gpu-pwrlevel-bins: Container for sets of GPU power levels (see
|
||||
adreno-pwrlevels.txt)
|
||||
DCVS Core info
|
||||
- qcom,dcvs-core-info Container for the DCVS core info (see
|
||||
dcvs-core-info.txt)
|
||||
|
||||
Optional Properties:
|
||||
- qcom,initial-powerlevel: This value indicates which qcom,gpu-pwrlevel should be used at start time
|
||||
and when coming back out of resume
|
||||
- qcom,throttle-pwrlevel: This value indicates which qcom,gpu-pwrlevel LM throttling
|
||||
may start to occur
|
||||
- qcom,bus-control: Boolean. Enables an independent bus vote from the gpu frequency
|
||||
- qcom,bus-width: Bus width in number of bytes. This enables dynamic AB bus voting based on
|
||||
bus width and actual bus transactions.
|
||||
- qcom,bus-accesses: Parameter for tuning bus dcvs.
|
||||
- qcom,bus-accesses-ddrX: Parameter for tuning bus dcvs for each DDR configuration where
|
||||
X will be the return value from of_fdt_get_ddrtype().
|
||||
- qcom,gpubw-dev: a phandle to a device representing bus bandwidth requirements
|
||||
(see devdw.txt)
|
||||
- qcom,idle-timeout: This property represents the time in milliseconds for idle timeout.
|
||||
- qcom,chipid: If it exists this property is used to replace
|
||||
the chip identification read from the GPU hardware.
|
||||
This is used to override faulty hardware readings.
|
||||
- qcom,gpu-model: If it exists this property is used for GPU model name.
|
||||
- qcom,vk-device-id: If it exists this property is used to specify vulkan device ID.
|
||||
- qcom,disable-wake-on-touch: Boolean. Disables the GPU power up on a touch input event.
|
||||
- qcom,disable-busy-time-burst:
|
||||
Boolean. Disables the busy time burst to avoid switching
|
||||
of power level for large frames based on the busy time limit.
|
||||
|
||||
- qcom,pm-qos-active-latency:
|
||||
Right after GPU wakes up from sleep, driver votes for
|
||||
acceptable maximum latency to the pm-qos driver. This
|
||||
voting demands that the system can not go into any
|
||||
power save state *if* the latency to bring system back
|
||||
into active state is more than this value.
|
||||
Value is in microseconds.
|
||||
- qcom,pm-qos-wakeup-latency:
|
||||
Similar to the above. Driver votes against deep low
|
||||
power modes right before GPU wakes up from sleep.
|
||||
- qcom,l2pc-cpu-mask-latency:
|
||||
The CPU mask latency in microseconds to avoid L2PC
|
||||
on masked CPUs.
|
||||
|
||||
- qcom,gpu-cx-ipeak:
|
||||
CX Ipeak is a mitigation scheme which throttles cDSP frequency
|
||||
if all the clients are running at their respective threshold
|
||||
frequencies to limit CX peak current.
|
||||
<phandle bit>
|
||||
phandle - phandle of CX Ipeak device node
|
||||
bit - Every bit corresponds to a client of CX Ipeak
|
||||
driver in the relevant register.
|
||||
- qcom, gpu-cx-ipeak-freq:
|
||||
GPU frequency threshold for CX Ipeak voting. GPU votes
|
||||
to CX Ipeak driver when GPU clock crosses this threshold.
|
||||
CX Ipeak can limit peak current based on voting from other clients.
|
||||
|
||||
- qcom,force-32bit:
|
||||
Force the GPU to use 32 bit data sizes even if
|
||||
it is capable of doing 64 bit.
|
||||
|
||||
- qcom,gpu-speed-bin: GPU speed bin information in the format
|
||||
<offset mask shift>
|
||||
offset - offset of the efuse register from the base.
|
||||
mask - mask for the relevant bits in the efuse register.
|
||||
shift - number of bits to right shift to get the speed bin
|
||||
value.
|
||||
- qcom,gpu-disable-fuse: GPU disable fuse
|
||||
<offset mask shift>
|
||||
offset - offset of the efuse register from the base.
|
||||
mask - mask for the relevant bits in the efuse register.
|
||||
shift - number of bits to right shift to get the disable_gpu
|
||||
fuse bit value.
|
||||
|
||||
- qcom,soc-hw-rev-efuse: SOC hardware revision fuse information in the format
|
||||
<offset bit_position mask>
|
||||
offset - offset of the efuse register from the base.
|
||||
bit_position - hardware revision starting bit in the efuse register.
|
||||
mask - mask for the relevant bits in the efuse register.
|
||||
|
||||
- qcom,highest-bank-bit:
|
||||
Specify the bit of the highest DDR bank. This
|
||||
is programmed into protected registers and also
|
||||
passed to the user as a property.
|
||||
- qcom,min-access-length:
|
||||
Specify the minimum access length for the chip.
|
||||
Either 32 or 64 bytes.
|
||||
Based on the above options, program the appropriate bit into
|
||||
certain protected registers and also pass to the user as
|
||||
a property.
|
||||
- qcom,ubwc-mode:
|
||||
Specify the ubwc mode for this chip.
|
||||
1: UBWC 1.0
|
||||
2: UBWC 2.0
|
||||
3: UBWC 3.0
|
||||
Based on the ubwc mode, program the appropriate bit into
|
||||
certain protected registers and also pass to the user as
|
||||
a property.
|
||||
- qcom,l2pc-cpu-mask:
|
||||
Disables L2PC on masked CPUto the string.rendering thread is running on masked CPUs.
|
||||
Bit 0 is for CPU-0, bit 1 is for CPU-1...
|
||||
|
||||
- qcom,l2pc-update-queue:
|
||||
Disables L2PC on masked CPUs at queue time when it's true.
|
||||
|
||||
- qcom,snapshot-size:
|
||||
Specify the size of snapshot in bytes. This will override
|
||||
snapshot size defined in the driver code.
|
||||
|
||||
- qcom,enable-ca-jump:
|
||||
Boolean. Enables use of context aware DCVS
|
||||
- qcom,ca-busy-penalty:
|
||||
This property represents the time in microseconds required to
|
||||
initiate context aware power level jump.
|
||||
- qcom,ca-target-pwrlevel:
|
||||
This value indicates which qcom,gpu-pwrlevel to jump on in case
|
||||
of context aware power level jump.
|
||||
|
||||
- qcom,gpu-qdss-stm:
|
||||
<baseAddr size>
|
||||
baseAddr - base address of the gpu channels in the qdss stm memory region
|
||||
size - size of the gpu stm region
|
||||
|
||||
- qcom,gpu-timer:
|
||||
<baseAddr size>
|
||||
baseAddr - base address of the qtimer memory region
|
||||
size - size of the qtimer region
|
||||
|
||||
- qcom,tzone-names:
|
||||
Specify the names of GPU thermal zones. These will be used
|
||||
to get gpu temperature from the thermal driver API.
|
||||
|
||||
nvmem-cells:
|
||||
A phandle to the configuration data such as gpu speed bin, gpu gaming mode,
|
||||
gpu model name provided by a nvmem device. If unspecified default values shall be used.
|
||||
nvmem-cell-names:
|
||||
Should be "speed_bin", "gaming_bin", "gpu_model"
|
||||
|
||||
GPU Quirks:
|
||||
- qcom,gpu-quirk-two-pass-use-wfi:
|
||||
Signal the GPU to set Set TWOPASSUSEWFI bit in
|
||||
PC_DBG_ECO_CNTL (5XX and 6XX only)
|
||||
- qcom,gpu-quirk-critical-packets:
|
||||
Submit a set of critical PM4 packets when the GPU wakes up
|
||||
- qcom,gpu-quirk-fault-detect-mask:
|
||||
Mask out RB1-3 activity signals from HW hang
|
||||
detection logic
|
||||
- qcom,gpu-quirk-dp2clockgating-disable:
|
||||
Disable RB sampler data path clock gating optimization
|
||||
- qcom,gpu-quirk-lmloadkill-disable:
|
||||
Use register setting to disable local memory(LM) feature
|
||||
to avoid corner case error
|
||||
- qcom,gpu-quirk-hfi-use-reg:
|
||||
Use registers to replace DCVS HFI message to avoid GMU failure
|
||||
to access system memory during IFPC
|
||||
- qcom,gpu-quirk-limit-uche-gbif-rw:
|
||||
Limit number of read and write transactions from UCHE block to
|
||||
GBIF to avoid possible deadlock between GBIF, SMMU and MEMNOC.
|
||||
- qcom,gpu-quirk-mmu-secure-cb-alt:
|
||||
Select alternate secure context bank to generate SID1 for
|
||||
secure playback.
|
||||
|
||||
KGSL Memory Pools:
|
||||
- qcom,gpu-mempools: Container for sets of GPU mempools.Multiple sets
|
||||
(pools) can be defined within qcom,gpu-mempools.
|
||||
Each mempool defines a pool order, reserved pages,
|
||||
allocation allowed.
|
||||
Properties:
|
||||
- compatible: Must be qcom,gpu-mempools.
|
||||
- qcom,mempool-max-pages: Max pages for all mempools, If not defined there is no limit.
|
||||
- qcom,gpu-mempool: Defines a set of mempools.
|
||||
|
||||
Properties:
|
||||
- reg: Index of the pool (0 = lowest pool order).
|
||||
- qcom,mempool-page-size: Size of page.
|
||||
- qcom,mempool-reserved: Number of pages reserved at init time for a pool.
|
||||
- qcom,mempool-allocate: Allocate memory from the system memory when the
|
||||
reserved pool exhausted.
|
||||
- qcom,mempool-max-pages: Limit on max pages this pool can hold, If not defined
|
||||
there is no limit.
|
||||
GPU model configuration:
|
||||
- qcom,gpu-models:
|
||||
Container of sets of GPU model names specified by qcom,gpu-models.
|
||||
Properties:
|
||||
- compatible:
|
||||
Must be qcom,gpu-models.
|
||||
|
||||
- qcom,gpu-model:
|
||||
Defines a GPU model name for specific GPU model ID.
|
||||
|
||||
Properties:
|
||||
- compatible:
|
||||
May also include "qcom,adreno-gpu-*" for few targets.
|
||||
- qcom,gpu-model-id:
|
||||
Identifier for the specific GPU hardware configuration - must match the value read
|
||||
from the hardware.
|
||||
- qcom,gpu-model:
|
||||
GPU model name for a specific GPU hardware.
|
||||
|
||||
- qcom,vk-device-id:
|
||||
Vulkan device id unique for specific GPU hardware model.
|
||||
SOC Hardware revisions:
|
||||
- qcom,soc-hw-revisions:
|
||||
Container of sets of SOC hardware revisions specified by
|
||||
qcom,soc-hw-revision.
|
||||
Properties:
|
||||
- compatible:
|
||||
Must be qcom,soc-hw-revisions.
|
||||
|
||||
- qcom,soc-hw-revision:
|
||||
Defines a SOC hardware revision.
|
||||
|
||||
Properties:
|
||||
- qcom,soc-hw-revision:
|
||||
Identifier for the hardware revision - must match the value read
|
||||
from the hardware.
|
||||
- qcom,chipid:
|
||||
GPU Chip ID to be used for this hardware revision.
|
||||
- qcom,gpu-quirk-*:
|
||||
GPU quirks applicable for this hardware revision.
|
||||
|
||||
GPU LLC slice info:
|
||||
- cache-slice-names: List of LLC cache slices for GPU transactions
|
||||
and pagetable walk.
|
||||
- cache-slices: phandle to the system LLC driver, cache slice index.
|
||||
|
||||
L3 Power levels:
|
||||
- qcom,l3-pwrlevels: Container for sets of L3 power levels, the
|
||||
L3 frequency is adjusted according to the
|
||||
performance hint received from userspace.
|
||||
|
||||
Properties:
|
||||
- compatible: Must be qcom,l3-pwrlevels
|
||||
- qcom,l3-pwrlevel: A single L3 powerlevel
|
||||
|
||||
Properties:
|
||||
- reg: Index of the L3 powerlevel
|
||||
0 = powerlevel for no L3 vote
|
||||
1 = powerlevel for medium L3 vote
|
||||
2 = powerlevel for maximum L3 vote
|
||||
- qcom,l3-freq: The L3 frequency for the powerlevel (in Hz)
|
||||
|
||||
GPU coresight info:
|
||||
The following properties are optional as collecting data via coresight might
|
||||
not be supported for every chipset. The documentation for coresight
|
||||
properties can be found in:
|
||||
Documentation/devicetree/bindings/coresight/coresight.txt
|
||||
|
||||
- qcom,gpu-coresights: Container for sets of GPU coresight sources.
|
||||
- coresight-id: Unique integer identifier for the bus.
|
||||
- coresight-name: Unique descriptive name of the bus.
|
||||
- coresight-nr-inports: Number of input ports on the bus.
|
||||
- coresight-outports: List of output port numbers on the bus.
|
||||
- coresight-child-list: List of phandles pointing to the children of this
|
||||
component.
|
||||
- coresight-child-ports: List of input port numbers of the children.
|
||||
- coresight-atid: The unique ATID value of the coresight device
|
||||
|
||||
Example of A330 GPU in MSM8916:
|
||||
|
||||
&soc {
|
||||
msm_gpu: qcom,kgsl-3d0@1c00000 {
|
||||
label = "kgsl-3d0";
|
||||
compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
|
||||
reg = <0x1c00000 0x10000
|
||||
0x1c20000 0x20000>;
|
||||
reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory";
|
||||
interrupts = <0 33 0>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
qcom,id = <0>;
|
||||
|
||||
qcom,chipid = <0x03000600>;
|
||||
|
||||
qcom,initial-pwrlevel = <1>;
|
||||
|
||||
/* Idle Timeout = HZ/12 */
|
||||
qcom,idle-timeout = <8>;
|
||||
qcom,strtstp-sleepwake;
|
||||
|
||||
clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>,
|
||||
<&clock_gcc clk_gcc_oxili_ahb_clk>,
|
||||
<&clock_gcc clk_gcc_oxili_gmem_clk>,
|
||||
<&clock_gcc clk_gcc_bimc_gfx_clk>,
|
||||
<&clock_gcc clk_gcc_bimc_gpu_clk>;
|
||||
clock-names = "core_clk", "iface_clk", "mem_clk",
|
||||
"mem_iface_clk", "alt_mem_iface_clk";
|
||||
|
||||
/* Bus Scale Settings */
|
||||
qcom, gpu-bus-table {
|
||||
compatible="qcom,gpu-bus-table","qcom,gpu-bus-table-ddr7";
|
||||
qcom,msm-bus,name = "grp3d";
|
||||
qcom,msm-bus,num-cases = <4>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<26 512 0 0>,
|
||||
<26 512 0 1600000>,
|
||||
<26 512 0 3200000>,
|
||||
<26 512 0 4264000>;
|
||||
};
|
||||
|
||||
/* GDSC oxili regulators */
|
||||
vdd-supply = <&gdsc_oxili_gx>;
|
||||
vdd-parent-supply = <&VDD_GFX_LEVEL>;
|
||||
vdd-parent-min-corner = <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
|
||||
|
||||
nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>, <&gpu_model_bin>;
|
||||
nvmem-cell-names = "speed_bin", "gaming_bin","gpu_model";
|
||||
|
||||
/* IOMMU Data */
|
||||
iommu = <&gfx_iommu>;
|
||||
|
||||
/* Trace bus */
|
||||
coresight-id = <67>;
|
||||
coresight-name = "coresight-gfx";
|
||||
coresight-nr-inports = <0>;
|
||||
coresight-outports = <0>;
|
||||
coresight-child-list = <&funnel_in0>;
|
||||
coresight-child-ports = <5>;
|
||||
|
||||
/* Enable context aware freq. scaling */
|
||||
qcom,enable-ca-jump;
|
||||
|
||||
/* Context aware jump busy penalty in us */
|
||||
qcom,ca-busy-penalty = <12000>;
|
||||
|
||||
/* Context aware jump target power level */
|
||||
qcom,ca-target-pwrlevel = <1>;
|
||||
|
||||
qcom,soc-hw-revisions {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible="qcom,soc-hw-revisions";
|
||||
|
||||
qcom,soc-hw-revision@0 {
|
||||
reg = <0>;
|
||||
|
||||
qcom,chipid = <0x06010500>;
|
||||
qcom,gpu-quirk-hfi-use-reg;
|
||||
qcom,gpu-quirk-limit-uche-gbif-rw;
|
||||
};
|
||||
|
||||
qcom,soc-hw-revision@1 {
|
||||
reg = <1>;
|
||||
|
||||
qcom,chipid = <0x06010501>;
|
||||
qcom,gpu-quirk-hfi-use-reg;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-models {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible="qcom,gpu-models";
|
||||
|
||||
qcom,gpu-model@0 {
|
||||
compatible="qcom,adreno-gpu-a642l";
|
||||
qcom,gpu-model-id = <0>;
|
||||
qcom,gpu-model = "Adreno642Lv1";
|
||||
qcom,vk-device-id= <0x06030500>;
|
||||
};
|
||||
qcom,gpu-model@1 {
|
||||
compatible="qcom,adreno-gpu-a645";
|
||||
qcom,gpu-model-id = <190>;
|
||||
qcom,gpu-model = "Adreno645";
|
||||
qcom,vk-device-id= <0x06030500>;
|
||||
};
|
||||
}
|
||||
|
||||
/* GPU Mempools */
|
||||
qcom,gpu-mempools {
|
||||
#address-cells= <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-reserved = <2048>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-reserved = <1024>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevels-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <0>;
|
||||
qcom,ca-target-pwrlevel = <1>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <400000000>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,io-fraction = <33>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <310000000>;
|
||||
qcom,bus-freq = <2>;
|
||||
qcom,io-fraction = <66>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <200000000>;
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,io-fraction = <100>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <27000000>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,io-fraction = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
684
qcom/graphics/gpu/bengal-gpu.dtsi
Normal file
684
qcom/graphics/gpu/bengal-gpu.dtsi
Normal file
@@ -0,0 +1,684 @@
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
&msm_gpu {
|
||||
label = "kgsl-3d0";
|
||||
compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
|
||||
status = "ok";
|
||||
|
||||
reg = <0x5900000 0x90000>,
|
||||
<0x5961000 0x800>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "cx_dbgc";
|
||||
|
||||
interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
|
||||
qcom,id = <0>;
|
||||
qcom,chipid = <0x06010000>;
|
||||
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
|
||||
qcom,ubwc-mode = <1>;
|
||||
qcom,min-access-length = <64>;
|
||||
|
||||
/* base addr, size */
|
||||
qcom,gpu-qdss-stm = <0xe1c0000 0x40000>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_BIMC_GPU_AXI_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
||||
<&rpmcc RPM_SMD_QDSS_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
|
||||
|
||||
clock-names = "core_clk",
|
||||
"rbbmtimer_clk",
|
||||
"iface_clk",
|
||||
"ahb_clk",
|
||||
"mem_clk",
|
||||
"gmu_clk",
|
||||
"smmu_vote",
|
||||
"apb_pclk",
|
||||
"gpu_cc_ahb",
|
||||
"gcc_gpu_memnoc_gfx",
|
||||
"gpu_cc_hlos1_vote_gpu_smmu",
|
||||
"gcc_gpu_snoc_dvm_gfx";
|
||||
|
||||
interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
|
||||
interconnect-names = "gpu_icc_path";
|
||||
|
||||
qcom,bus-table-cnoc =
|
||||
<0>, /* Off */
|
||||
<100>; /* On */
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 8)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(100, 8)>, /* index=1 */
|
||||
<MHZ_TO_KBPS(200, 8)>, /* index=2 */
|
||||
<MHZ_TO_KBPS(300, 8)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(451, 8)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(547, 8)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(681, 8)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(768, 8)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(1017, 8)>, /* index=8 */
|
||||
<MHZ_TO_KBPS(1353, 8)>, /* index=9 */
|
||||
<MHZ_TO_KBPS(1555, 8)>, /* index=10 */
|
||||
<MHZ_TO_KBPS(1804, 8)>; /* index=11 */
|
||||
|
||||
|
||||
/* GDSC regulator names */
|
||||
regulator-names = "vddcx", "vdd";
|
||||
/* GDSC oxili regulators */
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
/* CPU latency parameter */
|
||||
qcom,pm-qos-active-latency = <422>;
|
||||
qcom,pm-qos-wakeup-latency = <422>;
|
||||
|
||||
/* Enable context aware freq. scaling */
|
||||
qcom,enable-ca-jump;
|
||||
/* Context aware jump busy penalty in us */
|
||||
qcom,ca-busy-penalty = <12000>;
|
||||
/* Context aware jump target power level */
|
||||
qcom,ca-target-pwrlevel = <5>;
|
||||
|
||||
nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
|
||||
nvmem-cell-names = "speed_bin", "gaming_bin";
|
||||
|
||||
qcom,gpu-cx-ipeak {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-cx-ipeak";
|
||||
|
||||
qcom,gpu-cx-ipeak@0 {
|
||||
qcom,gpu-cx-ipeak = <&cx_ipeak_lm 10>;
|
||||
qcom,gpu-cx-ipeak-freq = <950000000>;
|
||||
};
|
||||
|
||||
qcom,gpu-cx-ipeak@1 {
|
||||
qcom,gpu-cx-ipeak = <&cx_ipeak_lm 1>;
|
||||
qcom,gpu-cx-ipeak-freq = <900000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* ZAP Shader memory */
|
||||
zap-shader {
|
||||
memory-region = <&pil_gpu_mem>;
|
||||
};
|
||||
|
||||
/* GPU Mempools */
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
/* GPU Mempool configuration for low memory SKUs */
|
||||
qcom,gpu-mempools-lowmem {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools-lowmem";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-allocate;
|
||||
qcom,mempool-max-pages = <256>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-allocate;
|
||||
qcom,mempool-max-pages = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Speed-bin zero is default speed bin.
|
||||
* For rest of the speed bins, speed-bin value
|
||||
* is calculated as FMAX/4.8 MHz round up to zero
|
||||
* decimal places plus two margin to account for
|
||||
* clock jitters.
|
||||
*/
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevel-bins";
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
qcom,ca-target-pwrlevel = <5>;
|
||||
|
||||
/* TURBO_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <980000000>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
};
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <900000000>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
/* NOM_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <820000000>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <600000000>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <9>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <465000000>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <320000000>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <206>;
|
||||
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
qcom,ca-target-pwrlevel = <5>;
|
||||
|
||||
/* TURBO_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <980000000>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
};
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <900000000>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
/* NOM_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <820000000>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <600000000>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <9>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <465000000>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <320000000>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <200>;
|
||||
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
qcom,ca-target-pwrlevel = <5>;
|
||||
|
||||
/* TURBO_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <950000000>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
};
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <900000000>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
/* NOM_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <820000000>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <600000000>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <9>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <465000000>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <320000000>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <157>;
|
||||
|
||||
qcom,initial-pwrlevel = <3>;
|
||||
qcom,ca-target-pwrlevel = <2>;
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <600000000>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <465000000>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <320000000>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <127>;
|
||||
|
||||
qcom,initial-pwrlevel = <2>;
|
||||
qcom,ca-target-pwrlevel = <1>;
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <600000000>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <11>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <465000000>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <320000000>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&soc {
|
||||
gpu_opp_table: gpu-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-980000000 {
|
||||
opp-hz = /bits/ 64 <980000000>;
|
||||
opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
};
|
||||
|
||||
opp-950000000 {
|
||||
opp-hz = /bits/ 64 <950000000>;
|
||||
opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
};
|
||||
|
||||
opp-900000000 {
|
||||
opp-hz = /bits/ 64 <900000000>;
|
||||
opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
opp-820000000 {
|
||||
opp-hz = /bits/ 64 <820000000>;
|
||||
opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
opp-745000000 {
|
||||
opp-hz = /bits/ 64 <745000000>;
|
||||
opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
opp-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
opp-465000000 {
|
||||
opp-hz = /bits/ 64 <465000000>;
|
||||
opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
opp-320000000 {
|
||||
opp-hz = /bits/ 64 <320000000>;
|
||||
opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
};
|
||||
|
||||
gpu_bw_tbl: gpu-bw-tbl {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */
|
||||
|
||||
opp-100 { opp-hz = /bits/ 64 < 762 >; }; /* 1.100 MHz */
|
||||
|
||||
opp-200 { opp-hz = /bits/ 64 < 1525 >; }; /* 2.200 MHz */
|
||||
|
||||
opp-300 { opp-hz = /bits/ 64 < 2288 >; }; /* 3.300 MHz */
|
||||
|
||||
opp-451 { opp-hz = /bits/ 64 < 3440 >; }; /* 4.451 MHz */
|
||||
|
||||
opp-547 { opp-hz = /bits/ 64 < 4173 >; }; /* 5.547 MHz */
|
||||
|
||||
opp-681 { opp-hz = /bits/ 64 < 5195 >; }; /* 6.681 MHz */
|
||||
|
||||
opp-768 { opp-hz = /bits/ 64 < 5859 >; }; /* 7.768 MHz */
|
||||
|
||||
opp-1017 { opp-hz = /bits/ 64 < 7759 >; }; /* 8.1017 MHz */
|
||||
|
||||
opp-1353 { opp-hz = /bits/ 64 < 10322 >; }; /* 9.1353 MHz */
|
||||
|
||||
opp-1555 { opp-hz = /bits/ 64 < 11863 >; }; /* 10.1555 MHz */
|
||||
|
||||
opp-1804 { opp-hz = /bits/ 64 < 13763 >; }; /* 11.1804 MHz */
|
||||
};
|
||||
|
||||
gpubw: qcom,gpubw {
|
||||
compatible = "qcom,devbw";
|
||||
governor = "bw_vbif";
|
||||
qcom,src-dst-ports = <26 512>;
|
||||
operating-points-v2 = <&gpu_bw_tbl>;
|
||||
};
|
||||
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
|
||||
reg = <0x59a0000 0x10000>;
|
||||
qcom,protect = <0xa0000 0x10000>;
|
||||
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
qcom,retention;
|
||||
qcom,hyp_secure_alloc;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
label = "gfx3d_user";
|
||||
iommus = <&kgsl_smmu 0 1>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
qcom,gpu-offset = <0xa8000>;
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
label = "gfx3d_secure";
|
||||
iommus = <&kgsl_smmu 2 0>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
332
qcom/graphics/gpu/blair-gpu-pwrlevels.dtsi
Normal file
332
qcom/graphics/gpu/blair-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,332 @@
|
||||
&msm_gpu {
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-pwrlevel-bins";
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,speed-bin = <0>;
|
||||
qcom,ca-target-pwrlevel = <5>;
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
|
||||
/* TURBO_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <900000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <9>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
};
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <840000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <7>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
};
|
||||
|
||||
/* NOM_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <770000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <7>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <490000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <390000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7= <5>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <266000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <1>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,speed-bin = <190>;
|
||||
qcom,ca-target-pwrlevel = <5>;
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
|
||||
/* TURBO_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <900000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <9>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
};
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <840000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <7>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
};
|
||||
|
||||
/* NOM_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <770000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <7>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <490000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <390000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7= <5>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <266000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <1>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,speed-bin = <177>;
|
||||
qcom,ca-target-pwrlevel = <4>;
|
||||
qcom,initial-pwrlevel = <5>;
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <840000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <7>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
};
|
||||
|
||||
/* NOM_L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <770000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <7>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <490000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <390000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7= <5>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <266000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <1>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,speed-bin = <148>;
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
|
||||
|
||||
/* NOM_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <700000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <9>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <490000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <390000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7= <5>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <266000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <1>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
20
qcom/graphics/gpu/blair-gpu.dts
Normal file
20
qcom/graphics/gpu/blair-gpu.dts
Normal file
@@ -0,0 +1,20 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-blair.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-blair.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/interconnect/qcom,blair.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
#include "blair-gpu.dtsi"
|
||||
#include "blair-gpu-pwrlevels.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Blair";
|
||||
compatible = "qcom,blair";
|
||||
qcom,msm-id = <507 0x10000>, <578 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
130
qcom/graphics/gpu/blair-gpu.dtsi
Normal file
130
qcom/graphics/gpu/blair-gpu.dtsi
Normal file
@@ -0,0 +1,130 @@
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
&msm_gpu {
|
||||
compatible = "qcom,kgsl-3d0", "qcom,adreno-gpu-a619-holi";
|
||||
status = "ok";
|
||||
|
||||
reg = <0x5900000 0x40000>,
|
||||
<0x5961000 0x800>,
|
||||
<0x0596A000 0x30000>,
|
||||
<0x599E000 0x1000>;
|
||||
reg-names = "kgsl_3d0_reg_memory",
|
||||
"cx_dbgc",
|
||||
"gmu_wrapper",
|
||||
"cx_misc";
|
||||
|
||||
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_BIMC_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
|
||||
|
||||
clock-names = "core_clk",
|
||||
"rbbmtimer_clk",
|
||||
"iface_clk",
|
||||
"mem_clk",
|
||||
"gmu_clk",
|
||||
"gcc_gpu_memnoc_gfx";
|
||||
|
||||
interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>, <0 181 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq", "freq_limiter_irq";
|
||||
|
||||
resets = <&gpucc GPUCC_GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR>;
|
||||
reset-names = "freq_limiter_irq_clear";
|
||||
|
||||
nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
|
||||
nvmem-cell-names = "speed_bin", "gaming_bin";
|
||||
|
||||
qcom,chipid = <0x06010901>;
|
||||
qcom,gpu-model = "Adreno619v2";
|
||||
|
||||
regulator-names = "vddcx", "vdd";
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
vdd-parent-supply = <&S8A_LEVEL>;
|
||||
vdd-parent-min-corner = <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
|
||||
|
||||
qcom,gpu-quirk-secvid-set-once;
|
||||
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
qcom,ubwc-mode = <2>;
|
||||
|
||||
qcom,enable-ca-jump;
|
||||
|
||||
/* Context aware jump busy penalty in us */
|
||||
qcom,ca-busy-penalty = <12000>;
|
||||
|
||||
interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI>;
|
||||
interconnect-names = "gpu_icc_path";
|
||||
|
||||
qcom,bus-table-ddr7 =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(451, 4)>, /* index=1 (LOW SVS) */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=2(LOW SVS) */
|
||||
<MHZ_TO_KBPS(681, 4)>, /* index=3 (SVS) */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=4 (SVS) */
|
||||
<MHZ_TO_KBPS(1017, 4)>, /* index=5 (SVS) */
|
||||
<MHZ_TO_KBPS(1353, 4)>, /* index=6 (NOM) */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=7 (NOM) */
|
||||
<MHZ_TO_KBPS(1804, 4)>, /* index=8 (TURBO) */
|
||||
<MHZ_TO_KBPS(2092, 4)>; /* index=9 (TURBO_L1) */
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&pil_gpu_micro_code_mem>;
|
||||
};
|
||||
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@5940000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
reg = <0x5940000 0x10000>;
|
||||
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x0>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x2>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
153
qcom/graphics/gpu/cliffs-gpu-pwrlevels.dtsi
Normal file
153
qcom/graphics/gpu/cliffs-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,153 @@
|
||||
&msm_gpu {
|
||||
qcom,initial-pwrlevel = <10>;
|
||||
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
compatible="qcom,gpu-pwrlevels";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Turbo_L2 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1100000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xA02F5FFD>;
|
||||
};
|
||||
/* Turbo_L1*/
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <1000000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xA02F5FFD>;
|
||||
};
|
||||
|
||||
/* Turbo_L0 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <950000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L0>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xA8285FFD>;
|
||||
};
|
||||
|
||||
/* Turbo */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <900000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xA8285FFD>;
|
||||
};
|
||||
|
||||
/* Nom_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <835000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xA8285FFD>;
|
||||
};
|
||||
|
||||
/* Nom */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <736000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
qcom,acd-level = <0x88295FFD>;
|
||||
};
|
||||
|
||||
/* SVS_L2 */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <684000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
qcom,acd-level = <0x88295FFD>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <633000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
qcom,acd-level = <0x88295FFD>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0xA8295FFD>;
|
||||
};
|
||||
|
||||
/* Low_SVS */
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <353000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0x882C5FFD>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D1 */
|
||||
qcom,gpu-pwrlevel@10 {
|
||||
reg = <10>;
|
||||
qcom,gpu-freq = <255000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0x882F5FFD>;
|
||||
};
|
||||
};
|
||||
};
|
||||
20
qcom/graphics/gpu/cliffs-gpu.dts
Normal file
20
qcom/graphics/gpu/cliffs-gpu.dts
Normal file
@@ -0,0 +1,20 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-cliffs.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-cliffs.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,cliffs.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
|
||||
#include "cliffs-gpu.dtsi"
|
||||
#include "cliffs-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Cliffs";
|
||||
compatible = "qcom,cliffs", "qcom,cliffsp";
|
||||
qcom,msm-id = <614 0x10000>, <642 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
215
qcom/graphics/gpu/cliffs-gpu.dtsi
Normal file
215
qcom/graphics/gpu/cliffs-gpu.dtsi
Normal file
@@ -0,0 +1,215 @@
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
&msm_gpu {
|
||||
compatible = "qcom,adreno-gpu-gen7-11-0", "qcom,kgsl-3d0";
|
||||
status = "ok";
|
||||
|
||||
reg = <0x3d00000 0x40000>, <0x3d50000 0x10000>,
|
||||
<0x3d61000 0x800>, <0x3d9e000 0x1000>,
|
||||
<0x10048000 0x8000>, <0x10900000 0x80000>,
|
||||
<0x10b05000 0x1000>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc",
|
||||
"cx_misc", "qdss_etr", "qdss_gfx", "qdss_tmc";
|
||||
|
||||
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
|
||||
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&aoss_qmp QDSS_CLK>;
|
||||
clock-names = "gcc_gpu_memnoc_gfx",
|
||||
"gcc_gpu_snoc_dvm_gfx",
|
||||
"gpu_cc_ahb",
|
||||
"apb_pclk";
|
||||
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
qcom,ubwc-mode = <4>;
|
||||
|
||||
qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
|
||||
|
||||
qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3";
|
||||
|
||||
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "gpu_icc_path";
|
||||
|
||||
qcom,bus-table-cnoc =
|
||||
<0>, /* Off */
|
||||
<100>; /* On */
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(547, 4) >, /* index=1 */
|
||||
<MHZ_TO_KBPS(768, 4) >, /* index=2 */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(1708, 4)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(2092, 4)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(2736, 4)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(3187, 4)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(3686, 4)>, /* index=8 */
|
||||
<MHZ_TO_KBPS(4224, 4)>; /* index=9 */
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&gpu_microcode_mem>;
|
||||
};
|
||||
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-reserved = <2048>;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-reserved = <1024>;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 128K Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <131072>;
|
||||
qcom,mempool-reserved = <128>;
|
||||
};
|
||||
/* 256K Page Pool configuration */
|
||||
qcom,gpu-mempool@4 {
|
||||
reg = <4>;
|
||||
qcom,mempool-page-size = <262144>;
|
||||
qcom,mempool-reserved = <80>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@5 {
|
||||
reg = <5>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
reg = <0x3da0000 0x40000>;
|
||||
|
||||
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x0 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x2 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gmu: qcom,gmu@3d69000 {
|
||||
compatible = "qcom,gen7-gmu";
|
||||
|
||||
reg = <0x3d68000 0x37000>,
|
||||
<0xb280000 0x10000>,
|
||||
<0x3d40000 0x10000>;
|
||||
|
||||
reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
|
||||
|
||||
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hfi", "gmu";
|
||||
|
||||
regulator-names = "vddcx", "vdd";
|
||||
|
||||
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
||||
vdd-supply = <&gpu_cc_gx_gdsc>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gpucc GPU_CC_HUB_CX_INT_CLK>;
|
||||
|
||||
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
|
||||
"memnoc_clk", "ahb_clk", "hub_clk";
|
||||
|
||||
qcom,gmu-freq-table = <220000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
|
||||
<550000000 RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
iommus = <&kgsl_smmu 0x5 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
|
||||
mboxes = <&qmp_aop 0>;
|
||||
mbox-names = "aop";
|
||||
|
||||
qcom,ipc-core = <0x00400000 0x140000>;
|
||||
};
|
||||
|
||||
coresight_cx_dgbc: qcom,gpu-coresight-cx {
|
||||
compatible = "qcom,gpu-coresight-cx";
|
||||
|
||||
coresight-name = "coresight-gfx-cx";
|
||||
coresight-atid = <52>;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
cx_dbgc_out_funnel_gfx: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_gfx_in_cx_dbgc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
coresight_gx_dgbc: qcom,gpu-coresight-gx {
|
||||
compatible = "qcom,gpu-coresight-gx";
|
||||
|
||||
coresight-name = "coresight-gfx";
|
||||
coresight-atid = <53>;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
gx_dbgc_out_funnel_gfx: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_gfx_in_gx_dbgc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&funnel_gfx {
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
funnel_gfx_in_gx_dbgc: endpoint {
|
||||
remote-endpoint =
|
||||
<&gx_dbgc_out_funnel_gfx>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
funnel_gfx_in_cx_dbgc: endpoint {
|
||||
remote-endpoint =
|
||||
<&cx_dbgc_out_funnel_gfx>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
127
qcom/graphics/gpu/cliffs7-gpu-pwrlevels.dtsi
Normal file
127
qcom/graphics/gpu/cliffs7-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,127 @@
|
||||
&msm_gpu {
|
||||
qcom,initial-pwrlevel = <8>;
|
||||
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
compatible="qcom,gpu-pwrlevels";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Turbo_L0*/
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <950000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L0>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xA8285FFD>;
|
||||
};
|
||||
/* Turbo */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <900000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xA8285FFD>;
|
||||
};
|
||||
|
||||
/* Nom_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <835000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xA8285FFD>;
|
||||
};
|
||||
|
||||
/* Nom */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <736000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
qcom,acd-level = <0x88295FFD>;
|
||||
};
|
||||
|
||||
/* SVS_L2 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <684000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
qcom,acd-level = <0x88295FFD>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <633000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
qcom,acd-level = <0x88295FFD>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0xA8295FFD>;
|
||||
};
|
||||
|
||||
/* Low_SVS */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <353000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0x882C5FFD>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D1 */
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <255000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0x882F5FFD>;
|
||||
};
|
||||
};
|
||||
};
|
||||
20
qcom/graphics/gpu/cliffs7-gpu.dts
Normal file
20
qcom/graphics/gpu/cliffs7-gpu.dts
Normal file
@@ -0,0 +1,20 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-cliffs.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-cliffs.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,cliffs.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
|
||||
#include "cliffs-gpu.dtsi"
|
||||
#include "cliffs7-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Cliffs 7";
|
||||
compatible = "qcom,cliffs", "qcom,cliffsp";
|
||||
qcom,msm-id = <632 0x10000>, <643 0x10000>, <700 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
196
qcom/graphics/gpu/holi-gpu-pwrlevels.dtsi
Normal file
196
qcom/graphics/gpu/holi-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,196 @@
|
||||
&msm_gpu {
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-pwrlevel-bins";
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,speed-bin = <0>;
|
||||
qcom,ca-target-pwrlevel = <5>;
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
|
||||
/* TURBO_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <875000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <9>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
};
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <800000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <7>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
};
|
||||
|
||||
/* NOM_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <7>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <565000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <430000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <355000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7= <5>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <253000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <1>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,speed-bin = <138>;
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
|
||||
/* NOM_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <7>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <565000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <430000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <355000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7= <5>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <253000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <1>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,speed-bin = <92>;
|
||||
qcom,ca-target-pwrlevel = <1>;
|
||||
qcom,initial-pwrlevel = <2>;
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <430000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <355000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7= <5>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <253000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <1>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
21
qcom/graphics/gpu/holi-gpu.dts
Normal file
21
qcom/graphics/gpu/holi-gpu.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-holi.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-holi.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/interconnect/qcom,holi.h>
|
||||
#include <dt-bindings/interconnect/qcom,icc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
#include "holi-gpu.dtsi"
|
||||
#include "holi-gpu-pwrlevels.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Holi SoC";
|
||||
compatible = "qcom,holi";
|
||||
qcom,msm-id = <454 0x10000>, <472 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
131
qcom/graphics/gpu/holi-gpu.dtsi
Normal file
131
qcom/graphics/gpu/holi-gpu.dtsi
Normal file
@@ -0,0 +1,131 @@
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
&msm_gpu {
|
||||
compatible = "qcom,kgsl-3d0", "qcom,adreno-gpu-a619-holi";
|
||||
status = "ok";
|
||||
|
||||
reg = <0x5900000 0x40000>,
|
||||
<0x5961000 0x800>,
|
||||
<0x596A000 0x30000>,
|
||||
<0x599E000 0x1000>;
|
||||
reg-names = "kgsl_3d0_reg_memory",
|
||||
"cx_dbgc",
|
||||
"gmu_wrapper",
|
||||
"cx_misc";
|
||||
|
||||
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_BIMC_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
|
||||
clock-names = "core_clk",
|
||||
"rbbmtimer_clk",
|
||||
"iface_clk",
|
||||
"mem_clk",
|
||||
"gmu_clk",
|
||||
"gcc_gpu_memnoc_gfx";
|
||||
|
||||
interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>, <0 181 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq", "freq_limiter_irq";
|
||||
|
||||
resets = <&gpucc GPUCC_GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR>;
|
||||
reset-names = "freq_limiter_irq_clear";
|
||||
|
||||
nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
|
||||
nvmem-cell-names = "speed_bin", "gaming_bin";
|
||||
|
||||
qcom,chipid = <0x06010900>;
|
||||
qcom,gpu-model = "Adreno619v1";
|
||||
|
||||
regulator-names = "vddcx", "vdd";
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
vdd-parent-supply = <&S3A_LEVEL>;
|
||||
vdd-parent-min-corner = <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
|
||||
|
||||
qcom,gpu-quirk-secvid-set-once;
|
||||
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
qcom,ubwc-mode = <2>;
|
||||
|
||||
/* Enable context aware freq. scaling */
|
||||
qcom,enable-ca-jump;
|
||||
|
||||
/* Context aware jump busy penalty in us */
|
||||
qcom,ca-busy-penalty = <12000>;
|
||||
|
||||
interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI>;
|
||||
interconnect-names = "gpu_icc_path";
|
||||
|
||||
qcom,bus-table-ddr7 =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(451, 4)>, /* index=1 (LOW SVS) */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=2 (LOW SVS) */
|
||||
<MHZ_TO_KBPS(681, 4)>, /* index=3 (SVS) */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=4 (SVS) */
|
||||
<MHZ_TO_KBPS(1017, 4)>, /* index=5 (SVS) */
|
||||
<MHZ_TO_KBPS(1353, 4)>, /* index=6 (NOM) */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=7 (NOM) */
|
||||
<MHZ_TO_KBPS(1804, 4)>, /* index=8 (TURBO) */
|
||||
<MHZ_TO_KBPS(2092, 4)>; /* index=9 (TURBO_L1) */
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&pil_gpu_microcode_mem>;
|
||||
};
|
||||
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@5940000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
reg = <0x5940000 0x10000>;
|
||||
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x0>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x2>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
229
qcom/graphics/gpu/kalama-gpu-pwrlevels.dtsi
Normal file
229
qcom/graphics/gpu/kalama-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,229 @@
|
||||
&msm_gpu {
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
compatible="qcom,gpu-pwrlevel-bins";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AC)
|
||||
SKU_CODE(PCODE_UNKNOWN, FC_AF)
|
||||
SKU_CODE(PCODE_2, FC_Y0)
|
||||
SKU_CODE(PCODE_2, FC_Y2)
|
||||
SKU_CODE(PCODE_4, FC_Y0)
|
||||
SKU_CODE(PCODE_4, FC_Y2)
|
||||
SKU_CODE(PCODE_6, FC_Y0)
|
||||
SKU_CODE(PCODE_6, FC_Y1)
|
||||
SKU_CODE(PCODE_6, FC_YD)
|
||||
SKU_CODE(PCODE_6, FC_YE)>;
|
||||
|
||||
qcom,initial-pwrlevel = <9>;
|
||||
qcom,initial-min-pwrlevel = <9>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <746000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882b5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <719000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0x882b5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <680000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0x882c5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <615000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0x882c5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <550000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0xa82d5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <475000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0xa82d5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <401000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <348000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <295000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0xc02c5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <220000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@10 {
|
||||
reg = <10>;
|
||||
qcom,gpu-freq = <124800000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
|
||||
|
||||
qcom,initial-pwrlevel = <5>;
|
||||
qcom,initial-min-pwrlevel = <5>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <550000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa82d5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <475000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0xa82d5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <401000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <348000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <295000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0xc02c5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <220000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <124800000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
22
qcom/graphics/gpu/kalama-gpu.dts
Normal file
22
qcom/graphics/gpu/kalama-gpu.dts
Normal file
@@ -0,0 +1,22 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-kalama.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-kalama.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,kalama.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "kalama-gpu.dtsi"
|
||||
#include "kalama-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama";
|
||||
compatible = "qcom,kalama";
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
|
||||
264
qcom/graphics/gpu/kalama-gpu.dtsi
Normal file
264
qcom/graphics/gpu/kalama-gpu.dtsi
Normal file
@@ -0,0 +1,264 @@
|
||||
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
/* External feature codes */
|
||||
#define FC_UNKNOWN 0x0
|
||||
#define FC_AA 0x1
|
||||
#define FC_AB 0x2
|
||||
#define FC_AC 0x3
|
||||
#define FC_AD 0x4
|
||||
#define FC_AE 0x5
|
||||
#define FC_AF 0x6
|
||||
#define FC_AG 0x7
|
||||
#define FC_AH 0x8
|
||||
|
||||
/* Internal feature codes */
|
||||
#define FC_Y0 0x00f1
|
||||
#define FC_Y1 0x00f2
|
||||
#define FC_Y2 0x00f3
|
||||
#define FC_Y3 0x00f4
|
||||
#define FC_Y4 0x00f5
|
||||
#define FC_Y5 0x00f6
|
||||
#define FC_Y6 0x00f7
|
||||
#define FC_Y7 0x00f8
|
||||
#define FC_Y8 0x00f9
|
||||
#define FC_Y9 0x00fa
|
||||
#define FC_YA 0x00fb
|
||||
#define FC_YB 0x00fc
|
||||
#define FC_YC 0x00fd
|
||||
#define FC_YD 0x00fe
|
||||
#define FC_YE 0x00ff
|
||||
#define FC_YF 0x0100
|
||||
|
||||
/* Pcodes */
|
||||
#define PCODE_UNKNOWN 0
|
||||
#define PCODE_0 1
|
||||
#define PCODE_1 2
|
||||
#define PCODE_2 3
|
||||
#define PCODE_3 4
|
||||
#define PCODE_4 5
|
||||
#define PCODE_5 6
|
||||
#define PCODE_6 7
|
||||
#define PCODE_7 8
|
||||
#define PCODE_8 9
|
||||
|
||||
#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode)
|
||||
|
||||
&msm_gpu {
|
||||
compatible = "qcom,adreno-gpu-gen7-2-0", "qcom,kgsl-3d0";
|
||||
status = "ok";
|
||||
reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
|
||||
<0x03d50000 0x10000>, <0x3d8b000 0x2000>,
|
||||
<0x03d9e000 0x1000>, <0x10900000 0x80000>,
|
||||
<0x10048000 0x8000>, <0x10b05000 0x1000>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
|
||||
"isense_cntl", "cx_misc", "qdss_gfx", "qdss_etr",
|
||||
"qdss_tmc";
|
||||
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
|
||||
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&aoss_qmp QDSS_CLK>;
|
||||
clock-names = "gcc_gpu_memnoc_gfx",
|
||||
"gcc_gpu_snoc_dvm_gfx",
|
||||
"gpu_cc_ahb", "apb_pclk";
|
||||
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
qcom,ubwc-mode = <4>;
|
||||
|
||||
qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
|
||||
|
||||
qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3",
|
||||
"gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7";
|
||||
|
||||
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "gpu_icc_path";
|
||||
|
||||
qcom,bus-table-cnoc =
|
||||
<0>, /* Off */
|
||||
<100>; /* On */
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(547, 4) >, /* index=1 */
|
||||
<MHZ_TO_KBPS(768, 4) >, /* index=2 */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(1708, 4)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(2092, 4)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(2736, 4)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(3187, 4)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(3686, 4)>, /* index=8 */
|
||||
<MHZ_TO_KBPS(4224, 4)>; /* index=9 */
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&gpu_micro_code_mem>;
|
||||
};
|
||||
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-reserved = <2048>;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-reserved = <1024>;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 128K Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <131072>;
|
||||
qcom,mempool-reserved = <128>;
|
||||
};
|
||||
/* 256K Page Pool configuration */
|
||||
qcom,gpu-mempool@4 {
|
||||
reg = <4>;
|
||||
qcom,mempool-page-size = <262144>;
|
||||
qcom,mempool-reserved = <80>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@5 {
|
||||
reg = <5>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
reg = <0x03da0000 0x40000>;
|
||||
|
||||
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x0 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_lpac: gfx3d_lpac {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x1 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x2 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gmu: qcom,gmu@3d69000 {
|
||||
compatible = "qcom,gen7-gmu";
|
||||
|
||||
reg = <0x3d68000 0x37000>,
|
||||
<0xb280000 0x10000>,
|
||||
<0x03D40000 0x10000>;
|
||||
|
||||
reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
|
||||
|
||||
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hfi", "gmu";
|
||||
|
||||
regulator-names = "vddcx", "vdd";
|
||||
|
||||
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
||||
vdd-supply = <&gpu_cc_gx_gdsc>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gpucc GPU_CC_HUB_CX_INT_CLK>;
|
||||
|
||||
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
|
||||
"memnoc_clk", "ahb_clk", "hub_clk";
|
||||
|
||||
qcom,gmu-freq-table = <220000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
|
||||
<550000000 RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
iommus = <&kgsl_smmu 0x5 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
|
||||
mboxes = <&qmp_aop 0>;
|
||||
mbox-names = "aop";
|
||||
|
||||
qcom,ipc-core = <0x00400000 0xfc000>;
|
||||
};
|
||||
|
||||
coresight_cx_dgbc: qcom,gpu-coresight-cx {
|
||||
compatible = "qcom,gpu-coresight-cx";
|
||||
|
||||
coresight-name = "coresight-gfx-cx";
|
||||
coresight-atid = <52>;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
cx_dbgc_out_funnel_gfx: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_gfx_in_cx_dbgc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
coresight_gx_dgbc: qcom,gpu-coresight-gx {
|
||||
compatible = "qcom,gpu-coresight-gx";
|
||||
|
||||
coresight-name = "coresight-gfx";
|
||||
coresight-atid = <53>;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
gx_dbgc_out_funnel_gfx: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_gfx_in_gx_dbgc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&funnel_gfx {
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
funnel_gfx_in_gx_dbgc: endpoint {
|
||||
remote-endpoint =
|
||||
<&gx_dbgc_out_funnel_gfx>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
funnel_gfx_in_cx_dbgc: endpoint {
|
||||
remote-endpoint =
|
||||
<&cx_dbgc_out_funnel_gfx>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
191
qcom/graphics/gpu/kalama-hhg-gpu-pwrlevels.dtsi
Normal file
191
qcom/graphics/gpu/kalama-hhg-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,191 @@
|
||||
&msm_gpu {
|
||||
qcom,initial-pwrlevel = <13>;
|
||||
qcom,initial-min-pwrlevel = <13>;
|
||||
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1000000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882d5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <860000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882d5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <827000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa82d5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <794000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa82d5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <746000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <719000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <680000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <615000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0xa82f5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <550000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0xe0285ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <475000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <0xe0285ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@10 {
|
||||
reg = <10>;
|
||||
qcom,gpu-freq = <401000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <4>;
|
||||
|
||||
qcom,acd-level = <0xc02a5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@11 {
|
||||
reg = <11>;
|
||||
qcom,gpu-freq = <348000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0xe02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@12 {
|
||||
reg = <12>;
|
||||
qcom,gpu-freq = <295000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0xe02d5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@13 {
|
||||
reg = <13>;
|
||||
qcom,gpu-freq = <220000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0xc02f5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@14 {
|
||||
reg = <14>;
|
||||
qcom,gpu-freq = <124800000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
118
qcom/graphics/gpu/kalama-iot-gpu-pwrlevels.dtsi
Normal file
118
qcom/graphics/gpu/kalama-iot-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,118 @@
|
||||
&msm_gpu {
|
||||
qcom,initial-pwrlevel = <7>;
|
||||
qcom,initial-min-pwrlevel = <7>;
|
||||
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <680000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <615000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa82f5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <550000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0xe0285ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <475000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <0xe0285ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <401000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <4>;
|
||||
|
||||
qcom,acd-level = <0xc02a5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <348000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0xe02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <295000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0xe02d5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <220000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0xc02f5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <124800000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
21
qcom/graphics/gpu/kalama-iot-gpu.dts
Normal file
21
qcom/graphics/gpu/kalama-iot-gpu.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-kalama.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-kalama.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,kalama.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "kalama-v2-gpu.dtsi"
|
||||
#include "kalama-iot-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama v2";
|
||||
compatible = "qcom,kalama", "qcom,kalamap";
|
||||
qcom,msm-id = <603 0x20000>, <604 0x20000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
248
qcom/graphics/gpu/kalama-v2-gpu-pwrlevels.dtsi
Normal file
248
qcom/graphics/gpu/kalama-v2-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,248 @@
|
||||
&msm_gpu {
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
compatible="qcom,gpu-pwrlevel-bins";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AC)
|
||||
SKU_CODE(PCODE_UNKNOWN, FC_AF)
|
||||
SKU_CODE(PCODE_2, FC_Y0)
|
||||
SKU_CODE(PCODE_2, FC_Y2)
|
||||
SKU_CODE(PCODE_4, FC_Y0)
|
||||
SKU_CODE(PCODE_4, FC_Y2)
|
||||
SKU_CODE(PCODE_6, FC_Y0)
|
||||
SKU_CODE(PCODE_6, FC_Y1)
|
||||
SKU_CODE(PCODE_6, FC_YD)
|
||||
SKU_CODE(PCODE_6, FC_YE)>;
|
||||
|
||||
qcom,initial-pwrlevel = <8>;
|
||||
qcom,initial-min-pwrlevel = <8>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <719000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <680000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <615000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0xa82f5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <550000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0xe0285ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <475000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <0xe0285ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <401000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <4>;
|
||||
|
||||
qcom,acd-level = <0xc02a5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <348000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0xe02b5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <295000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0xe02d5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <220000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0xc02f5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <124800000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
|
||||
|
||||
qcom,initial-pwrlevel = <7>;
|
||||
qcom,initial-min-pwrlevel = <7>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <680000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <615000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa82f5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <550000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <0xe0285ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <475000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <0xe0285ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <401000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <4>;
|
||||
|
||||
qcom,acd-level = <0xc02a5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <348000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0xe02b5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <295000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0xe02d5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <220000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <0xc02f5ffd>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <124800000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
22
qcom/graphics/gpu/kalama-v2-gpu.dts
Normal file
22
qcom/graphics/gpu/kalama-v2-gpu.dts
Normal file
@@ -0,0 +1,22 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-kalama.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-kalama.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,kalama.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "kalama-v2-gpu.dtsi"
|
||||
#include "kalama-v2-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama v2";
|
||||
compatible = "qcom,kalama";
|
||||
qcom,msm-id = <519 0x20000>, <536 0x20000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
|
||||
5
qcom/graphics/gpu/kalama-v2-gpu.dtsi
Normal file
5
qcom/graphics/gpu/kalama-v2-gpu.dtsi
Normal file
@@ -0,0 +1,5 @@
|
||||
#include "kalama-gpu.dtsi"
|
||||
|
||||
&msm_gpu {
|
||||
compatible = "qcom,adreno-gpu-gen7-2-1", "qcom,kgsl-3d0";
|
||||
};
|
||||
22
qcom/graphics/gpu/kalamap-hhg-gpu.dts
Normal file
22
qcom/graphics/gpu/kalamap-hhg-gpu.dts
Normal file
@@ -0,0 +1,22 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-kalama.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-kalama.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,kalama.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "kalama-v2-gpu.dtsi"
|
||||
#include "kalama-hhg-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama HHG";
|
||||
compatible = "qcom,kalamap-hhg";
|
||||
qcom,msm-id = <600 0x20000>, <601 0x20000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
|
||||
23
qcom/graphics/gpu/khaje-gpu.dts
Normal file
23
qcom/graphics/gpu/khaje-gpu.dts
Normal file
@@ -0,0 +1,23 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-khaje.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-khaje.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-khaje.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interconnect/qcom,bengal.h>
|
||||
#include <dt-bindings/soc/qcom,dcc_v2.h>
|
||||
|
||||
#include "khaje-gpu.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Khaje SoC";
|
||||
compatible = "qcom,khaje", "qcom,khaje-qrd",
|
||||
"qcom,khaje-atp", "qcom,khaje-idp";
|
||||
qcom,msm-id = <518 0x10000>, <586 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
|
||||
270
qcom/graphics/gpu/khaje-gpu.dtsi
Normal file
270
qcom/graphics/gpu/khaje-gpu.dtsi
Normal file
@@ -0,0 +1,270 @@
|
||||
#include "bengal-gpu.dtsi"
|
||||
|
||||
&msm_gpu {
|
||||
qcom,chipid = <0x06010001>;
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 8)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(200, 8)>, /* index=1 */
|
||||
<MHZ_TO_KBPS(547, 8)>, /* index=2 */
|
||||
<MHZ_TO_KBPS(768, 8)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(1017, 8)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(1555, 8)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(1804, 8)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(2092, 8)>; /* index=7 */
|
||||
|
||||
/delete-node/ qcom,gpu-pwrlevel-bins;
|
||||
/*
|
||||
* Speed-bin zero is default speed bin.
|
||||
* For rest of the speed bins, speed-bin value
|
||||
* is calculated as FMAX/4.8 MHz round up to zero
|
||||
* decimal places plus two margin to account for
|
||||
* clock jitters.
|
||||
*/
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevel-bins";
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
qcom,ca-target-pwrlevel = <5>;
|
||||
|
||||
/* TURBO_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1260000000>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <7>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
};
|
||||
|
||||
/* TURBO_L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <1114800000>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <7>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
};
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <1025000000>;
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <7>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <785000000>;
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <5>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <600000000>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <465000000>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <4>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <320000000>;
|
||||
qcom,bus-freq = <2>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <2>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <235>;
|
||||
|
||||
qcom,initial-pwrlevel = <5>;
|
||||
qcom,ca-target-pwrlevel = <4>;
|
||||
|
||||
/* TURBO_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1114800000>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <7>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
};
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <1025000000>;
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <7>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <785000000>;
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <5>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <600000000>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <465000000>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <4>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <320000000>;
|
||||
qcom,bus-freq = <2>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <2>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <216>;
|
||||
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1025000000>;
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <7>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <785000000>;
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <5>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <600000000>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <465000000>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <4>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <320000000>;
|
||||
qcom,bus-freq = <2>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <2>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
23
qcom/graphics/gpu/khajeg-gpu.dts
Normal file
23
qcom/graphics/gpu/khajeg-gpu.dts
Normal file
@@ -0,0 +1,23 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-khaje.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-khaje.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-khaje.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interconnect/qcom,bengal.h>
|
||||
#include <dt-bindings/soc/qcom,dcc_v2.h>
|
||||
|
||||
#include "khaje-gpu.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Khajeg SoC";
|
||||
compatible = "qcom,khajeg", "qcom,khajeg-qrd",
|
||||
"qcom,khajeg-atp", "qcom,khajeg-idp";
|
||||
qcom,msm-id = <585 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
|
||||
23
qcom/graphics/gpu/khajep-gpu.dts
Normal file
23
qcom/graphics/gpu/khajep-gpu.dts
Normal file
@@ -0,0 +1,23 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-khaje.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-khaje.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-khaje.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interconnect/qcom,bengal.h>
|
||||
#include <dt-bindings/soc/qcom,dcc_v2.h>
|
||||
|
||||
#include "khaje-gpu.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Khajep SoC";
|
||||
compatible = "qcom,khajep", "qcom,khajep-qrd",
|
||||
"qcom,khajep-atp", "qcom,khajep-idp";
|
||||
qcom,msm-id = <561 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
|
||||
23
qcom/graphics/gpu/khajeq-gpu.dts
Normal file
23
qcom/graphics/gpu/khajeq-gpu.dts
Normal file
@@ -0,0 +1,23 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-khaje.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-khaje.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-khaje.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interconnect/qcom,bengal.h>
|
||||
#include <dt-bindings/soc/qcom,dcc_v2.h>
|
||||
|
||||
#include "khaje-gpu.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Khajeq SoC";
|
||||
compatible = "qcom,khajeq", "qcom,khajeq-qrd",
|
||||
"qcom,khajeq-atp", "qcom,khajeq-idp";
|
||||
qcom,msm-id = <562 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
|
||||
18
qcom/graphics/gpu/kona-gpu.dts
Normal file
18
qcom/graphics/gpu/kona-gpu.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/interconnect/qcom,kona.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "kona-gpu.dtsi"
|
||||
|
||||
/{
|
||||
model = "Qualcomm Technologies, Inc. Kona-iot";
|
||||
compatible = "qcom,kona", "qcom,kona-iot";
|
||||
qcom,msm-id = <356 0x10000>, <455 0x0>, <481 0x0>,
|
||||
<496 0x0>, <598 0x0>, <599 0x0>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
240
qcom/graphics/gpu/kona-gpu.dtsi
Normal file
240
qcom/graphics/gpu/kona-gpu.dtsi
Normal file
@@ -0,0 +1,240 @@
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
&msm_gpu {
|
||||
compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
|
||||
status = "ok";
|
||||
reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
|
||||
<0x3de0000 0x10000>, <0x3d8b000 0x2000>,
|
||||
<0x06900000 0x80000>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
|
||||
"isense_cntl", "qdss_gfx";
|
||||
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
|
||||
qcom,chipid = <0x06050000>;
|
||||
|
||||
qcom,initial-pwrlevel = <2>;
|
||||
|
||||
qcom,no-nap;
|
||||
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
qcom,ubwc-mode = <4>;
|
||||
|
||||
qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
|
||||
|
||||
#cooling-cells = <2>;
|
||||
|
||||
qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";
|
||||
|
||||
clocks = <&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
|
||||
|
||||
clock-names = "rbbmtimer_clk",
|
||||
"mem_clk",
|
||||
"mem_iface_clk",
|
||||
"gmu_clk",
|
||||
"gpu_cc_ahb",
|
||||
"gcc_gpu_memnoc_gfx",
|
||||
"gcc_gpu_snoc_dvm_gfx";
|
||||
|
||||
qcom,isense-clk-on-level = <1>;
|
||||
|
||||
/* GDSC regulator names */
|
||||
regulator-names = "vddcx", "vdd";
|
||||
/* GDSC oxili regulators */
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
nvmem-cells = <&gpu_lm_efuse>, <&gpu_speed_bin>;
|
||||
nvmem-cell-names = "isense_slope", "speed_bin";
|
||||
|
||||
interconnect-names = "gpu_icc_path";
|
||||
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
|
||||
|
||||
/* bus table */
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(200, 4)>, /* index=1 */
|
||||
<MHZ_TO_KBPS(300, 4)>, /* index=2 */
|
||||
<MHZ_TO_KBPS(451, 4)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(681, 4)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(1017, 4)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=8 */
|
||||
<MHZ_TO_KBPS(1804, 4)>, /* index=9 */
|
||||
<MHZ_TO_KBPS(2092, 4)>, /* index=10 */
|
||||
<MHZ_TO_KBPS(2736, 4)>; /* index=11 */
|
||||
|
||||
qcom,bus-table-cnoc =
|
||||
<0>, /* Off */
|
||||
<100>; /* On */
|
||||
|
||||
qcom,l3-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,l3-pwrlevels";
|
||||
|
||||
qcom,l3-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,l3-freq = <0>;
|
||||
};
|
||||
|
||||
qcom,l3-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,l3-freq = <864000000>;
|
||||
};
|
||||
|
||||
qcom,l3-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,l3-freq = <1344000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* ZAP Shader memory */
|
||||
zap-shader {
|
||||
memory-region = <&pil_gpu_mem>;
|
||||
};
|
||||
|
||||
/* GPU Mempools */
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-reserved = <2048>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-reserved = <1024>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <480000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <381000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <290000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <2>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
|
||||
reg = <0x03da0000 0x10000>;
|
||||
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x0 0x401>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x2 0x400>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
gmu: qcom,gmu@3d6a000 {
|
||||
compatible = "qcom,gpu-gmu";
|
||||
|
||||
reg = <0x3d6a000 0x30000>,
|
||||
<0xb290000 0x10000>,
|
||||
<0xb490000 0x10000>;
|
||||
reg-names = "kgsl_gmu_reg",
|
||||
"kgsl_gmu_pdc_cfg",
|
||||
"kgsl_gmu_pdc_seq";
|
||||
|
||||
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";
|
||||
|
||||
iommus = <&kgsl_smmu 0x5 0x400>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
|
||||
regulator-names = "vddcx", "vdd";
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>;
|
||||
|
||||
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
|
||||
"memnoc_clk", "gpu_cc_ahb";
|
||||
|
||||
/* AOP mailbox for sending ACD enable and disable messages */
|
||||
mboxes = <&qmp_aop 0>;
|
||||
mbox-names = "aop";
|
||||
};
|
||||
};
|
||||
17
qcom/graphics/gpu/kona-v2-gpu.dts
Normal file
17
qcom/graphics/gpu/kona-v2-gpu.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/interconnect/qcom,kona.h>
|
||||
#include "kona-v2-gpu.dtsi"
|
||||
|
||||
/{
|
||||
model = "Qualcomm Technologies, Inc. kona-iot v2";
|
||||
compatible = "qcom,kona", "qcom,kona-iot";
|
||||
qcom,msm-id = <356 0x20000>, <481 0x20000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
446
qcom/graphics/gpu/kona-v2-gpu.dtsi
Normal file
446
qcom/graphics/gpu/kona-v2-gpu.dtsi
Normal file
@@ -0,0 +1,446 @@
|
||||
#include "kona-gpu.dtsi"
|
||||
|
||||
&msm_gpu {
|
||||
qcom,chipid = <0x06050001>;
|
||||
|
||||
/delete-property/qcom,initial-pwrlevel;
|
||||
/delete-node/qcom,gpu-pwrlevels;
|
||||
|
||||
/* Power levels bins */
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
compatible="qcom,gpu-pwrlevel-bins";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,speed-bin = <0>;
|
||||
qcom,initial-pwrlevel = <5>;
|
||||
qcom,throttle-pwrlevel = <0>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <587000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x802b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <525000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x802b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <490000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <441600000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <400000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <305000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,speed-bin = <1>;
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
qcom,throttle-pwrlevel = <1>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <670000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x802b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <587000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x802b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <525000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x802b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <490000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <441600000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <400000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <305000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,speed-bin = <3>;
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <525000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x802b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <490000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <441600000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <400000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <305000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,speed-bin = <2>;
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
qcom,throttle-pwrlevel = <1>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <670000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x802b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <587000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x802b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <525000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x802b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <490000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <441600000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <400000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <305000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,speed-bin = <4>;
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
qcom,throttle-pwrlevel = <1>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <670000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x802b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <587000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x802b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <525000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x802b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <490000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <441600000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <400000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <305000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0xa02b5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
17
qcom/graphics/gpu/kona-v2.1-gpu.dts
Normal file
17
qcom/graphics/gpu/kona-v2.1-gpu.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/interconnect/qcom,kona.h>
|
||||
#include "kona-v2.1-gpu.dtsi"
|
||||
|
||||
/{
|
||||
model = "Qualcomm Technologies, Inc. kona-iot v2.1";
|
||||
compatible = "qcom,kona", "qcom,kona-iot";
|
||||
qcom,msm-id = <356 0x20001>, <481 0x20001>, <548 0x20001>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
5
qcom/graphics/gpu/kona-v2.1-gpu.dtsi
Normal file
5
qcom/graphics/gpu/kona-v2.1-gpu.dtsi
Normal file
@@ -0,0 +1,5 @@
|
||||
#include "kona-v2-gpu.dtsi"
|
||||
|
||||
&msm_gpu {
|
||||
qcom,chipid = <0x06050002>;
|
||||
};
|
||||
24
qcom/graphics/gpu/lemans-gpu-ivi-adas-star.dts
Normal file
24
qcom/graphics/gpu/lemans-gpu-ivi-adas-star.dts
Normal file
@@ -0,0 +1,24 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-lemans.h>
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-lemans.h>
|
||||
#include <dt-bindings/interconnect/qcom,epss-l3.h>
|
||||
#include <dt-bindings/interconnect/qcom,lemans.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interconnect/qcom,epss-l3.h>
|
||||
|
||||
#include "lemans-gpu.dtsi"
|
||||
#include "lemans-gpu-pwrlevel-ivi-adas-star.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Lemans SoC";
|
||||
compatible = "qcom,lemans";
|
||||
qcom,msm-id = <533 0x10000>, <534 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
56
qcom/graphics/gpu/lemans-gpu-pwrlevel-ivi-adas-star.dtsi
Normal file
56
qcom/graphics/gpu/lemans-gpu-pwrlevel-ivi-adas-star.dtsi
Normal file
@@ -0,0 +1,56 @@
|
||||
&msm_gpu {
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
qcom,initial-pwrlevel = <3>;
|
||||
qcom,initial-min-pwrlevel = <3>;
|
||||
|
||||
/* Turbo_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <800000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq = <12>;
|
||||
qcom,bus-min = <12>;
|
||||
qcom,bus-max = <12>;
|
||||
};
|
||||
|
||||
/* Turbo */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <778000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <12>;
|
||||
};
|
||||
|
||||
/* Nom */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <676000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <405000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
};
|
||||
};
|
||||
23
qcom/graphics/gpu/lemans-gpu.dts
Normal file
23
qcom/graphics/gpu/lemans-gpu.dts
Normal file
@@ -0,0 +1,23 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-lemans.h>
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-lemans.h>
|
||||
#include <dt-bindings/interconnect/qcom,epss-l3.h>
|
||||
#include <dt-bindings/interconnect/qcom,lemans.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interconnect/qcom,epss-l3.h>
|
||||
|
||||
#include "lemans-gpu.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Lemans SoC";
|
||||
compatible = "qcom,lemans";
|
||||
qcom,msm-id = <532 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
249
qcom/graphics/gpu/lemans-gpu.dtsi
Normal file
249
qcom/graphics/gpu/lemans-gpu.dtsi
Normal file
@@ -0,0 +1,249 @@
|
||||
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
&msm_gpu {
|
||||
compatible = "qcom,kgsl-3d0";
|
||||
status = "ok";
|
||||
reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
|
||||
<0x3de0000 0x10000>, <0x4900000 0x80000>,
|
||||
<0x3dff000 0x1000>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
|
||||
"qdss_gfx", "fusa";
|
||||
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
|
||||
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
||||
<&gpucc GPU_CC_HUB_AON_CLK>,
|
||||
<&gpucc GPU_CC_HUB_CX_INT_CLK>;
|
||||
clock-names = "gcc_gpu_memnoc_gfx",
|
||||
"gcc_gpu_snoc_dvm_gfx",
|
||||
"gpu_cc_ahb",
|
||||
"gpu_cc_cx_gmu",
|
||||
"gpu_cc_hlos1_vote_gpu_smmu",
|
||||
"gpu_cc_hub_aon",
|
||||
"gpu_cc_hub_cx_int";
|
||||
|
||||
qcom,chipid = <0x06060300>;
|
||||
|
||||
qcom,initial-pwrlevel = <3>;
|
||||
|
||||
qcom,highest-bank-bit = <16>;
|
||||
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
qcom,ubwc-mode = <4>;
|
||||
|
||||
qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
|
||||
|
||||
nvmem-cells = <&gpu_speed_bin>;
|
||||
nvmem-cell-names = "speed_bin";
|
||||
|
||||
qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";
|
||||
|
||||
interconnect-names = "gpu_icc_path";
|
||||
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(200, 4)>, /* index=1 */
|
||||
<MHZ_TO_KBPS(451, 4)>, /* index=2 */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(681, 4)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(1017, 4)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(1353, 4)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=8 */
|
||||
<MHZ_TO_KBPS(1708, 4)>, /* index=9 */
|
||||
<MHZ_TO_KBPS(2092, 4)>, /* index=10 */
|
||||
<MHZ_TO_KBPS(2736, 4)>, /* index=11 */
|
||||
<MHZ_TO_KBPS(3196, 4)>; /* index=12 */
|
||||
|
||||
qcom,bus-table-cnoc =
|
||||
<0>, /* Off */
|
||||
<100>; /* On */
|
||||
|
||||
qcom,l3-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,l3-pwrlevels";
|
||||
|
||||
qcom,l3-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,l3-freq = <0>;
|
||||
};
|
||||
|
||||
qcom,l3-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,l3-freq = <614400000>;
|
||||
};
|
||||
|
||||
qcom,l3-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,l3-freq = <1516800000>;
|
||||
};
|
||||
};
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&pil_gpu_mem>;
|
||||
};
|
||||
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-reserved = <2048>;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-reserved = <1024>;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 128K Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <131072>;
|
||||
qcom,mempool-reserved = <128>;
|
||||
};
|
||||
/* 256K Page Pool configuration */
|
||||
qcom,gpu-mempool@4 {
|
||||
reg = <4>;
|
||||
qcom,mempool-page-size = <262144>;
|
||||
qcom,mempool-reserved = <80>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@5 {
|
||||
reg = <5>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <840000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq = <12>;
|
||||
qcom,bus-min = <12>;
|
||||
qcom,bus-max = <12>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <778000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <12>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <676000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <405000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
reg = <0x03da0000 0x20000>;
|
||||
|
||||
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x0 0xc00>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_lpac: gfx3d_lpac {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x1 0xc00>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x2 0xc00>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gmu: qcom,gmu@3d69000 {
|
||||
compatible = "qcom,gpu-gmu";
|
||||
|
||||
reg = <0x3d6a000 0x34000>,
|
||||
<0xb290000 0x10000>,
|
||||
<0xb490000 0x10000>;
|
||||
|
||||
reg-names = "kgsl_gmu_reg",
|
||||
"kgsl_gmu_pdc_cfg",
|
||||
"kgsl_gmu_pdc_seq";
|
||||
|
||||
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";
|
||||
|
||||
regulator-names = "vddcx", "vdd", "vdd-parent";
|
||||
|
||||
iommus = <&kgsl_smmu 0x5 0xc00>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
|
||||
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
||||
vdd-supply = <&gpu_cc_gx_gdsc>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gpucc GPU_CC_HUB_CX_INT_CLK>;
|
||||
|
||||
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
|
||||
"memnoc_clk", "ahb_clk", "hub_clk";
|
||||
|
||||
mboxes = <&qmp_aop 0>;
|
||||
mbox-names = "aop";
|
||||
};
|
||||
};
|
||||
19
qcom/graphics/gpu/monaco-gpu.dts
Normal file
19
qcom/graphics/gpu/monaco-gpu.dts
Normal file
@@ -0,0 +1,19 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-monaco.h>
|
||||
#include <dt-bindings/interconnect/qcom,monaco.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-monaco.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
|
||||
#include "monaco-gpu.dtsi"
|
||||
|
||||
/{
|
||||
model = "Qualcomm Technologies, Inc. Monaco";
|
||||
compatible = "qcom,monaco";
|
||||
qcom,msm-id = <486 0x10000>, <517 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
156
qcom/graphics/gpu/monaco-gpu.dtsi
Normal file
156
qcom/graphics/gpu/monaco-gpu.dtsi
Normal file
@@ -0,0 +1,156 @@
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
&msm_gpu {
|
||||
label = "kgsl-3d0";
|
||||
compatible = "qcom,kgsl-3d0";
|
||||
status = "ok";
|
||||
|
||||
reg = <0x5900000 0x90000>,
|
||||
<0x5961000 0x800>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "cx_dbgc";
|
||||
|
||||
interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
|
||||
qcom,chipid = <0x07000201>;
|
||||
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
qcom,idle-timeout = <80>;
|
||||
qcom,gpu-bimc-interface-clk-freq = <768000000>;
|
||||
|
||||
qcom,ubwc-mode = <2>;
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
/* base addr, size */
|
||||
qcom,gpu-qdss-stm = <0xe1c0000 0x40000>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_BIMC_GPU_AXI_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
||||
<&rpmcc RPM_SMD_BIMC_GPU_CLK>;
|
||||
|
||||
clock-names = "core_clk", "rbbmtimer_clk", "mem_clk",
|
||||
"gpu_cc_ahb", "gcc_gpu_memnoc_gfx", "gmu_clk",
|
||||
"gpu_cc_hlos1_vote_gpu_smmu", "gcc_gpu_snoc_dvm_gfx",
|
||||
"bimc_gpu_clk";
|
||||
|
||||
/* GDSC regulator names */
|
||||
regulator-names = "vddcx", "vdd";
|
||||
/* GDSC oxili regulators */
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
/* Enable context aware freq. scaling */
|
||||
qcom,enable-ca-jump;
|
||||
/* Context aware jump busy penalty in us */
|
||||
qcom,ca-busy-penalty = <12000>;
|
||||
/* Context aware jump target power level */
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
|
||||
interconnect-names = "gpu_icc_path";
|
||||
interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(200, 4)>, /* index=1 */
|
||||
<MHZ_TO_KBPS(300, 4)>, /* index=2 */
|
||||
<MHZ_TO_KBPS(451, 4)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(681, 4)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(1017, 4)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(1353, 4)>, /* index=8 */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=9 */
|
||||
<MHZ_TO_KBPS(1804, 4)>, /* index=10 */
|
||||
<MHZ_TO_KBPS(2092, 4)>, /* index=11 */
|
||||
<MHZ_TO_KBPS(2133, 4)>; /* index=12 */
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&pil_gpu_mem>;
|
||||
};
|
||||
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1010000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq = <12>;
|
||||
qcom,bus-min = <12>;
|
||||
qcom,bus-max = <12>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <900000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <12>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <700000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <470000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <310000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
reg = <0x59a0000 0x10000>;
|
||||
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0 1>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 2 0>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
682
qcom/graphics/gpu/pineapple-gpu-pwrlevels.dtsi
Normal file
682
qcom/graphics/gpu/pineapple-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,682 @@
|
||||
/* ACD Control register values */
|
||||
#define ACD_LEVEL_TURBO_L1 0x882f5ffd
|
||||
#define ACD_LEVEL_TURBO 0x882f5ffd
|
||||
#define ACD_LEVEL_NOM_L1 0x882f5ffd
|
||||
#define ACD_LEVEL_NOM 0xc0285ffd
|
||||
#define ACD_LEVEL_SVS_L2 0xe0295ffd
|
||||
#define ACD_LEVEL_SVS_L1 0xe0295ffd
|
||||
#define ACD_LEVEL_SVS_L0 0xc02a5ffd
|
||||
#define ACD_LEVEL_SVS 0xc02a5ffd
|
||||
#define ACD_LEVEL_LOW_SVS_L1 0xc02c5ffd
|
||||
#define ACD_LEVEL_LOW_SVS 0xc02f5ffd
|
||||
#define ACD_LEVEL_LOW_SVS_D0 0xc02f5ffd
|
||||
|
||||
&msm_gpu {
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevels-bins";
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
|
||||
qcom,speed-bin = <2>;
|
||||
|
||||
qcom,initial-pwrlevel = <12>;
|
||||
|
||||
/* Turbo_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <903000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
|
||||
};
|
||||
|
||||
/* Turbo */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <869000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
/* Nom_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <834000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
/* Nom */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <770000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L2 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <720000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <680000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS_L0 */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <629000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <578000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_L1 */
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
|
||||
};
|
||||
|
||||
/* Low_SVS */
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <422000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D0 */
|
||||
qcom,gpu-pwrlevel@10 {
|
||||
reg = <10>;
|
||||
qcom,gpu-freq = <366000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D1 */
|
||||
qcom,gpu-pwrlevel@11 {
|
||||
reg = <11>;
|
||||
qcom,gpu-freq = <310000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D2 */
|
||||
qcom,gpu-pwrlevel@12 {
|
||||
reg = <12>;
|
||||
qcom,gpu-freq = <231000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
|
||||
|
||||
qcom,initial-pwrlevel = <11>;
|
||||
|
||||
/* Turbo */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <869000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
/* Nom_L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <834000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
/* Nom */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <770000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L2 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <720000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <680000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS_L0 */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <629000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <578000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_L1 */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
|
||||
};
|
||||
|
||||
/* Low_SVS */
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <422000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D0 */
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <366000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D1 */
|
||||
qcom,gpu-pwrlevel@10 {
|
||||
reg = <10>;
|
||||
qcom,gpu-freq = <310000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D2 */
|
||||
qcom,gpu-pwrlevel@11 {
|
||||
reg = <11>;
|
||||
qcom,gpu-freq = <231000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_0, FC_Y0)
|
||||
SKU_CODE(PCODE_1, FC_Y0)
|
||||
SKU_CODE(PCODE_0, FC_Y1)>;
|
||||
|
||||
qcom,initial-pwrlevel = <12>;
|
||||
|
||||
/* Turbo_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <903000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
|
||||
};
|
||||
|
||||
/* Turbo */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <869000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
/* Nom_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <834000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
/* Nom */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <770000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L2 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <720000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <680000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS_L0 */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <629000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <578000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_L1 */
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
|
||||
};
|
||||
|
||||
/* Low_SVS */
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <422000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D0 */
|
||||
qcom,gpu-pwrlevel@10 {
|
||||
reg = <10>;
|
||||
qcom,gpu-freq = <366000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D1 */
|
||||
qcom,gpu-pwrlevel@11 {
|
||||
reg = <11>;
|
||||
qcom,gpu-freq = <310000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D2 */
|
||||
qcom,gpu-pwrlevel@12 {
|
||||
reg = <12>;
|
||||
qcom,gpu-freq = <231000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
|
||||
|
||||
qcom,initial-pwrlevel = <10>;
|
||||
|
||||
/* Nom_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <834000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
/* Nom */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <770000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L2 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <720000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <680000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS_L0 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <629000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <578000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_L1 */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
|
||||
};
|
||||
|
||||
/* Low_SVS */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <422000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D0 */
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <366000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D1 */
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <310000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D2 */
|
||||
qcom,gpu-pwrlevel@10 {
|
||||
reg = <10>;
|
||||
qcom,gpu-freq = <231000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
22
qcom/graphics/gpu/pineapple-gpu.dts
Normal file
22
qcom/graphics/gpu/pineapple-gpu.dts
Normal file
@@ -0,0 +1,22 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-pineapple.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,pineapple.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "pineapple-gpu.dtsi"
|
||||
#include "pineapple-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple";
|
||||
compatible = "qcom,pineapple";
|
||||
qcom,msm-id = <557 0x10000>, <577 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
|
||||
254
qcom/graphics/gpu/pineapple-gpu.dtsi
Normal file
254
qcom/graphics/gpu/pineapple-gpu.dtsi
Normal file
@@ -0,0 +1,254 @@
|
||||
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
/* External feature codes */
|
||||
#define FC_UNKNOWN 0x0
|
||||
#define FC_AA 0x1
|
||||
#define FC_AB 0x2
|
||||
#define FC_AC 0x3
|
||||
#define FC_AD 0x4
|
||||
|
||||
/* Internal feature codes */
|
||||
#define FC_Y0 0x00f1
|
||||
#define FC_Y1 0x00f2
|
||||
|
||||
/* Pcodes */
|
||||
#define PCODE_UNKNOWN 0
|
||||
#define PCODE_0 1
|
||||
#define PCODE_1 2
|
||||
#define PCODE_2 3
|
||||
#define PCODE_3 4
|
||||
#define PCODE_4 5
|
||||
#define PCODE_5 6
|
||||
#define PCODE_6 7
|
||||
#define PCODE_7 8
|
||||
|
||||
#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode)
|
||||
|
||||
&msm_gpu {
|
||||
compatible = "qcom,adreno-gpu-gen7-9-0", "qcom,kgsl-3d0";
|
||||
status = "ok";
|
||||
reg = <0x3d00000 0x40000>, <0x3d61000 0x3000>,
|
||||
<0x03d50000 0x10000>, <0x03d9e000 0x2000>,
|
||||
<0x10900000 0x80000>, <0x10048000 0x8000>,
|
||||
<0x10b05000 0x1000>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", "cx_misc",
|
||||
"qdss_gfx", "qdss_etr", "qdss_tmc";
|
||||
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
|
||||
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&aoss_qmp QDSS_CLK>;
|
||||
clock-names = "gcc_gpu_memnoc_gfx",
|
||||
"gcc_gpu_snoc_dvm_gfx",
|
||||
"gpu_cc_ahb",
|
||||
"apb_pclk";
|
||||
|
||||
qcom,gpu-model = "Adreno750";
|
||||
|
||||
qcom,chipid = <0x43051400>;
|
||||
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
qcom,ubwc-mode = <4>;
|
||||
|
||||
qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
|
||||
|
||||
qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3",
|
||||
"gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7";
|
||||
|
||||
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "gpu_icc_path";
|
||||
|
||||
qcom,bus-table-cnoc =
|
||||
<0>, /* Off */
|
||||
<100>; /* On */
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(547, 4) >, /* index=1 */
|
||||
<MHZ_TO_KBPS(768, 4) >, /* index=2 */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(1708, 4)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(2092, 4)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(2736, 4)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(3187, 4)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(3686, 4)>, /* index=8 */
|
||||
<MHZ_TO_KBPS(4224, 4)>; /* index=9 */
|
||||
|
||||
nvmem-cells = <&gpu_speed_bin>;
|
||||
nvmem-cell-names = "speed_bin";
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&gpu_micro_code_mem>;
|
||||
};
|
||||
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-reserved = <2048>;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-reserved = <1024>;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 128K Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <131072>;
|
||||
qcom,mempool-reserved = <128>;
|
||||
};
|
||||
/* 256K Page Pool configuration */
|
||||
qcom,gpu-mempool@4 {
|
||||
reg = <4>;
|
||||
qcom,mempool-page-size = <262144>;
|
||||
qcom,mempool-reserved = <80>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@5 {
|
||||
reg = <5>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
reg = <0x03da0000 0x40000>;
|
||||
|
||||
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x0 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_lpac: gfx3d_lpac {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x1 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x2 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gmu: qcom,gmu@3d69000 {
|
||||
compatible = "qcom,gen7-gmu";
|
||||
|
||||
reg = <0x3d68000 0x37000>,
|
||||
<0xb280000 0x10000>,
|
||||
<0x03D40000 0x10000>;
|
||||
|
||||
reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
|
||||
|
||||
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hfi", "gmu";
|
||||
|
||||
regulator-names = "vddcx", "vdd";
|
||||
|
||||
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
||||
vdd-supply = <&gpu_cc_gx_gdsc>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gpucc GPU_CC_HUB_CX_INT_CLK>;
|
||||
|
||||
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
|
||||
"memnoc_clk", "ahb_clk", "hub_clk";
|
||||
|
||||
qcom,gmu-freq-table = <260000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
|
||||
<625000000 RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,gmu-perf-ddr-bw = <MHZ_TO_KBPS(768, 4)>;
|
||||
|
||||
iommus = <&kgsl_smmu 0x5 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
|
||||
qcom,ipc-core = <0x00400000 0x140000>;
|
||||
|
||||
mboxes = <&qmp_aop 0>;
|
||||
mbox-names = "aop";
|
||||
};
|
||||
|
||||
coresight_cx_dgbc: qcom,gpu-coresight-cx {
|
||||
compatible = "qcom,gpu-coresight-cx";
|
||||
|
||||
coresight-name = "coresight-gfx-cx";
|
||||
coresight-atid = <52>;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
cx_dbgc_out_funnel_gfx: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_gfx_in_cx_dbgc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
coresight_gx_dgbc: qcom,gpu-coresight-gx {
|
||||
compatible = "qcom,gpu-coresight-gx";
|
||||
|
||||
coresight-name = "coresight-gfx";
|
||||
coresight-atid = <53>;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
gx_dbgc_out_funnel_gfx: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_gfx_in_gx_dbgc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&funnel_gfx {
|
||||
status = "ok";
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
funnel_gfx_in_gx_dbgc: endpoint {
|
||||
remote-endpoint =
|
||||
<&gx_dbgc_out_funnel_gfx>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
funnel_gfx_in_cx_dbgc: endpoint {
|
||||
remote-endpoint =
|
||||
<&cx_dbgc_out_funnel_gfx>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
673
qcom/graphics/gpu/pineapple-v2-gpu-pwrlevels.dtsi
Normal file
673
qcom/graphics/gpu/pineapple-v2-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,673 @@
|
||||
/* ACD Control register values */
|
||||
#define ACD_LEVEL_TURBO_L1 0x882a5ffd
|
||||
#define ACD_LEVEL_TURBO 0x882a5ffd
|
||||
#define ACD_LEVEL_NOM_L1 0x882a5ffd
|
||||
#define ACD_LEVEL_NOM 0x882a5ffd
|
||||
#define ACD_LEVEL_SVS_L2 0x882a5ffd
|
||||
#define ACD_LEVEL_SVS_L1 0x882a5ffd
|
||||
#define ACD_LEVEL_SVS_L0 0x882a5ffd
|
||||
#define ACD_LEVEL_SVS 0x882c5ffd
|
||||
#define ACD_LEVEL_LOW_SVS_L1 0xc02a5ffd
|
||||
#define ACD_LEVEL_LOW_SVS 0xc02d5ffd
|
||||
#define ACD_LEVEL_LOW_SVS_D0 0xc02e5ffd
|
||||
#define ACD_LEVEL_LOW_SVS_D1 0xc82c5ffd
|
||||
#define ACD_LEVEL_LOW_SVS_D2 0xc82f5ffd
|
||||
|
||||
&msm_gpu {
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevels-bins";
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
|
||||
qcom,speed-bin = <4>;
|
||||
|
||||
qcom,initial-pwrlevel = <11>;
|
||||
|
||||
/* Turbo */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <903000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
/* Nom_L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <834000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
/* Nom */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <770000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L2 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <720000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <680000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS_L0 */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <629000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <578000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_L1 */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
|
||||
};
|
||||
|
||||
/* Low_SVS */
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <422000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D0 */
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <366000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D1 */
|
||||
qcom,gpu-pwrlevel@10 {
|
||||
reg = <10>;
|
||||
qcom,gpu-freq = <310000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D2 */
|
||||
qcom,gpu-pwrlevel@11 {
|
||||
reg = <11>;
|
||||
qcom,gpu-freq = <231000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AC)
|
||||
SKU_CODE(PCODE_0, FC_Y0)
|
||||
SKU_CODE(PCODE_1, FC_Y0)
|
||||
SKU_CODE(PCODE_0, FC_Y1)>;
|
||||
|
||||
qcom,initial-pwrlevel = <13>;
|
||||
|
||||
/* Turbo_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1000000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
|
||||
};
|
||||
|
||||
/* Turbo_L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <950000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* Turbo */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <903000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
/* Nom_L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <834000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
/* Nom */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <770000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L2 */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <720000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <680000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS_L0 */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <629000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <578000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_L1 */
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
|
||||
};
|
||||
|
||||
/* Low_SVS */
|
||||
qcom,gpu-pwrlevel@10 {
|
||||
reg = <10>;
|
||||
qcom,gpu-freq = <422000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D0 */
|
||||
qcom,gpu-pwrlevel@11 {
|
||||
reg = <11>;
|
||||
qcom,gpu-freq = <366000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D1 */
|
||||
qcom,gpu-pwrlevel@12 {
|
||||
reg = <12>;
|
||||
qcom,gpu-freq = <310000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D2 */
|
||||
qcom,gpu-pwrlevel@13 {
|
||||
reg = <13>;
|
||||
qcom,gpu-freq = <231000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AA)>;
|
||||
|
||||
qcom,initial-pwrlevel = <8>;
|
||||
|
||||
/* SVS_L2 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <720000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <680000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS_L0 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <629000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <578000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
|
||||
};
|
||||
|
||||
/* Low_SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <422000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D0 */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <366000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D1 */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <310000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D2 */
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <231000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
|
||||
|
||||
qcom,initial-pwrlevel = <11>;
|
||||
|
||||
/* Turbo */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <903000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
/* Nom_L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <834000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
/* Nom */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <770000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
/* SVS_L2 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <720000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <680000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
/* SVS_L0 */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <629000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <578000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_L1 */
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
|
||||
};
|
||||
|
||||
/* Low_SVS */
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <422000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D0 */
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <366000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D1 */
|
||||
qcom,gpu-pwrlevel@10 {
|
||||
reg = <10>;
|
||||
qcom,gpu-freq = <310000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
|
||||
};
|
||||
|
||||
/* Low_SVS_D2 */
|
||||
qcom,gpu-pwrlevel@11 {
|
||||
reg = <11>;
|
||||
qcom,gpu-freq = <231000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
21
qcom/graphics/gpu/pineapple-v2-gpu.dts
Normal file
21
qcom/graphics/gpu/pineapple-v2-gpu.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-pineapple.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,pineapple.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "pineapple-v2-gpu.dtsi"
|
||||
#include "pineapple-v2-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple";
|
||||
compatible = "qcom,pineapple", "qcom,pineappleq";
|
||||
qcom,msm-id = <557 0x20000>, <577 0x20000>, <696 0x20000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
9
qcom/graphics/gpu/pineapple-v2-gpu.dtsi
Normal file
9
qcom/graphics/gpu/pineapple-v2-gpu.dtsi
Normal file
@@ -0,0 +1,9 @@
|
||||
#include "pineapple-gpu.dtsi"
|
||||
|
||||
&msm_gpu {
|
||||
compatible = "qcom,adreno-gpu-gen7-9-1", "qcom,kgsl-3d0";
|
||||
|
||||
qcom,gpu-model = "Adreno750v2";
|
||||
|
||||
qcom,chipid = <0x43051401>;
|
||||
};
|
||||
202
qcom/graphics/gpu/pineapple-v2-sg-gpu-pwrlevels.dtsi
Normal file
202
qcom/graphics/gpu/pineapple-v2-sg-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,202 @@
|
||||
/* ACD Control register values */
|
||||
#define ACD_LEVEL_TURBO_L2 0x882a5ffd
|
||||
#define ACD_LEVEL_TURBO_L1 0x882a5ffd
|
||||
#define ACD_LEVEL_TURBO 0x882a5ffd
|
||||
#define ACD_LEVEL_NOM_L1 0x882a5ffd
|
||||
#define ACD_LEVEL_NOM 0x882a5ffd
|
||||
#define ACD_LEVEL_SVS_L2 0x882a5ffd
|
||||
#define ACD_LEVEL_SVS_L1 0x882a5ffd
|
||||
#define ACD_LEVEL_SVS_L0 0x882a5ffd
|
||||
#define ACD_LEVEL_SVS 0x882c5ffd
|
||||
#define ACD_LEVEL_LOW_SVS_L1 0xc02a5ffd
|
||||
#define ACD_LEVEL_LOW_SVS 0xc02d5ffd
|
||||
#define ACD_LEVEL_LOW_SVS_D0 0xc02e5ffd
|
||||
#define ACD_LEVEL_LOW_SVS_D1 0xc82c5ffd
|
||||
#define ACD_LEVEL_LOW_SVS_D2 0xc82f5ffd
|
||||
|
||||
&msm_gpu {
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevel-bins";
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
|
||||
|
||||
qcom,initial-pwrlevel = <13>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1050000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO_L2>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <1000000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <903000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <834000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <770000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <720000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <680000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <629000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <578000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@10 {
|
||||
reg = <10>;
|
||||
qcom,gpu-freq = <422000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@11 {
|
||||
reg = <11>;
|
||||
qcom,gpu-freq = <366000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@12 {
|
||||
reg = <12>;
|
||||
qcom,gpu-freq = <310000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@13 {
|
||||
reg = <13>;
|
||||
qcom,gpu-freq = <231000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
|
||||
qcom,bus-freq = <1>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <1>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
26
qcom/graphics/gpu/pineapple-v2-sg-gpu.dts
Normal file
26
qcom/graphics/gpu/pineapple-v2-sg-gpu.dts
Normal file
@@ -0,0 +1,26 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-pineapple.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,pineapple.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "pineapple-v2-gpu.dtsi"
|
||||
#include "pineapple-v2-sg-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple SG";
|
||||
compatible = "qcom,pineapple";
|
||||
qcom,msm-id = <682 0x20000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
|
||||
&msm_gpu {
|
||||
/delete-property/qcom,gpu-model;
|
||||
qcom,gpu-model = "Adreno33v2";
|
||||
};
|
||||
190
qcom/graphics/gpu/pitti-gpu-pwrlevels.dtsi
Normal file
190
qcom/graphics/gpu/pitti-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,190 @@
|
||||
&msm_gpu {
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-pwrlevel-bins";
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <0>;
|
||||
|
||||
qcom,ca-target-pwrlevel = <5>;
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
|
||||
/* TURBO_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1115000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <975000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
};
|
||||
|
||||
/* NOM_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <875000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <765000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <6>;
|
||||
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <605000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <4>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <340000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <2>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <2>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <235>;
|
||||
|
||||
qcom,ca-target-pwrlevel = <5>;
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
|
||||
/* TURBO_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1115000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <975000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
};
|
||||
|
||||
/* NOM_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <875000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <7>;
|
||||
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <765000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <6>;
|
||||
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <605000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <2>;
|
||||
qcom,bus-max = <4>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <340000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <2>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
20
qcom/graphics/gpu/pitti-gpu.dts
Normal file
20
qcom/graphics/gpu/pitti-gpu.dts
Normal file
@@ -0,0 +1,20 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-pitti.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-pitti.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/interconnect/qcom,pitti.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
#include "pitti-gpu.dtsi"
|
||||
#include "pitti-gpu-pwrlevels.dtsi"
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pitti";
|
||||
compatible = "qcom,pitti";
|
||||
qcom,msm-id = <623 0x10000>;
|
||||
qcom,board-id = <0 0>, <0 0x501>, <0 0x600>;
|
||||
};
|
||||
132
qcom/graphics/gpu/pitti-gpu.dtsi
Normal file
132
qcom/graphics/gpu/pitti-gpu.dtsi
Normal file
@@ -0,0 +1,132 @@
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
&msm_gpu {
|
||||
compatible = "qcom,kgsl-3d0", "qcom,adreno-gpu-a611";
|
||||
status = "ok";
|
||||
|
||||
reg = <0x5900000 0x90000>;
|
||||
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
|
||||
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_BIMC_GPU_AXI_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
||||
<&rpmcc RPM_SMD_QDSS_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
|
||||
|
||||
clock-names = "core_clk",
|
||||
"rbbmtimer_clk",
|
||||
"iface_clk",
|
||||
"ahb_clk",
|
||||
"mem_clk",
|
||||
"gmu_clk",
|
||||
"smmu_vote",
|
||||
"apb_pclk",
|
||||
"gpu_cc_ahb",
|
||||
"gcc_gpu_memnoc_gfx",
|
||||
"gpu_cc_hlos1_vote_gpu_smmu";
|
||||
|
||||
interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>, <0 181 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq", "freq_limiter_irq";
|
||||
|
||||
resets = <&gpucc GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR>;
|
||||
reset-names = "freq_limiter_irq_clear";
|
||||
|
||||
qcom,chipid = <0x06010100>;
|
||||
qcom,gpu-model = "Adreno611v1";
|
||||
|
||||
regulator-names = "vddcx", "vdd";
|
||||
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
||||
vdd-supply = <&gpu_cc_gx_gdsc>;
|
||||
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
qcom,ubwc-mode = <2>;
|
||||
|
||||
qcom,enable-ca-jump;
|
||||
|
||||
qcom,tzone-names = "gpuss";
|
||||
|
||||
/* Context aware jump busy penalty in us */
|
||||
qcom,ca-busy-penalty = <12000>;
|
||||
|
||||
nvmem-cells = <&gpu_speed_bin>;
|
||||
nvmem-cell-names = "speed_bin";
|
||||
|
||||
interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
|
||||
interconnect-names = "gpu_icc_path";
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(200, 4)>, /* index=1 (LOW SVS) */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=2 (LOW SVS) */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=3 (SVS) */
|
||||
<MHZ_TO_KBPS(1017, 4)>, /* index=4 (SVS) */
|
||||
<MHZ_TO_KBPS(1353, 4)>, /* index=5 (NOM) */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=6 (NOM) */
|
||||
<MHZ_TO_KBPS(1804, 4)>, /* index=7 (TURBO) */
|
||||
<MHZ_TO_KBPS(2092, 4)>; /* index=8 (TURBO_L1) */
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&gpu_microcode_mem>;
|
||||
};
|
||||
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
|
||||
reg = <0x59a0000 0x10000>;
|
||||
|
||||
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x0 0x001>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x2 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
16
qcom/graphics/gpu/qcs405-gpu.dts
Normal file
16
qcom/graphics/gpu/qcs405-gpu.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/interconnect/qcom,qcs405.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "qcs405-gpu.dtsi"
|
||||
|
||||
/{
|
||||
model = "Qualcomm Technologies, Inc. QCS405";
|
||||
compatible = "qcom,qcs405";
|
||||
qcom,msm-id = <352 0x0>,<411 0x0>,<452 0x0>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
126
qcom/graphics/gpu/qcs405-gpu.dtsi
Normal file
126
qcom/graphics/gpu/qcs405-gpu.dtsi
Normal file
@@ -0,0 +1,126 @@
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
&msm_gpu {
|
||||
compatible = "qcom,kgsl-3d0" , "qcom,kgsl-3d";
|
||||
reg = <0x1c00000 0x10000>,
|
||||
<0x1c10000 0x10000>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "kgsl_3d0_shader_memory";
|
||||
|
||||
interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
|
||||
qcom,chipid = <0x03000620>;
|
||||
|
||||
qcom,initial-pwrlevel = <3>;
|
||||
|
||||
qcom,gpu-bimc-interface-clk-freq = <400000000>; //In Hz
|
||||
|
||||
clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
|
||||
<&gcc GCC_OXILI_AHB_CLK>,
|
||||
<&gcc GCC_BIMC_GFX_CLK>,
|
||||
<&gcc GCC_BIMC_GPU_CLK>,
|
||||
<&gcc GCC_GTCU_AHB_CLK>,
|
||||
<&gcc GCC_GFX_TCU_CLK>,
|
||||
<&gcc GCC_GFX_TBU_CLK>,
|
||||
<&rpmcc RPM_SMD_BIMC_GPU_CLK>,
|
||||
<&gcc GCC_SMMU_CFG_CLK>,
|
||||
<&gcc GCC_GFX_TCU_CLK>;
|
||||
|
||||
clock-names = "core_clk", "iface_clk", "mem_iface_clk",
|
||||
"alt_mem_iface_clk", "gtcu_iface_clk",
|
||||
"gtcu_clk", "gtbu_clk", "bimc_gpu_clk",
|
||||
"gcc_smmu_cfg_clk", "gcc_gfx_tcu_clk";
|
||||
|
||||
interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
|
||||
interconnect-names = "gpu_icc_path";
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(101, 4)>, /* index=1 */
|
||||
<MHZ_TO_KBPS(211, 4)>, /* index=2 */
|
||||
<MHZ_TO_KBPS(298, 4)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(384, 4)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(557, 4)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(595, 4)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(672, 4)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(739, 4)>; /* index=8 */
|
||||
|
||||
/* GDSC regulator names */
|
||||
regulator-names = "vdd";
|
||||
/* GDSC oxili regulators */
|
||||
vdd-supply = <&gdsc_oxili_gx>;
|
||||
|
||||
/* Enable gpu cooling device */
|
||||
#cooling-cells = <2>;
|
||||
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <598000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* NOM+ */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <523200000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <7>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <484800000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <4>;
|
||||
qcom,bus-max = <6>;
|
||||
};
|
||||
|
||||
/* SVS+ */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <400000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <270000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@1f00000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
reg = <0x1f00000 0x10000>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&gfx_iommu 0 1>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
339
qcom/graphics/gpu/sa6155p-gpu-pwrlevels.dtsi
Normal file
339
qcom/graphics/gpu/sa6155p-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,339 @@
|
||||
/* GPU Powerlevel overrides for SA6155p */
|
||||
&msm_gpu {
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible="qcom,gpu-pwrlevel-bins";
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <845000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <3>;
|
||||
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <845000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <4>;
|
||||
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <845000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <5>;
|
||||
|
||||
qcom,initial-pwrlevel = <2>;
|
||||
qcom,ca-target-pwrlevel = <1>;
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <650000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <6>;
|
||||
|
||||
qcom,initial-pwrlevel = <1>;
|
||||
qcom,ca-target-pwrlevel = <0>;
|
||||
|
||||
/* SVS L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <7>;
|
||||
|
||||
qcom,initial-pwrlevel = <0>;
|
||||
qcom,ca-target-pwrlevel = <0>;
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <435000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* XO */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
23
qcom/graphics/gpu/sa6155p-gpu.dts
Normal file
23
qcom/graphics/gpu/sa6155p-gpu.dts
Normal file
@@ -0,0 +1,23 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-sm6150.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm6150.h>
|
||||
#include <dt-bindings/interconnect/qcom,icc.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm6150.h>
|
||||
#include <dt-bindings/soc/qcom,dcc_v2.h>
|
||||
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
|
||||
#include "sa6155p-gpu.dtsi"
|
||||
#include "sa6155p-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SA6155P SoC";
|
||||
compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star", "qcom,adp-air";
|
||||
qcom,msm-id = <377 0>, <380 0>;
|
||||
qcom,board-id = <0x010019 0>, <0x03010019 0>;
|
||||
};
|
||||
1
qcom/graphics/gpu/sa6155p-gpu.dtsi
Normal file
1
qcom/graphics/gpu/sa6155p-gpu.dtsi
Normal file
@@ -0,0 +1 @@
|
||||
#include "sm6150-gpu.dtsi"
|
||||
20
qcom/graphics/gpu/sa8155-v2-gpu.dts
Normal file
20
qcom/graphics/gpu/sa8155-v2-gpu.dts
Normal file
@@ -0,0 +1,20 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8150.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "sa8155-v2-gpu.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SA8155 SoC";
|
||||
qcom,msm-name = "SA8155 V2";
|
||||
qcom,msm-id = <362 0x20000>, <367 0x20000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
180
qcom/graphics/gpu/sa8155-v2-gpu.dtsi
Normal file
180
qcom/graphics/gpu/sa8155-v2-gpu.dtsi
Normal file
@@ -0,0 +1,180 @@
|
||||
#include "sm8150-gpu.dtsi"
|
||||
|
||||
/* GPU power level overrides */
|
||||
&msm_gpu {
|
||||
/* Updated chip ID */
|
||||
qcom,chipid = <0x06040001>;
|
||||
|
||||
/* Power level to start throttling */
|
||||
qcom,throttle-pwrlevel = <0>;
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(200, 4)>, /* index=1 */
|
||||
<MHZ_TO_KBPS(300, 4)>, /* index=2 */
|
||||
<MHZ_TO_KBPS(451, 4)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(681, 4)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(1017, 4)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(1353, 4)>, /* index=8 */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=9 */
|
||||
<MHZ_TO_KBPS(1804, 4)>, /* index=10 */
|
||||
<MHZ_TO_KBPS(2092, 4)>; /* index=11 */
|
||||
|
||||
/delete-property/qcom,initial-pwrlevel;
|
||||
/delete-node/qcom,gpu-pwrlevels;
|
||||
/delete-node/qcom,gpu-pwrlevel-bins;
|
||||
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible="qcom,gpu-pwrlevel-bins";
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <0>;
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <700000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <675000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <585000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <427000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* Vote for SVS_L1 voltage for 345MHz instead of SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <345000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* Vote for SVS_L1 voltage for 257MHz instead of LOW_SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <257000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <2>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <1>;
|
||||
qcom,initial-pwrlevel = <2>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <427000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* Vote for SVS_L1 voltage for 345MHz instead of SVS */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <345000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* Vote for SVS_L1 voltage for 257MHz instead of LOW_SVS */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <257000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <2>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gmu {
|
||||
reg = <0x2c6a000 0x30000>,
|
||||
<0xb290000 0x10000>,
|
||||
<0xb490000 0x10000>;
|
||||
reg-names = "kgsl_gmu_reg",
|
||||
"kgsl_gmu_pdc_cfg",
|
||||
"kgsl_gmu_pdc_seq";
|
||||
};
|
||||
17
qcom/graphics/gpu/sa8195p-gpu.dts
Normal file
17
qcom/graphics/gpu/sa8195p-gpu.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
|
||||
#include <dt-bindings/interconnect/qcom,sc8180x.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
|
||||
#include "sa8195p-gpu.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SA8195P SoC";
|
||||
qcom,msm-name = "SA8195P";
|
||||
qcom,msm-id = <405 0x20000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
255
qcom/graphics/gpu/sa8195p-gpu.dtsi
Normal file
255
qcom/graphics/gpu/sa8195p-gpu.dtsi
Normal file
@@ -0,0 +1,255 @@
|
||||
#include "sdmshrike-gpu.dtsi"
|
||||
|
||||
&msm_gpu {
|
||||
/* Updated chip ID */
|
||||
qcom,chipid = <0x6080001>;
|
||||
|
||||
/* Power level to start throttling */
|
||||
qcom,throttle-pwrlevel = <3>;
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(200, 4)>, /* index=1 */
|
||||
<MHZ_TO_KBPS(300, 4)>, /* index=2 */
|
||||
<MHZ_TO_KBPS(451, 4)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(681, 4)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(1017, 4)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(1353, 4)>, /* index=8 */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=9 */
|
||||
<MHZ_TO_KBPS(1804, 4)>, /* index=10 */
|
||||
<MHZ_TO_KBPS(2092, 4)>; /* index=11 */
|
||||
|
||||
qcom,bus-table-cnoc =
|
||||
<0>, /* Off */
|
||||
<100>; /* On */
|
||||
|
||||
nvmem-cells = <&gpu_speed_bin>;
|
||||
nvmem-cell-names = "speed_bin";
|
||||
|
||||
/delete-property/qcom,initial-pwrlevel;
|
||||
/delete-node/qcom,gpu-pwrlevels;
|
||||
/delete-node/qcom,gpu-pwrlevel-bins;
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible="qcom,gpu-pwrlevel-bins";
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <0>;
|
||||
qcom,initial-pwrlevel = <1>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <530000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <392000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <1>;
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <670000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <625000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <595000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <530000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <392000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <2>;
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <670000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <625000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <595000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <530000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <392000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,speed-bin = <3>;
|
||||
qcom,initial-pwrlevel = <4>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <670000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <625000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <595000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <530000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <392000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qcom,l3-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,l3-pwrlevels";
|
||||
|
||||
qcom,l3-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,l3-freq = <0>;
|
||||
};
|
||||
|
||||
qcom,l3-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,l3-freq = <1344000000>;
|
||||
};
|
||||
|
||||
qcom,l3-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,l3-freq = <1612800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gmu {
|
||||
reg = <0x2c6a000 0x30000>,
|
||||
<0xb290000 0x10000>,
|
||||
<0xb490000 0x10000>;
|
||||
reg-names = "kgsl_gmu_reg",
|
||||
"kgsl_gmu_pdc_cfg",
|
||||
"kgsl_gmu_pdc_seq";
|
||||
};
|
||||
232
qcom/graphics/gpu/sdmshrike-gpu.dtsi
Normal file
232
qcom/graphics/gpu/sdmshrike-gpu.dtsi
Normal file
@@ -0,0 +1,232 @@
|
||||
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
&msm_gpu {
|
||||
label = "kgsl-3d0";
|
||||
compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
|
||||
status = "ok";
|
||||
reg = <0x2c00000 0x40000>, <0x780000 0x6fff>,
|
||||
<0x2c61000 0x800>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "qfprom_memory",
|
||||
"cx_dbgc";
|
||||
|
||||
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
qcom,id = <0>;
|
||||
|
||||
qcom,chipid = <0x6080000>;
|
||||
|
||||
qcom,initial-pwrlevel = <5>;
|
||||
|
||||
qcom,gpu-quirk-secvid-set-once;
|
||||
qcom,gpu-quirk-cx-gdsc;
|
||||
|
||||
qcom,idle-timeout = <80>; /* msecs */
|
||||
|
||||
qcom,highest-bank-bit = <16>;
|
||||
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
qcom,ubwc-mode = <3>;
|
||||
|
||||
qcom,macrotiling-channels = <8>;
|
||||
|
||||
qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
|
||||
|
||||
#cooling-cells = <2>;
|
||||
|
||||
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>;
|
||||
|
||||
clock-names = "gcc_gpu_ahb", "rbbmtimer_clk",
|
||||
"gcc_gpu_axi_clk", "gcc_gpu_memnoc_gfx",
|
||||
"gmu_clk", "gpu_cc_ahb";
|
||||
|
||||
qcom,isense-clk-on-level = <1>;
|
||||
|
||||
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "gpu_icc_path";
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(100, 4)>, /* index=1 */
|
||||
<MHZ_TO_KBPS(150, 4)>, /* index=2 */
|
||||
<MHZ_TO_KBPS(200, 4)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(300, 4)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(412, 4)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(681, 4)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=8 */
|
||||
<MHZ_TO_KBPS(1017, 4)>, /* index=9 */
|
||||
<MHZ_TO_KBPS(1296, 4)>, /* index=10 */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=11 */
|
||||
<MHZ_TO_KBPS(1804, 4)>; /* index=12 */
|
||||
|
||||
qcom,bus-table-cnoc =
|
||||
<0>, /* Off */
|
||||
<100>; /* On */
|
||||
|
||||
|
||||
/* GDSC regulator names */
|
||||
regulator-names = "vddcx", "vdd";
|
||||
/* GDSC oxili regulators */
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&gpu_micro_code_mem>;
|
||||
};
|
||||
|
||||
|
||||
/* GPU Mempools */
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-reserved = <2048>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-reserved = <1024>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <514000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <12>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <12>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <500000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
qcom,bus-freq = <12>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <12>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <461000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <405000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <315000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@2ca0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
|
||||
reg = <0x2ca0000 0x10000>;
|
||||
|
||||
qcom,secure-size = <0x20000000>; /* 512MB */
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
label = "gfx3d_user";
|
||||
iommus = <&kgsl_smmu 0x0 0xC01>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
label = "gfx3d_secure";
|
||||
iommus = <&kgsl_smmu 0x2 0xC00>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gmu: qcom,gmu@2c6a000 {
|
||||
compatible = "qcom,gpu-gmu";
|
||||
|
||||
reg = <0x2c6a000 0x30000>, <0xb200000 0x300000>;
|
||||
reg-names = "kgsl_gmu_reg", "kgsl_gmu_pdc_reg";
|
||||
|
||||
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";
|
||||
|
||||
regulator-names = "vddcx", "vdd";
|
||||
|
||||
iommus = <&kgsl_smmu 0x5 0xc00>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>;
|
||||
|
||||
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
|
||||
"gcc_gpu_memnoc_gfx_clk", "gpu_cc_ahb";
|
||||
};
|
||||
};
|
||||
166
qcom/graphics/gpu/sm6150-gpu.dtsi
Normal file
166
qcom/graphics/gpu/sm6150-gpu.dtsi
Normal file
@@ -0,0 +1,166 @@
|
||||
|
||||
#define KHZ_TO_KBPS(khz, w) ((khz * 1000 * w) / (1024))
|
||||
|
||||
&msm_gpu {
|
||||
label = "kgsl-3d0";
|
||||
compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
|
||||
status = "ok";
|
||||
reg = <0x5000000 0x90000>;
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
qcom,id = <0>;
|
||||
|
||||
qcom,chipid = <0x06010200>;
|
||||
|
||||
/* <HZ/12> */
|
||||
qcom,idle-timeout = <80>;
|
||||
|
||||
qcom,highest-bank-bit = <14>;
|
||||
qcom,ubwc-mode = <2>;
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
/* base addr, size */
|
||||
qcom,gpu-qdss-stm = <0x161c0000 0x40000>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
||||
<&gpucc GPU_CC_CX_GMU_CLK>;
|
||||
|
||||
clock-names = "core_clk", "rbbmtimer_clk", "gcc_gpu_axi_clk",
|
||||
"iface_clk", "gcc_gpu_memnoc_gfx",
|
||||
"gpu_cc_hlos1_vote_gpu_smmu", "gmu_clk";
|
||||
|
||||
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "gpu_icc_path";
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<KHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<KHZ_TO_KBPS(100000, 4)>, /* index=1 (Low SVS) */
|
||||
<KHZ_TO_KBPS(200000, 4)>, /* index=2 (Low SVS) */
|
||||
<KHZ_TO_KBPS(300000, 4)>, /* index=3 (Low SVS) */
|
||||
<KHZ_TO_KBPS(451200, 4)>, /* index=4 (Low SVS) */
|
||||
<KHZ_TO_KBPS(547200, 4)>, /* index=5 (Low SVS) */
|
||||
<KHZ_TO_KBPS(681600, 4)>, /* index=6 (SVS) */
|
||||
<KHZ_TO_KBPS(768000, 4)>, /* index=7 (SVS) */
|
||||
<KHZ_TO_KBPS(1017600, 4)>, /* index=8 (SVS L1) */
|
||||
<KHZ_TO_KBPS(1353600, 4)>, /* index=9 (NOM) */
|
||||
<KHZ_TO_KBPS(1555200, 4)>, /* index=10 (NOM) */
|
||||
<KHZ_TO_KBPS(1804800, 4)>; /* index=11 (TURBO) */
|
||||
|
||||
qcom,bus-table-cnoc =
|
||||
<0>, /* Off */
|
||||
<100>; /* On */
|
||||
|
||||
/* GDSC regulator names */
|
||||
regulator-names = "vddcx", "vdd";
|
||||
/* GDSC oxili regulators */
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
|
||||
/* CPU latency parameter */
|
||||
qcom,pm-qos-active-latency = <67>;
|
||||
qcom,pm-qos-wakeup-latency = <67>;
|
||||
|
||||
/* Enable context aware freq. scaling */
|
||||
qcom,enable-ca-jump;
|
||||
/* Context aware jump busy penalty in us */
|
||||
qcom,ca-busy-penalty = <12000>;
|
||||
/* Context aware jump target power level */
|
||||
qcom,ca-target-pwrlevel = <3>;
|
||||
|
||||
nvmem-cells = <&gpu_speed_bin>;
|
||||
nvmem-cell-names = "speed_bin";
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&pil_gpu_mem>;
|
||||
};
|
||||
|
||||
/* GPU Mempools */
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@50a0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
|
||||
reg = <0x50a0000 0x10000>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
label = "gfx3d_user";
|
||||
iommus = <&kgsl_smmu 0x0 0x401>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
label = "gfx3d_secure";
|
||||
iommus = <&kgsl_smmu 0x2 0x400>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
rgmu: qcom,rgmu@0x0506d000 {
|
||||
compatible = "qcom,gpu-rgmu";
|
||||
label = "kgsl-rgmu";
|
||||
|
||||
reg = <0x506d000 0x31000>;
|
||||
reg-names = "kgsl_rgmu";
|
||||
|
||||
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_oob", "kgsl_rgmu";
|
||||
|
||||
regulator-names = "vddcx", "vdd";
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
||||
<&gpucc GPU_CC_GX_GFX3D_CLK>;
|
||||
|
||||
clock-names = "gmu", "rbbmtimer", "mem",
|
||||
"iface", "mem_iface",
|
||||
"smmu_vote", "core";
|
||||
};
|
||||
};
|
||||
277
qcom/graphics/gpu/sm8150-gpu.dtsi
Normal file
277
qcom/graphics/gpu/sm8150-gpu.dtsi
Normal file
@@ -0,0 +1,277 @@
|
||||
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
&msm_gpu {
|
||||
label = "kgsl-3d0";
|
||||
compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
|
||||
status = "ok";
|
||||
reg = <0x2c00000 0x40000>, <0x2c61000 0x800>,
|
||||
<0x6900000 0x44000>, <0x780000 0x6fff>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "cx_dbgc",
|
||||
"qdss_gfx", "qfprom_memory";
|
||||
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
qcom,id = <0>;
|
||||
|
||||
qcom,chipid = <0x06040000>;
|
||||
|
||||
qcom,initial-pwrlevel = <5>;
|
||||
|
||||
qcom,gpu-quirk-secvid-set-once;
|
||||
qcom,gpu-quirk-cx-gdsc;
|
||||
|
||||
qcom,idle-timeout = <80>; //msecs
|
||||
qcom,no-nap;
|
||||
|
||||
qcom,highest-bank-bit = <15>;
|
||||
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
qcom,ubwc-mode = <3>;
|
||||
|
||||
qcom,gpu-qdss-stm = <0x161c0000 0x40000>; // base addr, size
|
||||
|
||||
#cooling-cells = <2>;
|
||||
|
||||
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>;
|
||||
|
||||
clock-names = "gcc_gpu_ahb", "rbbmtimer_clk",
|
||||
"gcc_gpu_axi_clk", "gcc_gpu_memnoc_gfx",
|
||||
"gmu_clk", "gpu_cc_ahb";
|
||||
|
||||
qcom,isense-clk-on-level = <1>;
|
||||
|
||||
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "gpu_icc_path";
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(100, 4)>, /* index=1 */
|
||||
<MHZ_TO_KBPS(150, 4)>, /* index=2 */
|
||||
<MHZ_TO_KBPS(200, 4)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(300, 4)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(412, 4)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(681, 4)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=8 */
|
||||
<MHZ_TO_KBPS(1017, 4)>, /* index=9 */
|
||||
<MHZ_TO_KBPS(1296, 4)>, /* index=10 */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=11 */
|
||||
<MHZ_TO_KBPS(1804, 4)>; /* index=12 */
|
||||
|
||||
qcom,bus-table-cnoc =
|
||||
<0>, /* Off */
|
||||
<100>; /* On */
|
||||
|
||||
|
||||
/* GDSC regulator names */
|
||||
regulator-names = "vddcx", "vdd";
|
||||
/* GDSC oxili regulators */
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
nvmem-cells = <&gpu_speed_bin>;
|
||||
nvmem-cell-names = "speed_bin";
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&gpu_micro_code_mem>;
|
||||
};
|
||||
|
||||
qcom,l3-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,l3-pwrlevels";
|
||||
|
||||
qcom,l3-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,l3-freq = <0>;
|
||||
};
|
||||
|
||||
qcom,l3-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,l3-freq = <864000000>;
|
||||
};
|
||||
|
||||
qcom,l3-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,l3-freq = <1344000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* GPU Mempools */
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-reserved = <2048>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-reserved = <1024>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <600000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <12>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <12>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <553850000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <486460000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <379650000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <309110000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <5>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <7>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <215000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <0>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
|
||||
qcom,bus-freq = <0>;
|
||||
qcom,bus-min = <0>;
|
||||
qcom,bus-max = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@2ca0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
|
||||
reg = <0x2ca0000 0x10000>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
label = "gfx3d_user";
|
||||
iommus = <&kgsl_smmu 0x0 0x401>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
label = "gfx3d_secure";
|
||||
iommus = <&kgsl_smmu 0x2 0x400>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gmu: qcom,gmu@2c6a000 {
|
||||
compatible = "qcom,gpu-gmu";
|
||||
|
||||
reg = <0x2c6a000 0x30000>,
|
||||
<0xb280000 0x10000>,
|
||||
<0xb480000 0x10000>;
|
||||
reg-names = "kgsl_gmu_reg",
|
||||
"kgsl_gmu_pdc_cfg",
|
||||
"kgsl_gmu_pdc_seq";
|
||||
|
||||
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";
|
||||
|
||||
regulator-names = "vddcx", "vdd";
|
||||
|
||||
iommus = <&kgsl_smmu 0x5 0x400>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
|
||||
vddcx-supply = <&gpu_cx_gdsc>;
|
||||
vdd-supply = <&gpu_gx_gdsc>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>;
|
||||
|
||||
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
|
||||
"gcc_gpu_memnoc_gfx_clk", "gpu_cc_ahb";
|
||||
|
||||
/* AOP mailbox for sending ACD enable and disable messages */
|
||||
mboxes = <&qmp_aop 0>;
|
||||
mbox-names = "aop";
|
||||
|
||||
};
|
||||
};
|
||||
18
qcom/graphics/gpu/trinket-gpu.dts
Normal file
18
qcom/graphics/gpu/trinket-gpu.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-trinket.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-trinket.h>
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/interconnect/qcom,trinket.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
#include "trinket-gpu.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. TRINKET IOT";
|
||||
compatible = "qcom,trinket-iot";
|
||||
qcom,msm-id = <467 0x0>, <394 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
211
qcom/graphics/gpu/trinket-gpu.dtsi
Normal file
211
qcom/graphics/gpu/trinket-gpu.dtsi
Normal file
@@ -0,0 +1,211 @@
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
&msm_gpu {
|
||||
compatible = "qcom,kgsl-3d0";
|
||||
status = "ok";
|
||||
|
||||
reg = <0x5900000 0x90000>,
|
||||
<0x5961000 0x800>;
|
||||
reg-names = "kgsl_3d0_reg_memory",
|
||||
"cx_dbgc";
|
||||
|
||||
interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
|
||||
qcom,chipid = <0x06010000>;
|
||||
|
||||
qcom,initial-pwrlevel = <6>;
|
||||
|
||||
qcom,ubwc-mode = <1>;
|
||||
qcom,min-access-length = <64>;
|
||||
|
||||
/* base addr, size */
|
||||
qcom,gpu-qdss-stm = <0xe1c0000 0x40000>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_BIMC_GPU_AXI_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
|
||||
|
||||
clock-names = "core_clk", "rbbmtimer_clk", "mem_clk",
|
||||
"iface_clk", "mem_iface_clk",
|
||||
"gmu_clk", "smmu_vote",
|
||||
"gcc_gpu_memnoc_gfx",
|
||||
"gcc_gpu_snoc_dvm_gfx",
|
||||
"gpu_cc_ahb",
|
||||
"gpu_cc_hlos1_vote_gpu_smmu";
|
||||
|
||||
interconnect-names = "gpu_icc_path";
|
||||
interconnects = <&system_noc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(100, 4)>, /* index=1 */
|
||||
<MHZ_TO_KBPS(200, 4)>, /* index=2 */
|
||||
<MHZ_TO_KBPS(300, 4)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(451, 4)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(681, 4)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(1017, 4)>, /* index=8 */
|
||||
<MHZ_TO_KBPS(1353, 4)>, /* index=9 */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=10 */
|
||||
<MHZ_TO_KBPS(1804, 4)>; /* index=11 */
|
||||
|
||||
/* GDSC regulator names */
|
||||
regulator-names = "vddcx", "vdd";
|
||||
/* GDSC oxili regulators */
|
||||
vddcx-supply = <&cx_gdsc>;
|
||||
vdd-supply = <&gx_gdsc>;
|
||||
|
||||
/* Enable context aware frequency scaling */
|
||||
qcom,enable-ca-jump;
|
||||
/* Context aware jump busy penalty in us */
|
||||
qcom,ca-busy-penalty = <12000>;
|
||||
/* Context aware jump target power level */
|
||||
qcom,ca-target-pwrlevel = <5>;
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&pil_gpu_mem>;
|
||||
};
|
||||
|
||||
/* GPU Mempools */
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-allocate;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
/* TURBO_L1 */
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <950000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* TURBO */
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <900000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM_L1 */
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <820000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
};
|
||||
|
||||
/* NOM */
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <745000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,bus-freq = <9>;
|
||||
qcom,bus-min = <8>;
|
||||
qcom,bus-max = <10>;
|
||||
};
|
||||
|
||||
/* SVS_L1 */
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <600000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <7>;
|
||||
qcom,bus-max = <9>;
|
||||
};
|
||||
|
||||
/* SVS */
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <465000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
qcom,bus-freq = <7>;
|
||||
qcom,bus-min = <5>;
|
||||
qcom,bus-max = <8>;
|
||||
};
|
||||
|
||||
/* LOW SVS */
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <320000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,bus-freq = <4>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <5>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
reg = <0x59a0000 0x10000>;
|
||||
|
||||
vddcx-supply = <&cx_gdsc>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0 1>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 2 0>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
18
qcom/graphics/gpu/trinketp-gpu.dts
Normal file
18
qcom/graphics/gpu/trinketp-gpu.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-trinket.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-trinket.h>
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/interconnect/qcom,trinket.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
#include "trinket-gpu.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. TRINKETP";
|
||||
compatible = "qcom,trinketp-iot";
|
||||
qcom,msm-id = <468 0x0>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
345
qcom/graphics/gpu/volcano-gpu-pwrlevels.dtsi
Normal file
345
qcom/graphics/gpu/volcano-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,345 @@
|
||||
&msm_gpu {
|
||||
/* Power level bins */
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
compatible = "qcom,gpu-pwrlevels-bins";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <8>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AC)
|
||||
SKU_CODE(PCODE_UNKNOWN, FC_AD)
|
||||
SKU_CODE(PCODE_1, FC_W0)
|
||||
SKU_CODE(PCODE_1, FC_W1)
|
||||
SKU_CODE(PCODE_2, FC_W0)
|
||||
SKU_CODE(PCODE_2, FC_W1)
|
||||
SKU_CODE(PCODE_3, FC_W0)
|
||||
SKU_CODE(PCODE_3, FC_W1)
|
||||
SKU_CODE(PCODE_0, FC_Y1)
|
||||
SKU_CODE(PCODE_0, FC_Y0)>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1150000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <9>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <9>;
|
||||
qcom,bus-min-ddr8 = <8>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Turbo_L2>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <1050000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <9>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <9>;
|
||||
qcom,bus-min-ddr8 = <8>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Turbo_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <960000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <8>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Turbo>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <895000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <7>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <6>;
|
||||
qcom,bus-max-ddr8 = <8>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Nominal_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <763000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <7>;
|
||||
qcom,bus-min-ddr7 = <6>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Nominal>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <688000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <644000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <6>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <5>;
|
||||
qcom,bus-min-ddr8 = <4>;
|
||||
qcom,bus-max-ddr8 = <6>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <510000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <5>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <4>;
|
||||
qcom,bus-min-ddr8 = <3>;
|
||||
qcom,bus-max-ddr8 = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <362000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <264000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS_D1>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <7>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AB)
|
||||
SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1050000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <9>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <9>;
|
||||
qcom,bus-min-ddr8 = <8>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Turbo_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <960000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <8>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Turbo>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <895000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <7>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <6>;
|
||||
qcom,bus-max-ddr8 = <8>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Nominal_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <763000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <7>;
|
||||
qcom,bus-min-ddr7 = <6>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Nominal>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <688000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <644000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <6>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <5>;
|
||||
qcom,bus-min-ddr8 = <4>;
|
||||
qcom,bus-max-ddr8 = <6>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <510000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <5>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <4>;
|
||||
qcom,bus-min-ddr8 = <3>;
|
||||
qcom,bus-max-ddr8 = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <362000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <264000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS_D1>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
21
qcom/graphics/gpu/volcano-gpu.dts
Normal file
21
qcom/graphics/gpu/volcano-gpu.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,volcano.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "volcano-gpu.dtsi"
|
||||
#include "volcano-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano SoC";
|
||||
compatible = "qcom,volcano";
|
||||
qcom,msm-id = <636 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
228
qcom/graphics/gpu/volcano-gpu.dtsi
Normal file
228
qcom/graphics/gpu/volcano-gpu.dtsi
Normal file
@@ -0,0 +1,228 @@
|
||||
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
#define UINT32_MAX 4294967295
|
||||
|
||||
/* External feature codes */
|
||||
#define FC_UNKNOWN 0x0
|
||||
#define FC_AA 0x1
|
||||
#define FC_AB 0x2
|
||||
#define FC_AC 0x3
|
||||
#define FC_AD 0x4
|
||||
#define FC_AE 0x5
|
||||
#define FC_AF 0x6
|
||||
#define FC_AG 0x7
|
||||
#define FC_AH 0x8
|
||||
|
||||
/* SubPart feature code */
|
||||
#define FC_W0 0x00d1
|
||||
#define FC_W1 0x00d2
|
||||
|
||||
/* Internal feature codes */
|
||||
#define FC_Y0 0x00f1
|
||||
#define FC_Y1 0x00f2
|
||||
#define FC_Y2 0x00f3
|
||||
#define FC_Y3 0x00f4
|
||||
#define FC_Y4 0x00f5
|
||||
#define FC_Y5 0x00f6
|
||||
#define FC_Y6 0x00f7
|
||||
#define FC_Y7 0x00f8
|
||||
#define FC_Y8 0x00f9
|
||||
#define FC_Y9 0x00fa
|
||||
#define FC_YA 0x00fb
|
||||
#define FC_YB 0x00fc
|
||||
#define FC_YC 0x00fd
|
||||
#define FC_YD 0x00fe
|
||||
#define FC_YE 0x00ff
|
||||
#define FC_YF 0x0100
|
||||
|
||||
/* Pcodes */
|
||||
#define PCODE_UNKNOWN 0
|
||||
#define PCODE_0 1
|
||||
#define PCODE_1 2
|
||||
#define PCODE_2 3
|
||||
#define PCODE_3 4
|
||||
#define PCODE_4 5
|
||||
#define PCODE_5 6
|
||||
#define PCODE_6 7
|
||||
#define PCODE_7 8
|
||||
#define PCODE_8 9
|
||||
|
||||
#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode)
|
||||
|
||||
/* ACD Control register values */
|
||||
#define ACD_LEVEL_Turbo_L2 0xa02f5ffd
|
||||
#define ACD_LEVEL_Turbo_L1 0x88285ffd
|
||||
#define ACD_LEVEL_Turbo 0xa8285ffd
|
||||
#define ACD_LEVEL_Nominal_L1 0x88295ffd
|
||||
#define ACD_LEVEL_Nominal 0xa8295ffd
|
||||
#define ACD_LEVEL_SVS_L2 0x882a5ffd
|
||||
#define ACD_LEVEL_SVS_L1 0x882a5ffd
|
||||
#define ACD_LEVEL_SVS 0x882b5ffd
|
||||
#define ACD_LEVEL_LowSVS 0xc02c5ffd
|
||||
#define ACD_LEVEL_LowSVS_D1 0xc8295ffd
|
||||
|
||||
&msm_gpu {
|
||||
compatible = "qcom,adreno-gpu-gen8-3-0", "qcom,kgsl-3d0";
|
||||
status = "ok";
|
||||
reg = <0x3d00000 0x40000>, <0x3d61000 0x3000>,
|
||||
<0x3d50000 0x10000>, <0x3d9e000 0x2000>,
|
||||
<0x10900000 0x80000>, <0x10048000 0x8000>,
|
||||
<0x10b05000 0x1000>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", "cx_misc",
|
||||
"qdss_gfx", "qdss_etr", "qdss_tmc";
|
||||
|
||||
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq", "cx_host_irq";
|
||||
|
||||
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&aoss_qmp QDSS_CLK>;
|
||||
clock-names = "gcc_gpu_memnoc_gfx",
|
||||
"gcc_gpu_snoc_dvm_gfx",
|
||||
"gpu_cc_ahb",
|
||||
"apb_pclk";
|
||||
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
qcom,ubwc-mode = <4>;
|
||||
|
||||
qcom,tzone-names = "gpuss-0", "gpuss-1";
|
||||
|
||||
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "gpu_icc_path";
|
||||
|
||||
qcom,bus-table-cnoc =
|
||||
<0>, /* Off */
|
||||
<100>; /* On */
|
||||
|
||||
qcom,bus-table-ddr7 =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(200, 4)>, /* index=1 LOW SVS */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=2 LOW SVS */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=3 SVS */
|
||||
<MHZ_TO_KBPS(1017, 4)>, /* index=4 SVS */
|
||||
<MHZ_TO_KBPS(1353, 4)>, /* index=5 SVS L1 */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=6 NOM */
|
||||
<MHZ_TO_KBPS(1708, 4)>, /* index=7 NOM */
|
||||
<MHZ_TO_KBPS(2092, 4)>, /* index=8 TURBO */
|
||||
<MHZ_TO_KBPS(4761, 4)>; /* index=9*/
|
||||
|
||||
qcom,bus-table-ddr8 =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(200, 4)>, /* index=1 LOW SVS */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=2 LOW SVS */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=3 SVS */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=4 SVS */
|
||||
<MHZ_TO_KBPS(1708, 4)>, /* index=5 SVS L1 */
|
||||
<MHZ_TO_KBPS(2092, 4)>, /* index=6 NOM */
|
||||
<MHZ_TO_KBPS(2736, 4)>, /* index=7 TURBO */
|
||||
<MHZ_TO_KBPS(3196, 4)>, /* index=8 TURBO L1 */
|
||||
<MHZ_TO_KBPS(4761, 4)>; /* index=9*/
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&gpu_microcode_mem>;
|
||||
};
|
||||
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-reserved = <2048>;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-reserved = <1024>;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 128K Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <131072>;
|
||||
qcom,mempool-reserved = <128>;
|
||||
};
|
||||
/* 256K Page Pool configuration */
|
||||
qcom,gpu-mempool@4 {
|
||||
reg = <4>;
|
||||
qcom,mempool-page-size = <262144>;
|
||||
qcom,mempool-reserved = <80>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@5 {
|
||||
reg = <5>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
reg = <0x3da0000 0x40000>;
|
||||
|
||||
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x0 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x2 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gmu: qcom,gmu@3d37000 {
|
||||
compatible = "qcom,gen8-gmu";
|
||||
|
||||
reg = <0x3d37000 0x68000>,
|
||||
<0x3d40000 0x10000>;
|
||||
reg-names = "gmu", "gmu_ao_blk_dec0";
|
||||
|
||||
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hfi", "gmu";
|
||||
|
||||
regulator-names = "vddcx", "vdd";
|
||||
|
||||
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
||||
vdd-supply = <&gx_clkctl_gx_gdsc>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gpucc GPU_CC_HUB_CX_INT_CLK>;
|
||||
|
||||
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
|
||||
"memnoc_clk", "ahb_clk", "hub_clk";
|
||||
|
||||
qcom,gmu-freq-table = <350000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
|
||||
<650000000 RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,gmu-perf-ddr-bw = <MHZ_TO_KBPS(768, 4)>;
|
||||
|
||||
iommus = <&kgsl_smmu 0x5 0x000>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
|
||||
qcom,qmp = <&aoss_qmp>;
|
||||
};
|
||||
};
|
||||
305
qcom/graphics/gpu/volcano6-gpu-pwrlevels.dtsi
Normal file
305
qcom/graphics/gpu/volcano6-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,305 @@
|
||||
&msm_gpu {
|
||||
/* Power level bins */
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
compatible = "qcom,gpu-pwrlevels-bins";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <8>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_0, FC_Y1)
|
||||
SKU_CODE(PCODE_0, FC_Y0)>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1150000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <9>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <9>;
|
||||
qcom,bus-min-ddr8 = <8>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Turbo_L2>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <1050000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <9>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <9>;
|
||||
qcom,bus-min-ddr8 = <8>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Turbo_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <960000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <8>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Turbo>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <895000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <7>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <6>;
|
||||
qcom,bus-max-ddr8 = <8>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Nominal_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <763000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <7>;
|
||||
qcom,bus-min-ddr7 = <6>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Nominal>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <688000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <644000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <6>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <5>;
|
||||
qcom,bus-min-ddr8 = <4>;
|
||||
qcom,bus-max-ddr8 = <6>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <510000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <5>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <4>;
|
||||
qcom,bus-min-ddr8 = <3>;
|
||||
qcom,bus-max-ddr8 = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <362000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <264000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS_D1>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevels-1 {
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <5>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AB)
|
||||
SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <895000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <9>;
|
||||
qcom,bus-min-ddr7 = <7>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <9>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Nominal_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <763000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <7>;
|
||||
qcom,bus-min-ddr7 = <6>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <8>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Nominal>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <688000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <644000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <6>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <5>;
|
||||
qcom,bus-min-ddr8 = <4>;
|
||||
qcom,bus-max-ddr8 = <6>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <510000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <5>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <4>;
|
||||
qcom,bus-min-ddr8 = <3>;
|
||||
qcom,bus-max-ddr8 = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <362000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <264000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS_D1>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
21
qcom/graphics/gpu/volcano6-gpu.dts
Normal file
21
qcom/graphics/gpu/volcano6-gpu.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,volcano.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "volcano-gpu.dtsi"
|
||||
#include "volcano6-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6 SoC";
|
||||
compatible = "qcom,volcano";
|
||||
qcom,msm-id = <640 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
31
qcom/graphics/gpu/volcano6i-fp1-gpu-pwrlevels.dtsi
Normal file
31
qcom/graphics/gpu/volcano6i-fp1-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,31 @@
|
||||
&msm_gpu {
|
||||
/delete-property/ qcom,gpu-speed-bin;
|
||||
/delete-property/ qcom,initial-pwrlevel;
|
||||
/delete-node/ qcom,gpu-pwrlevels;
|
||||
/delete-node/ qcom,gpu-pwrlevel-bins;
|
||||
|
||||
/* GPU power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <0>;
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <264000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS_D1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
21
qcom/graphics/gpu/volcano6i-fp1-gpu.dts
Normal file
21
qcom/graphics/gpu/volcano6i-fp1-gpu.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,volcano.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "volcano-gpu.dtsi"
|
||||
#include "volcano6i-fp1-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6I FP1 SoC";
|
||||
compatible = "qcom,volcano";
|
||||
qcom,msm-id = <0x4000291 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
47
qcom/graphics/gpu/volcano6i-fp2-gpu-pwrlevels.dtsi
Normal file
47
qcom/graphics/gpu/volcano6i-fp2-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,47 @@
|
||||
&msm_gpu {
|
||||
/delete-property/ qcom,gpu-speed-bin;
|
||||
/delete-property/ qcom,initial-pwrlevel;
|
||||
/delete-node/ qcom,gpu-pwrlevels;
|
||||
/delete-node/ qcom,gpu-pwrlevel-bins;
|
||||
|
||||
/* GPU power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <1>;
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <362000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <264000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS_D1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
21
qcom/graphics/gpu/volcano6i-fp2-gpu.dts
Normal file
21
qcom/graphics/gpu/volcano6i-fp2-gpu.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,volcano.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "volcano-gpu.dtsi"
|
||||
#include "volcano6i-fp2-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6I FP2 SoC";
|
||||
compatible = "qcom,volcano";
|
||||
qcom,msm-id = <0x8000291 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
79
qcom/graphics/gpu/volcano6i-fp3-gpu-pwrlevels.dtsi
Normal file
79
qcom/graphics/gpu/volcano6i-fp3-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,79 @@
|
||||
&msm_gpu {
|
||||
/delete-property/ qcom,gpu-speed-bin;
|
||||
/delete-property/ qcom,initial-pwrlevel;
|
||||
/delete-node/ qcom,gpu-pwrlevels;
|
||||
/delete-node/ qcom,gpu-pwrlevel-bins;
|
||||
|
||||
/* GPU power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <3>;
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <644000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <6>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <5>;
|
||||
qcom,bus-min-ddr8 = <4>;
|
||||
qcom,bus-max-ddr8 = <6>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <510000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <5>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <4>;
|
||||
qcom,bus-min-ddr8 = <3>;
|
||||
qcom,bus-max-ddr8 = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <362000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <264000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS_D1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
21
qcom/graphics/gpu/volcano6i-fp3-gpu.dts
Normal file
21
qcom/graphics/gpu/volcano6i-fp3-gpu.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,volcano.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "volcano-gpu.dtsi"
|
||||
#include "volcano6i-fp3-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6I FP3 SoC";
|
||||
compatible = "qcom,volcano";
|
||||
qcom,msm-id = <0xc000291 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
185
qcom/graphics/gpu/volcano6i-fp4-gpu-pwrlevels.dtsi
Normal file
185
qcom/graphics/gpu/volcano6i-fp4-gpu-pwrlevels.dtsi
Normal file
@@ -0,0 +1,185 @@
|
||||
&msm_gpu {
|
||||
/* Power level bins */
|
||||
qcom,gpu-pwrlevel-bins {
|
||||
compatible = "qcom,gpu-pwrlevels-bins";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,gpu-pwrlevels-0 {
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,initial-pwrlevel = <8>;
|
||||
|
||||
qcom,sku-codes = <SKU_CODE(PCODE_0, FC_Y0)
|
||||
SKU_CODE(PCODE_0, FC_Y1)
|
||||
SKU_CODE(PCODE_5, FC_Y0)
|
||||
SKU_CODE(PCODE_5, FC_Y1)
|
||||
SKU_CODE(PCODE_UNKNOWN, FC_AA)
|
||||
SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <1150000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <9>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <9>;
|
||||
qcom,bus-min-ddr8 = <8>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Turbo_L2>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <1050000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <9>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <9>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <9>;
|
||||
qcom,bus-min-ddr8 = <8>;
|
||||
qcom,bus-max-ddr8 = <9>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Turbo_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <960000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <8>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <7>;
|
||||
qcom,bus-max-ddr8 = <8>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Turbo>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <895000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <8>;
|
||||
qcom,bus-min-ddr7 = <7>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <7>;
|
||||
qcom,bus-min-ddr8 = <6>;
|
||||
qcom,bus-max-ddr8 = <8>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Nominal_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <763000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <7>;
|
||||
qcom,bus-min-ddr7 = <6>;
|
||||
qcom,bus-max-ddr7 = <8>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_Nominal>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <688000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <6>;
|
||||
qcom,bus-min-ddr7 = <5>;
|
||||
qcom,bus-max-ddr7 = <7>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <6>;
|
||||
qcom,bus-min-ddr8 = <5>;
|
||||
qcom,bus-max-ddr8 = <7>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <644000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <5>;
|
||||
qcom,bus-min-ddr7 = <4>;
|
||||
qcom,bus-max-ddr7 = <6>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <5>;
|
||||
qcom,bus-min-ddr8 = <4>;
|
||||
qcom,bus-max-ddr8 = <6>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <510000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <4>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <5>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <4>;
|
||||
qcom,bus-min-ddr8 = <3>;
|
||||
qcom,bus-max-ddr8 = <5>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <362000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <264000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq-ddr7 = <2>;
|
||||
qcom,bus-min-ddr7 = <2>;
|
||||
qcom,bus-max-ddr7 = <4>;
|
||||
|
||||
qcom,bus-freq-ddr8 = <2>;
|
||||
qcom,bus-min-ddr8 = <2>;
|
||||
qcom,bus-max-ddr8 = <4>;
|
||||
|
||||
qcom,acd-level = <ACD_LEVEL_LowSVS_D1>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
21
qcom/graphics/gpu/volcano6i-fp4-gpu.dts
Normal file
21
qcom/graphics/gpu/volcano6i-fp4-gpu.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,volcano.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "volcano-gpu.dtsi"
|
||||
#include "volcano6i-fp4-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6I FP4 SoC";
|
||||
compatible = "qcom,volcano";
|
||||
qcom,msm-id = <0x10000291 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
21
qcom/graphics/gpu/volcano6ip-fp1-gpu.dts
Normal file
21
qcom/graphics/gpu/volcano6ip-fp1-gpu.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,volcano.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "volcano-gpu.dtsi"
|
||||
#include "volcano6i-fp1-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6IP FP1 SoC";
|
||||
compatible = "qcom,volcanop";
|
||||
qcom,msm-id = <0x4000292 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
21
qcom/graphics/gpu/volcano6ip-fp2-gpu.dts
Normal file
21
qcom/graphics/gpu/volcano6ip-fp2-gpu.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,volcano.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "volcano-gpu.dtsi"
|
||||
#include "volcano6i-fp2-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6IP FP2 SoC";
|
||||
compatible = "qcom,volcanop";
|
||||
qcom,msm-id = <0x8000292 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
21
qcom/graphics/gpu/volcano6ip-fp3-gpu.dts
Normal file
21
qcom/graphics/gpu/volcano6ip-fp3-gpu.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,volcano.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "volcano-gpu.dtsi"
|
||||
#include "volcano6i-fp3-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6IP FP3 SoC";
|
||||
compatible = "qcom,volcanop";
|
||||
qcom,msm-id = <0xc000292 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
21
qcom/graphics/gpu/volcano6ip-fp4-gpu.dts
Normal file
21
qcom/graphics/gpu/volcano6ip-fp4-gpu.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,volcano.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "volcano-gpu.dtsi"
|
||||
#include "volcano6i-fp4-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6IP FP4 SoC";
|
||||
compatible = "qcom,volcanop";
|
||||
qcom,msm-id = <0x10000292 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
21
qcom/graphics/gpu/volcano6p-gpu.dts
Normal file
21
qcom/graphics/gpu/volcano6p-gpu.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-volcano.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,volcano.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "volcano-gpu.dtsi"
|
||||
#include "volcano6-gpu-pwrlevels.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6P SoC";
|
||||
compatible = "qcom,volcanop";
|
||||
qcom,msm-id = <641 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
22
qcom/graphics/gpu/waipio-gpu.dts
Normal file
22
qcom/graphics/gpu/waipio-gpu.dts
Normal file
@@ -0,0 +1,22 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-waipio.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-waipio.h>
|
||||
#include <dt-bindings/clock/qcom,camcc-waipio.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,waipio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "waipio-gpu.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Waipio SoC";
|
||||
compatible = "qcom,waipio";
|
||||
qcom,msm-id = <457 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
|
||||
284
qcom/graphics/gpu/waipio-gpu.dtsi
Normal file
284
qcom/graphics/gpu/waipio-gpu.dtsi
Normal file
@@ -0,0 +1,284 @@
|
||||
|
||||
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
||||
|
||||
&soc {
|
||||
msm_gpu: qcom,kgsl-3d0@3d00000 {
|
||||
compatible = "qcom,adreno-gpu-gen7-0-0", "qcom,kgsl-3d0";
|
||||
status = "ok";
|
||||
reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
|
||||
<0x03d50000 0x10000>, <0x3d8b000 0x2000>,
|
||||
<0x03d9e000 0x1000>, <0x10900000 0x80000>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
|
||||
"isense_cntl", "cx_misc", "qdss_gfx";
|
||||
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
|
||||
clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
||||
<&clock_gpucc GPU_CC_AHB_CLK>,
|
||||
<&aoss_qmp QDSS_CLK>;
|
||||
clock-names = "gcc_gpu_memnoc_gfx",
|
||||
"gcc_gpu_snoc_dvm_gfx",
|
||||
"gpu_cc_ahb", "apb_pclk";
|
||||
|
||||
qcom,gpu-model = "Adreno730v1";
|
||||
|
||||
qcom,chipid = <0x07030000>;
|
||||
|
||||
qcom,initial-pwrlevel = <8>;
|
||||
|
||||
qcom,min-access-length = <32>;
|
||||
|
||||
qcom,ubwc-mode = <4>;
|
||||
|
||||
qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
|
||||
|
||||
qcom,tzone-names = "gpuss-0", "gpuss-1";
|
||||
|
||||
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "gpu_icc_path";
|
||||
|
||||
qcom,bus-table-cnoc =
|
||||
<0>, /* Off */
|
||||
<100>; /* On */
|
||||
|
||||
qcom,bus-table-ddr =
|
||||
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
||||
<MHZ_TO_KBPS(200, 4)>, /* index=1 */
|
||||
<MHZ_TO_KBPS(451, 4)>, /* index=2 */
|
||||
<MHZ_TO_KBPS(547, 4)>, /* index=3 */
|
||||
<MHZ_TO_KBPS(681, 4)>, /* index=4 */
|
||||
<MHZ_TO_KBPS(768, 4)>, /* index=5 */
|
||||
<MHZ_TO_KBPS(1555, 4)>, /* index=6 */
|
||||
<MHZ_TO_KBPS(1708, 4)>, /* index=7 */
|
||||
<MHZ_TO_KBPS(2092, 4)>, /* index=8 */
|
||||
<MHZ_TO_KBPS(2736, 4)>, /* index=9 */
|
||||
<MHZ_TO_KBPS(3196, 4)>, /* index=10 */
|
||||
<MHZ_TO_KBPS(3350, 4)>; /* index=11 */
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&gpu_micro_code_mem>;
|
||||
};
|
||||
|
||||
/* Power levels */
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <818000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x882c5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <791000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x882c5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <734000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x882d5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <640000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0xa82d5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <599000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <545000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <492000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <421000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
qcom,acd-level = <0xa82e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <350000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <2>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <6>;
|
||||
|
||||
qcom,acd-level = <0x882f5ffd>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,gpu-mempools {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,gpu-mempools";
|
||||
|
||||
/* 4K Page Pool configuration */
|
||||
qcom,gpu-mempool@0 {
|
||||
reg = <0>;
|
||||
qcom,mempool-page-size = <4096>;
|
||||
qcom,mempool-reserved = <2048>;
|
||||
};
|
||||
/* 8K Page Pool configuration */
|
||||
qcom,gpu-mempool@1 {
|
||||
reg = <1>;
|
||||
qcom,mempool-page-size = <8192>;
|
||||
qcom,mempool-reserved = <1024>;
|
||||
};
|
||||
/* 64K Page Pool configuration */
|
||||
qcom,gpu-mempool@2 {
|
||||
reg = <2>;
|
||||
qcom,mempool-page-size = <65536>;
|
||||
qcom,mempool-reserved = <256>;
|
||||
};
|
||||
/* 128K Page Pool configuration */
|
||||
qcom,gpu-mempool@3 {
|
||||
reg = <3>;
|
||||
qcom,mempool-page-size = <131072>;
|
||||
qcom,mempool-reserved = <128>;
|
||||
};
|
||||
/* 256K Page Pool configuration */
|
||||
qcom,gpu-mempool@4 {
|
||||
reg = <4>;
|
||||
qcom,mempool-page-size = <262144>;
|
||||
qcom,mempool-reserved = <80>;
|
||||
};
|
||||
/* 1M Page Pool configuration */
|
||||
qcom,gpu-mempool@5 {
|
||||
reg = <5>;
|
||||
qcom,mempool-page-size = <1048576>;
|
||||
qcom,mempool-reserved = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
|
||||
compatible = "qcom,kgsl-smmu-v2";
|
||||
reg = <0x03da0000 0x40000>;
|
||||
|
||||
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
||||
|
||||
gfx3d_user: gfx3d_user {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x0 0x400>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_lpac: gfx3d_lpac {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x1 0x400>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
|
||||
gfx3d_secure: gfx3d_secure {
|
||||
compatible = "qcom,smmu-kgsl-cb";
|
||||
iommus = <&kgsl_smmu 0x2 0x400>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gmu: qcom,gmu@3d69000 {
|
||||
compatible = "qcom,gen7-gmu";
|
||||
|
||||
reg = <0x3d68000 0x37000>,
|
||||
<0xb290000 0x10000>,
|
||||
<0x03D40000 0x10000>;
|
||||
|
||||
reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
|
||||
|
||||
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hfi", "gmu";
|
||||
|
||||
regulator-names = "vddcx", "vdd";
|
||||
|
||||
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
||||
vdd-supply = <&gpu_cc_gx_gdsc>;
|
||||
|
||||
clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&clock_gpucc GPU_CC_CXO_CLK>,
|
||||
<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&clock_gpucc GPU_CC_AHB_CLK>,
|
||||
<&clock_gpucc GPU_CC_HUB_CX_INT_CLK>,
|
||||
<&aoss_qmp>;
|
||||
|
||||
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
|
||||
"memnoc_clk", "ahb_clk", "hub_clk", "apb_pclk";
|
||||
|
||||
|
||||
iommus = <&kgsl_smmu 0x5 0x400>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
|
||||
mboxes = <&qmp_aop 0>;
|
||||
mbox-names = "aop";
|
||||
};
|
||||
};
|
||||
22
qcom/graphics/gpu/waipio-v2-gpu.dts
Normal file
22
qcom/graphics/gpu/waipio-v2-gpu.dts
Normal file
@@ -0,0 +1,22 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-waipio.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-waipio.h>
|
||||
#include <dt-bindings/clock/qcom,camcc-waipio.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,waipio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "waipio-v2-gpu.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Waipio v2 SoC";
|
||||
compatible = "qcom,waipio";
|
||||
qcom,msm-id = <457 0x20000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
|
||||
137
qcom/graphics/gpu/waipio-v2-gpu.dtsi
Normal file
137
qcom/graphics/gpu/waipio-v2-gpu.dtsi
Normal file
@@ -0,0 +1,137 @@
|
||||
&msm_gpu {
|
||||
|
||||
compatible = "qcom,adreno-gpu-gen7-0-1", "qcom,kgsl-3d0";
|
||||
|
||||
qcom,initial-pwrlevel = <9>;
|
||||
|
||||
qcom,gpu-model = "Adreno730v2";
|
||||
|
||||
qcom,chipid = <0x07030001>;
|
||||
|
||||
qcom,gpu-pwrlevels {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
reg = <0>;
|
||||
qcom,gpu-freq = <818000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <11>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x882c5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
reg = <1>;
|
||||
qcom,gpu-freq = <791000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
|
||||
qcom,bus-freq = <11>;
|
||||
qcom,bus-min = <10>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x882c5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@2 {
|
||||
reg = <2>;
|
||||
qcom,gpu-freq = <734000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <9>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0x882d5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@3 {
|
||||
reg = <3>;
|
||||
qcom,gpu-freq = <640000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
|
||||
qcom,bus-freq = <10>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <11>;
|
||||
|
||||
qcom,acd-level = <0xa82d5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@4 {
|
||||
reg = <4>;
|
||||
qcom,gpu-freq = <599000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@5 {
|
||||
reg = <5>;
|
||||
qcom,gpu-freq = <545000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
||||
|
||||
qcom,bus-freq = <8>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <9>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@6 {
|
||||
reg = <6>;
|
||||
qcom,gpu-freq = <492000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <6>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
qcom,acd-level = <0x882e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@7 {
|
||||
reg = <7>;
|
||||
qcom,gpu-freq = <421000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
||||
|
||||
qcom,bus-freq = <6>;
|
||||
qcom,bus-min = <3>;
|
||||
qcom,bus-max = <8>;
|
||||
|
||||
qcom,acd-level = <0xa82e5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@8 {
|
||||
reg = <8>;
|
||||
qcom,gpu-freq = <350000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
|
||||
qcom,bus-freq = <3>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <6>;
|
||||
|
||||
qcom,acd-level = <0x882f5ffd>;
|
||||
};
|
||||
|
||||
qcom,gpu-pwrlevel@9 {
|
||||
reg = <9>;
|
||||
qcom,gpu-freq = <285000000>;
|
||||
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
|
||||
qcom,bus-freq = <2>;
|
||||
qcom,bus-min = <1>;
|
||||
qcom,bus-max = <5>;
|
||||
|
||||
qcom,acd-level = <0x882f5ffd>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user