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dt-bindings: Documentation for various dt nodes

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Dcumentation for various nodes required for Direwolf SOC that are
not yet documented.
The files are snapshots from msm-5.15 branch at
commit 5fdc57d28171 ("dt-bindings: msm-gen-uart: Add property
for compat IOCTL").

Change-Id: If71c2fade904df3648cd29e4670b6636ce014063
This commit is contained in:
Abdul Salam
2023-03-17 18:25:24 +05:30
parent fdfecc1726
commit ab1f9aecc5
15 changed files with 761 additions and 0 deletions
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17
bindings/arm/msm/msm.txt
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@@ -101,6 +101,10 @@ SoCs:
- PINEAPPLE
compatible = "qcom,pineapple", "qcom,pineapplep"
- LEMANS
compatible = "qcom,lemans"
Generic board variants:
- CDP device:
@@ -290,3 +294,16 @@ compatible = "qcom,pineapplep-cdp"
compatible = "qcom,pineapplep-qrd"
compatible = "qcom,pineapplep-atp"
compatible = "qcom,pineapplep-rcm"
compatible = "qcom,quinvm"
compatible = "qcom,lemans-rumi"
compatible = "qcom,lemans-ivi"
compatible = "qcom,lemans-ivi-adas"
compatible = "qcom,lemans-ivi-adp-air"
compatible = "qcom,lemans-ivi-adp-star"
compatible = "qcom,lemans-ivi-qam-star"
compatible = "qcom,lemans-adas-high"
compatible = "qcom,lemans-adas-high-adp-air"
compatible = "qcom,lemans-adas-high-adp-star"
compatible = "qcom,lemans-adas-high-qam-star"
compatible = "qcom,lemans-ivi-adas-adp-star"
compatible = "qcom,lemans-ivi-adas-qam-star"

111
bindings/arm/psci.txt Normal file
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@@ -0,0 +1,111 @@
* Power State Coordination Interface (PSCI)
Firmware implementing the PSCI functions described in ARM document number
ARM DEN 0022A ("Power State Coordination Interface System Software on ARM
processors") can be used by Linux to initiate various CPU-centric power
operations.
Issue A of the specification describes functions for CPU suspend, hotplug
and migration of secure software.
Functions are invoked by trapping to the privilege level of the PSCI
firmware (specified as part of the binding below) and passing arguments
in a manner similar to that specified by AAPCS:
r0 => 32-bit Function ID / return value
{r1 - r3} => Parameters
Note that the immediate field of the trapping instruction must be set
to #0.
Main node required properties:
- compatible : should contain at least one of:
* "arm,psci" : For implementations complying to PSCI versions prior
to 0.2.
For these cases function IDs must be provided.
* "arm,psci-0.2" : For implementations complying to PSCI 0.2.
Function IDs are not required and should be ignored by
an OS with PSCI 0.2 support, but are permitted to be
present for compatibility with existing software when
"arm,psci" is later in the compatible list.
* "arm,psci-1.0" : For implementations complying to PSCI 1.0.
PSCI 1.0 is backward compatible with PSCI 0.2 with
minor specification updates, as defined in the PSCI
specification[2].
- method : The method of calling the PSCI firmware. Permitted
values are:
"smc" : SMC #0, with the register assignments specified
in this binding.
"hvc" : HVC #0, with the register assignments specified
in this binding.
Main node optional properties:
- cpu_suspend : Function ID for CPU_SUSPEND operation
- cpu_off : Function ID for CPU_OFF operation
- cpu_on : Function ID for CPU_ON operation
- migrate : Function ID for MIGRATE operation
Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
state nodes, as per bindings in [1]) must specify the following properties:
- arm,psci-suspend-param
Usage: Required for state nodes[1] if the corresponding
idle-states node entry-method property is set
to "psci".
Value type: <u32>
Definition: power_state parameter to pass to the PSCI
suspend call.
Example:
Case 1: PSCI v0.1 only.
psci {
compatible = "arm,psci";
method = "smc";
cpu_suspend = <0x95c10000>;
cpu_off = <0x95c10001>;
cpu_on = <0x95c10002>;
migrate = <0x95c10003>;
};
Case 2: PSCI v0.2 only
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
Case 3: PSCI v0.2 and PSCI v0.1.
A DTB may provide IDs for use by kernels without PSCI 0.2 support,
enabling firmware and hypervisors to support existing and new kernels.
These IDs will be ignored by kernels with PSCI 0.2 support, which will
use the standard PSCI 0.2 IDs exclusively.
psci {
compatible = "arm,psci-0.2", "arm,psci";
method = "hvc";
cpu_on = < arbitrary value >;
cpu_off = < arbitrary value >;
...
};
[1] Kernel documentation - ARM idle states bindings
Documentation/devicetree/bindings/arm/idle-states.txt
[2] Power State Coordination Interface (PSCI) specification
http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf

26
bindings/firmware/qcom,scm.txt
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@@ -29,6 +29,9 @@ Required properties:
* "qcom,scm-sm8350"
and:
* "qcom,scm"
* "qcom,scm-v1.1" for firmwares that support waitqueue-based operation.
* "android,firmware" for firmware image
* "android,vbmeta" for setting system properties for verified boot.
- clocks: Specifies clocks needed by the SCM interface, if any:
* core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and
"qcom,scm-msm8960"
@@ -50,3 +53,26 @@ Example for MSM8916:
clock-names = "core", "bus", "iface";
};
};
Example for SM6150:
firmware: firmware {
android {
compatible = "android,firmware";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
fsmgr_flags = "wait,slotselect,avb";
status = "ok";
};
};
};
};

28
bindings/iommu/virt,smmu-v3.txt Normal file
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@@ -0,0 +1,28 @@
* Paravirtualized ARM SMMUv3
The Parvirt smmu-v3 driver communicates with the underlying
hypervisor to provide S1 translation context descriptor and
other properties which is set by the client. The backend SMMUv3
driver in hypervisor is supposed to program the SMMUv3 hardware
with the information from the paravirt SMMUv3 driver.
** Paravirt SMMUv3 required properties:
- compatible : Should include:
"arm,virt-smmu-v3"
- #iommu-cells : See the generic IOMMU binding described in
devicetree/bindings/pci/pci-iommu.txt
for details. For Paravirt SMMUv3, must be 1,
with each cell describing a single stream ID.
All possible stream IDs which a device may
emit must be described.
** Example
virt_smmuv3: qcom,virt-smmuv3 {
#iommu-cells = <1>;
compatible = "arm,virt-smmu-v3";
};

102
bindings/platform/msm/usb-bam.txt Normal file
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@@ -0,0 +1,102 @@
MSM USB Bus Access Manager (BAM)
This describes the device used to interface the USB controller
with the Smart Peripheral Subsystem (SPS). The BAM serves to
connect USB directly with other peer peripherals in the system
and is statically configured with a number of unidirectional pipes.
Required properties:
- compatible: should be "qcom,usb-bam-msm"
- reg : pair of physical base addresses and region size of BAM device
- interrupts: IRQ line for BAM device
- qcom,usb-bam-num-pipes: max number of pipes that can be used
Optional properties:
- qcom,usb-bam-fifo-baseaddr: base address for bam pipe's data and descriptor
fifos. This can be on chip memory (ocimem). This
property is required if sub-node's mem-type is ocimem or usb private mem.
- qcom,disable-clk-gating: If present then disable BAM clock gating.
- qcom,usb-bam-override-threshold: If present then the default 512 byte threshold
is overridden. This threshold configures the threshold value for Read/Write
event generation by the BAM towards another BAM.
- qcom,usb-bam-max-mbps-highspeed: max mbps in high speed connection
for either rx or tx direction.
- qcom,usb-bam-max-mbps-superspeed: max mbps in super speed connection
for either rx or tx direction.
- qcom,reset-bam-on-connect: If present then BAM is RESET before connecting
pipe. This may be required if BAM peripheral is also reset before connect.
- qcom,reset-bam-on-disconnect: If present then BAM is RESET after disconnecting pipes.
A number of USB BAM pipe parameters are represented as sub-nodes:
Subnode Required:
- label: a string describing uniquely the usb bam pipe. The string can be
constracted as follows: <core>-<peer>-<direction>-<pipe num>.
core options: hsusb, ssusb/dwc3, hsic
peer options: qdss, ipa
direction options: in (from peer to usb), out (from usb to peer)
pipe num options: 0..127
- qcom,usb-bam-mem-type: Type of memory used by this PIPE. Can be one of
0 - Uses SPS's dedicated pipe memory
1 - System RAM allocated by driver
2 - OCI memory residing @ 'qcom,usb-bam-fifo-baseaddr'
- qcom,dir: pipe direction
0 - from usb (out)
1 - to usb (in)
- qcom,pipe-num: pipe number
- qcom,peer-bam: peer BAM can be one of
0 - QDSS_P_BAM
1 - IPA_P_BAM
- qcom,data-fifo-size: data fifo size
- qcom,descriptor-fifo-size: descriptor fifo size
Optional Properties for Subnode:
- qcom,peer-bam-physical-address: peer BAM's physical address.
Not specified for IPA and used only for qdss connection
- qcom,dst-bam-pipe-index: destination BAM pipe index
- qcom,src-bam-pipe-index: source BAM pipe index
- qcom,data-fifo-offset: data fifo offset address
- qcom,descriptor-fifo-offset: descriptor fifo offset address
- qcom,pipe-connection-type: type of pipe connection. Can be one of
0 - BAM2BAM (default if not specified)
1 - SYS2BAM (only supported on UL)
Example USB BAM controller device node:
qcom,usbbam@f9a44000 {
compatible = "qcom,usb-bam-msm";
reg = <0xf9a44000 0x11000>;
interrupts = <0 135 0>;
qcom,usb-bam-num-pipes = <16>;
qcom,ignore-core-reset-ack;
qcom,disable-clk-gating;
qcom,usb-bam-max-mbps-highspeed = <400>;
qcom,usb-bam-max-mbps-superspeed = <3600>;
qcom,bam-type = <1>;
qcom,bam-mode = <0>;
qcom,pipe0 {
label = "hsusb-ipa-out-0";
qcom,usb-bam-mem-type = <0>;
qcom,dir = <0>;
qcom,pipe-num = <0>;
qcom,peer-bam = <2>;
qcom,src-bam-pipe-index = <1>;
qcom,data-fifo-offset = <0x2200>;
qcom,data-fifo-size = <0x1e00>;
qcom,descriptor-fifo-offset = <0x2100>;
qcom,descriptor-fifo-size = <0x100>;
};
qcom,pipe1 {
label = "hsusb-ipa-in-0";
qcom,usb-bam-mem-type = <0>;
qcom,dir = <1>;
qcom,pipe-num = <0>;
qcom,peer-bam = <2>;
qcom,dst-bam-pipe-index = <0>;
qcom,data-fifo-offset = <0x300>;
qcom,data-fifo-size = <0x1e00>;
qcom,descriptor-fifo-offset = <0>;
qcom,descriptor-fifo-size = <0x300>;
};
};

14
bindings/power/reset/qcom,vm-restart.txt Normal file
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@@ -0,0 +1,14 @@
Qualcomm Technologies, Inc. VM Restart Driver binding
-----------------------------------------------------
* VM Restart Driver
VM restart driver supports virtual machine power down and restart.
Required properties:
- compatible: Must be "qcom,vm-restart"
Example:
vm_restart: restart {
compatible = "qcom,vm-restart";
};

85
bindings/qseecom/qseecom.txt Normal file
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@@ -0,0 +1,85 @@
* QSEECOM (QTI Secure Execution Environment Communicator)
Required properties:
- compatible : Should be "qcom,qseecom"
- reg : should contain memory region address reserved for loading secure apps.
- qcom,disk-encrypt-pipe-pair : indicates what CE HW pipe pair is used for disk encryption
- qcom,file-encrypt-pipe-pair : indicates what CE HW pipe pair is used for file encryption
- qcom,support-multiple-ce-hw-instance : indicates if multicore CE support is supported.
- qcom,hlos-num-ce-hw-instances : indicates number of CE HW instances hlos can use.
- qcom,hlos-ce-hw-instance : indicates what CE HW is used by HLOS crypto driver
- qcom,qsee-ce-hw-instance : indicates what CE HW is used by secure domain (TZ) crypto driver
- qcom, msm_bus,name: Should be "qseecom-noc"
- qcom, msm_bus,num_cases: Depends on the use cases for bus scaling
- qcom, msm_bus,num_paths: The paths for source and destination ports
- qcom, msm_bus,vectors: Vectors for bus topology.
- qcom,ce-opp-freq: indicates the CE operating frequency in Hz, changes from target to target.
- qcom,full-disk-encrypt-info : Vectors defining full disk encryption unit, crypto engine, pipe pair configuration in <unit#, ce#, pipe-pair#>
- qcom,per-file-encrypt-info : Vectors defining per file encryption unit, crypto engine, pipe pair configuration in <unit#, ce#, pipe-pair#>
Optional properties:
- qcom,support-bus-scaling : indicates if driver support scaling the bus for crypto operation.
- qcom,support-fde : indicates if driver support key managing for full disk encryption feature.
- qcom,support-pfe : indicates if driver support key managing for per file encryption feature.
- qcom,no-clock-support : indicates clocks are not handled by qseecom (could be handled by RPM)
- qcom,appsbl-qseecom-support : indicates if there is qseecom support in appsbootloader
- vdd-hba-supply : handle for fixed power regulator
- qcom,qsee-reentrancy-support: indicates the qsee reentrancy phase supported by the target
- qcom,commonlib64-loaded-by-uefi: indicates commonlib64 is loaded by uefi already
- qcom,fde-key-size: indicates which FDE key size is used in device.
Example:
qcom,qseecom@7f00000 {
compatible = "qcom,qseecom";
reg = <0x7f00000 0x500000>;
reg-names = "secapp-region";
qcom,disk-encrypt-pipe-pair = <2>;
qcom,file-encrypt-pipe-pair = <0>;
qcom,support-multiple-ce-hw-instance;
qcom,hlos-num-ce-hw-instances = <2>;
qcom,hlos-ce-hw-instance = <1 2>;
qcom,qsee-ce-hw-instance = <0>;
qcom,support-fde;
qcom,support-pfe;
qcom,msm_bus,name = "qseecom-noc";
qcom,msm_bus,num_cases = <4>;
qcom,msm_bus,active_only = <0>;
qcom,msm_bus,num_paths = <1>;
qcom,no-clock-support;
qcom,appsbl-qseecom-support;
qcom,fde-key-size;
qcom,msm_bus,vectors =
<55 512 0 0>,
<55 512 3936000000 393600000>,
<55 512 3936000000 393600000>,
<55 512 3936000000 393600000>;
qcom,ce-opp-freq = <100000000>;
vdd-hba-supply = <&gdsc_ufs>;
};
Example: The following dts setup is the same as the example above.
qcom,qseecom@7f00000 {
compatible = "qcom,qseecom";
reg = <0x7f00000 0x500000>;
reg-names = "secapp-region";
qcom,support-fde;
qcom,full-disk-encrypt-info = <0 1 2>, <0 2 2>;
qcom,support-pfe;
qcom,per-file-encrypt-info = <0 1 0>, <0 2 0>;
qcom,qsee-ce-hw-instance = <0>;
qcom,msm_bus,name = "qseecom-noc";
qcom,msm_bus,num_cases = <4>;
qcom,msm_bus,active_only = <0>;
qcom,msm_bus,num_paths = <1>;
qcom,no-clock-support;
qcom,appsbl-qseecom-support;
qcom,fde-key-size;
qcom,msm_bus,vectors =
<55 512 0 0>,
<55 512 3936000000 393600000>,
<55 512 3936000000 393600000>,
<55 512 3936000000 393600000>;
qcom,ce-opp-freq = <100000000>;
vdd-hba-supply = <&gdsc_ufs>;
};

32
bindings/soc/hgsl.txt Normal file
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@@ -0,0 +1,32 @@
* HGSL
HGSL(Hypervisor Graphics system layer) is graphics driver under the hypervisor system.
Required properties:
- compatible : Must be "qcom,hgsl"
- reg : physical base address and length of the register set(s).
- reg-names : names corresponding to each reg property value.
reg_hwver: HW version registers
reg_doorbell_idx: address of GMUAO_DOORBELL_IDX
Optional properties:
- db-off: Disable Doorbell feature but keep hgsl for ifence service
- qcom,glb-db-senders : Point to possible nodes of HGSL TCSR sender. The user will select
which sender to use. The driver will use TCSR compute signal to
send signal to GPU.
- qcom,glb-db-receivers : Point to possible nodes of HGSL TCSR receiver. The user will
select which receiver to use. The driver will use TCSR compute
signal to receive signal from GPU.
Example:
msm_gpu_hyp {
compatible = "qcom,hgsl";
reg = <0x2c00000 0x8>, <0x2c8f000 0x4>;
reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx";
db-off = <0>;
qcom,glb-db-senders = <&hgsl_tcsr_sender0 &hgsl_tcsr_sender1>;
qcom,glb-db-receivers = <&hgsl_tcsr_receiver0 &hgsl_tcsr_receiver1>;
};

19
bindings/soc/qcom/guest_shm.txt Normal file
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@@ -0,0 +1,19 @@
QVM Guest Shared Memory
guest_shm is a device that enables linux as a guest operating system
to allocate shared memory between virtual machines and send notifications
of updates to other virtual machines.
Required properties:
- compatible: Must be "qvm,guest_shm".
- interrupt-parent: Parent interrupt controller.
- interrupts: Should contain QVM interrupt.
- reg: Physical address of the guest factory and length.
Example:
qvm,guest_shm {
compatible = "qvm,guest_shm";
interrupt-parent = <&gic>;
interrupts = <6 4>;
reg = <0x1c050000 0x1000>;
};

44
bindings/soc/qcom/hab.txt Normal file
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@@ -0,0 +1,44 @@
* HAB
HAB(Hypervisor ABstraction) is meant to be a cross-platform abstraction layer
for utilizing the underlying hypervisor system. This API can be accessed from
both user and kernel sides.
The intended users of this are primarily the multimedia drivers who want to
communicate with the host OS to use the multimedia hardware.
Required properties:
- compatible: Must be "qcom,hab"
- vmid: the local VM's ID
It should be unique in a system, and host's ID should be 0. Here is an
example for a system as qvm host + agl gvm + android gvm, and such below
setting is proper,
qvm host's vmid: 0
agl gvm's vmid: 1
android gvm's vmid: 2
- mmid group properties:
- grp-start-id: mmid group starting ID, eg, 100 is for MM_AUD_1~4
- role: the local role of this group, and must be "fe" or "be"
- remote-vmids: When the local role is "fe", this is to tell which VM is the
relevant BE. When it is "be", this is to tell which VMs it will support as
BE.
- kernel_only: If the current mmid group can only be accessed by kernel hab
clients, please add this property.
Example:
qcom,hab {
compatible = "qcom,hab";
vmid = <2>;
mmid100: mmid-grp@100 {
grp-start-id = <100>;
role = "fe";
remote-vmids = <0>;
};
mmid200: mmid-grp@200 {
grp-start-id = <200>;
role = "fe";
remote-vmids = <0>;
kernel_only;
};
}

31
bindings/soc/qcom/hgsl-tcsr.txt Normal file
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@@ -0,0 +1,31 @@
Top Control and Status Register(TCSR) for HGSL
TCSR hardware contains compute signal sub-block, which allows drivers in hypervisor
Linux to communicate with GPU hardware directly. This HGSL TCSR driver is to enable
the TCSR compute signal hardware. There are multiple instances of compute signal.
Each instance is either a signal sender or signal receiver.
The HGSL TCSR driver is built on top of generic TCSR driver, refer to
Documentation/devicetree/bindings/mfd/qcom,tcsr.txt for the generic TCSR driver.
Required properties:
- compatible : Must be "qcom,hgsl-tcsr-sender" or "qcom,hgsl-tcsr-receiver"
- syscon : Point to the generic TCSR compute signal node
- syscon-glb : Point to the generice TCSR node for compute signal global control.
This is only needed by signal sender.
- interrupts : Specify IRQ information used by the compute signal.
This is only needed by signal receiver.
Examples:
hgsl_tcsr_sender0: hgsl_tcsr_sender0 {
compatible = "qcom,hgsl-tcsr-sender";
syscon = <&tcsr_compute_signal_sender0>;
syscon-glb = <&tcsr_compute_signal_glb>;
};
hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 {
compatible = "qcom,hgsl-tcsr-receiver";
syscon = <&tcsr_compute_signal_receiver0>;
interrupts = <0 238 0>;
};

29
bindings/soc/qcom/qcom,power-state.txt Normal file
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@@ -0,0 +1,29 @@
* Qualcomm Technologies, Inc. Power State Driver
This binding describes the Qualcomm Technologies, Inc. Power State Driver. Power
State creates power_state device node for user space communication. User space
client can open device node for communication and driver accordingly handles the
request.
Required Properties:
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,power-state"
- subsys-name:
Usage: required
Value type: <string>
Description: subsystem names supported
- rproc-handle:
Usage: required
Description: phandle to subsys defined in subsys-name.
Example:
qcom,power-state {
compatible = "qcom,power-state";
qcom,subsys-name = "adsp", "modem";
qcom,rproc-handle = <&adsp_pas>, <&modem_pas>;
};

29
bindings/soc/qcom/rename_devices.txt Normal file
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@@ -0,0 +1,29 @@
* rename devices
Required properties for block devices rename:
- compatible: "qcom,rename-devices" compatibility string
- device-type: Device type to be renamed and supported device-types are block
- actual-dev: Original name of the disk assigned by generic driver
- rename-dev: New name of the disk or to set for disks respectively
Example:
rename_devices: rename_devices {
compatible = "qcom,rename-devices";
rename_blk: rename_blk {
device-type = "block";
actual-dev = "vda", "vdb", "vdc",
"vdd", "vde", "vdf",
"vdg", "vdh", "vdi",
"vdj", "vdk", "vdl",
"vdm", "vdn", "vdo",
"vdp", "vdq";
rename-dev = "super", "userdata", "metadata",
"persist", "modem_a", "modem_b",
"bluetooth_a", "bluetooth_b",
"misc", "vbmeta_a", "vbmeta_b",
"boot_a", "boot_b", "dtbo_a",
"dtbo_b", "dsp_a", "dsp_b";
};
};

187
bindings/sound/qcom,hsi2s.txt Normal file
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Qualcomm Technologies, Inc. High Speed I2S Interface
* HS-I2S generic node
Required properties:
- compatible : Should include "qcom,hsi2s"
Should include target specific compatible field
"qcom,sa6155-hsi2s" for SA6155
"qcom,sa8155-hsi2s" for SA8155
"qcom,sa8195-hsi2s" for SA8195
- number-of-interfaces : Denotes the number of HS-I2S interfaces
- reg : Specifies the base physical address and the size of the HS-I2S
register space
- reg-names : "lpa_if" - string to identify the HS-I2S base register
- interrupts : Interrupt number used by this interface
- clocks : Core clocks used by this interface
- clock-names : Clock names for each core clock
- iommus: The phandle and stream IDs for the SMMU used by this root
- qcom,iommu-dma-addr-pool: Specifies the start address and size of iova space
Optional properties:
- number-of-rate-detectors : Number of rate detectors to enable
0 - Doesn't enable rate detectors
1 - Enables primary rate detector
2 - Enables both primary and secondary
rate detectors
- rate-detector-interfaces : Specifies the minor number of the interfaces
to have rate detection enabled
* HS-I2S interface nodes
Required properties:
- compatible : Should be "qcom,hsi2s-interface"
- minor-number : Minor number of the character device interface
Should be 0 for HS0 interface
Should be 1 for HS1 interface
Should be 2 for HS2 interface
- clocks : Interface clock used by this interface
- clock-names : Clock name for the interface clock
- pinctrl-names : Pinctrl state names for each pin group configuration
- pinctrl-x : Defines pinctrl state for each pin group
- bit-clock-hz : Default bit clock frequency in hertz
- data-buffer-ms : Default periodic interrupt interval in milliseconds
Optional properties:
- bit-depth : Bit depth of the I2S data
Default - 32
- spkr-channel-count : Number of speaker channels
Default - 2
- mic-channel-count : Number of mic channels
Default - 2
- pcm-rate : Number of bit clocks per PCM frame
0 - ENUM_8
1 - ENUM_16
2 - ENUM_32 (Default)
3 - ENUM_64
4 - ENUM_128
5 - ENUM_256
- pcm-sync-src : Specifies whether the PCM block uses internal or
external sync
0 - External (Default)
1 - Internal
- aux-mode : Specifies the type of sync expected/generated by the
PCM block.
0 - PCM (Short sync) (Default)
1 - Aux PCM (Long sync)
- rpcm-width : Number of bits per receive slot
0 - 8 bits
1 - 16 bits (Default)
- tpcm-width : Number of bits per transmit slot
0 - 8 bits
1 - 16 bits (Default)
- enable-tdm : Specifies whether TDM is enabled by default
0 - Disable TDM
1 - Enable TDM (Default)
- tdm-rate : Number of bit clocks per TDM frame
Maximum permissible value is 512
Default - 32
- tdm-rpcm-width : Number of bits per receive slot in TDM
Maximum permissible value is 32
Default - 16
- tdm-tpcm-width : Number of bits per transmit slot in TDM
Maximum permissible value is 32
Default - 16
- tdm-sync-delay : Specifies the data delay relative to sync pulse
0 - First data appears two cycles after frame pulse
1 - First data appears one cycle after frame pulse
2 - First data and frame pulse occur on the same cycle
Default - 2
- tdm-inv-sync : Specifies whether the frame sync has to be inverted
in long sync(Aux PCM) mode
0 - Do not invert frame sync (Default)
1 - Invert frame sync
- pcm-lane-config : Specifies the PCM data lane configuration
0 - Single lane
D0 - MIC
D1 - SPEAKER
1 - Multi lane Rx (Default)
D0 - MIC
D1 - MIC
2 - Multi lane Tx
D0 - SPEAKER
D1 - SPEAKER
Example:
hsi2s: qcom,hsi2s {
compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s";
number-of-interfaces = <2>;
reg = <0x1B40000 0x28000>;
reg-names = "lpa_if";
interrupts = <GIC_SPI 267 0>;
clocks = <&clock_gcc GCC_SDR_CORE_CLK>,
<&clock_gcc GCC_SDR_WR0_MEM_CLK>,
<&clock_gcc GCC_SDR_WR1_MEM_CLK>,
<&clock_gcc GCC_SDR_WR2_MEM_CLK>,
<&clock_gcc GCC_SDR_CSR_HCLK>;
clock-names = "core_clk", "wr0_mem_clk",
"wr1_mem_clk", "wr2_mem_clk",
"csr_hclk";
number-of-rate-detectors = <2>;
rate-detector-interfaces = <0 1>;
iommus = <&apps_smmu 0x035C 0x1>;
qcom,iommu-dma-addr-pool = <0x0 0xFFFFFFFF>;
sdr0: qcom,hs0_i2s {
compatible = "qcom,hsi2s-interface";
minor-number = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hs0_i2s_sck_active &hs0_i2s_data0_active
&hs0_i2s_data1_active>;
pinctrl-1 = <&hs0_i2s_sck_sleep &hs0_i2s_data0_sleep
&hs0_i2s_data1_sleep>;
clocks = <&clock_gcc GCC_SDR_PRI_MI2S_CLK>;
clock-names = "pri_mi2s_clk";
bit-clock-hz = <12288000>;
data-buffer-ms = <10>;
bit-depth = <32>;
spkr-channel-count = <2>;
mic-channel-count = <2>;
pcm-rate = <2>;
pcm-sync-src = <0>;
aux-mode = <0>;
rpcm-width = <1>;
tpcm-width = <1>;
enable-tdm = <1>;
tdm-rate = <32>;
tdm-rpcm-width = <16>;
tdm-tpcm-width = <16>;
tdm-sync-delay = <2>;
tdm-inv-sync = <0>;
pcm-lane-config = <1>;
};
sdr1: qcom,hs1_i2s {
compatible = "qcom,hsi2s-interface";
minor-number = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hs1_i2s_sck_active &hs1_i2s_data0_active
&hs1_i2s_data1_active>;
pinctrl-1 = <&hs1_i2s_sck_sleep &hs1_i2s_data0_sleep
&hs1_i2s_data1_sleep>;
clocks = <&clock_gcc GCC_SDR_SEC_MI2S_CLK>;
clock-names = "sec_mi2s_clk";
bit-clock-hz = <12288000>;
data-buffer-ms = <10>;
bit-depth = <32>;
spkr-channel-count = <2>;
mic-channel-count = <2>;
pcm-rate = <2>;
pcm-sync-src = <0>;
aux-mode = <0>;
rpcm-width = <1>;
tpcm-width = <1>;
enable-tdm = <1>;
tdm-rate = <32>;
tdm-rpcm-width = <16>;
tdm-tpcm-width = <16>;
tdm-sync-delay = <2>;
tdm-inv-sync = <0>;
pcm-lane-config = <1>;
};
};

7
bindings/ufs/ufs-qcom.txt
View File

@@ -12,6 +12,8 @@ Required properties:
"qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy,
"qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy
present on MSM8996 chipset.
"qcom,ufs-phy-qmp-v4-direwolf" for ufs phy
present on SA8295 Makena chipset.
"qcom,ufs-phy-qrbtc-sdm845" for phy support
for pre-sil emulation.
"qcom,ufs-phy-qmp-v4-kalama" for ufs phy
@@ -36,6 +38,8 @@ Optional properties:
- vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply
- vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply
- resets : specifies the PHY reset in the UFS controller
- qcom,prime-mask : the cpu mask of prime core.
- qcom,silver-mask: the cpu mask of silver core.
Example:
@@ -66,4 +70,7 @@ Example:
...
phys = <&ufsphy1>;
phy-names = "ufsphy";
...
qcom,prime-mask = <0x80>;
qcom,silver-mask = <0x0f>;
};