ARM: dts: msm: Add initial device tree for Anorak IDP platform

Add device tree support for Anorak IDP platform.

Change-Id: I78b34ac8dc8dde0dd743e25cd5ced13e110fd13e

bindings/arm/msm/msm.txt

@@ -101,6 +101,9 @@ SoCs:
 - PINEAPPLE
   compatible = "qcom,pineapple", "qcom,pineapplep"
 
+- ANORAK
+  compatible = "qcom,anorak"
+
 - NIOBE
   compatible = "qcom,niobe", "qcom,niobep"
 
@@ -371,6 +374,7 @@ compatible = "qcom,monaco_auto-adas-adp-star"
 compatible = "qcom,monaco_auto-ivi"
 compatible = "qcom,monaco_auto-ivi-adp-air"
 compatible = "qcom,monaco_auto-ivi-adp-star"
+compatible = "qcom,anorak-idp"
 compatible = "qcom,pitti-rumi"
 compatible = "qcom,pitti-idp"
 compatible = "qcom,pitti-atp"

qcom/Makefile

@@ -132,6 +132,17 @@ niobe-dtb-$(CONFIG_ARCH_NIOBE) += \
 niobe-overlays-dtb-$(CONFIG_ARCH_NIOBE) += $(NIOBE_BOARDS) $(NOAPQ_NIOBE_BOARDS) $(NIOBE_BASE_DTB) $(NIOBE_APQ_BASE_DTB)
 dtb-y += $(niobe-dtb-y)
 
+ANORAK_BASE_DTB += anorak.dtb
+
+ANORAK_BOARDS += \
+		anorak-idp-overlay.dtbo
+
+anorak-dtb-$(CONFIG_ARCH_ANORAK) += \
+	$(call add-overlays, $(ANORAK_BOARDS) ,$(ANORAK_BASE_DTB))
+
+anorak-overlays-dtb-$(CONFIG_ARCH_ANORAK) += $(ANORAK_BOARDS) ${ANORAK_BASE_DTB)
+dtb-y += $(anorak-dtb-y)
+
 BLAIR_BASE_DTB += blair.dtb
 BLAIR_APQ_BASE_DTB += blairp.dtb
 

qcom/anorak-idp-overlay.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "anorak-idp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,msm-id = <549 0x10000>,<649 0x10000>;
+	qcom,board-id = <0x10022 0x0>;
+};

qcom/anorak-idp.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorak.dtsi"
+#include "anorak-idp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,board-id = <0x10022 0x0>;
+};

qcom/anorak-idp.dtsi

@@ -0,0 +1,2 @@
+&soc {
+};

qcom/anorak.dts

@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "anorak.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak SoC";
+	compatible = "qcom,anorak";
+	qcom,board-id = <0 0>;
+};

qcom/anorak.dtsi

@@ -0,0 +1,299 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak";
+	compatible = "qcom,anorak";
+	qcom,msm-id = <549 0x10000>;
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+	memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+
+	chosen: chosen { };
+
+	aliases: aliases { };
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x0>;
+			cpu-idle-states = <&GOLD_CPU_OFF &GOLD_CPU_RAIL_OFF>;
+			power-domains = <&CPU_PD0>;
+			power-domain-names = "psci";
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			#cooling-cells = <2>;
+			//qcom,freq-domain = <&cpufreq_hw 0 2>;
+			L2_0: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+
+				L3_0: l3-cache {
+					compatible = "arm,arch-cache";
+					cache-level = <3>;
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			cpu-idle-states = <&GOLD_CPU_OFF &GOLD_CPU_RAIL_OFF>;
+			power-domains = <&CPU_PD1>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_1>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			#cooling-cells = <2>;
+			//qcom,freq-domain = <&cpufreq_hw 0 2>;
+			L2_1: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			cpu-idle-states = <&GOLD_PLUS_CPU_OFF &GOLD_PLUS_CPU_RAIL_OFF>;
+			power-domains = <&CPU_PD2>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_2>;
+			capacity-dmips-mhz = <1075>;
+			dynamic-power-coefficient = <109>;
+			#cooling-cells = <2>;
+			///qcom,freq-domain = <&cpufreq_hw 1 4>;
+			L2_2: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			cpu-idle-states = <&GOLD_PLUS_CPU_OFF &GOLD_PLUS_CPU_RAIL_OFF>;
+			power-domains = <&CPU_PD3>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_3>;
+			capacity-dmips-mhz = <1075>;
+			dynamic-power-coefficient = <109>;
+			#cooling-cells = <2>;
+			//qcom,freq-domain = <&cpufreq_hw 1 4>;
+			L2_3: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+
+		};
+
+		CPU4: cpu@400 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+			cpu-idle-states = <&GOLD_PLUS_CPU_OFF &GOLD_PLUS_CPU_RAIL_OFF>;
+			power-domains = <&CPU_PD4>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_4>;
+			capacity-dmips-mhz = <1075>;
+			dynamic-power-coefficient = <109>;
+			#cooling-cells = <2>;
+			//qcom,freq-domain = <&cpufreq_hw 1 4>;
+			L2_4: l2-cache {
+				compatible = "arm,arch-cache";
+				cache-level = <2>;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU5: cpu@500 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+			cpu-idle-states = <&GOLD_PLUS_CPU_OFF &GOLD_PLUS_CPU_RAIL_OFF>;
+			power-domains = <&CPU_PD5>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_5>;
+			capacity-dmips-mhz = <1075>;
+			dynamic-power-coefficient = <109>;
+			#cooling-cells = <2>;
+			//qcom,freq-domain = <&cpufreq_hw 1 4>;
+			L2_5: l2-cache {
+				compatible = "arm,arch-cache";
+				cache-level = <2>;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU2>;
+				};
+
+				core1 {
+					cpu = <&CPU3>;
+				};
+
+				core2 {
+					cpu = <&CPU4>;
+				};
+
+				core3 {
+					cpu = <&CPU5>;
+				};
+			};
+		};
+	};
+
+	idle-states {
+		GOLD_CPU_OFF: gold-c3 {  /* C3 */
+			compatible = "arm,idle-state";
+			idle-state-name = "pc";
+			entry-latency-us = <400>;
+			exit-latency-us = <1400>;
+			min-residency-us = <2207>;
+			arm,psci-suspend-param = <0x40000003>;
+			local-timer-stop;
+		};
+
+		GOLD_CPU_RAIL_OFF: gold-c4 {  /* C4 */
+			compatible = "arm,idle-state";
+			idle-state-name = "rail-pc";
+			entry-latency-us = <600>;
+			exit-latency-us = <1300>;
+			min-residency-us = <8136>;
+			arm,psci-suspend-param = <0x40000004>;
+			local-timer-stop;
+		};
+
+		GOLD_PLUS_CPU_OFF: gold-plus-c3 {  /* C3 */
+			compatible = "arm,idle-state";
+			idle-state-name = "pc";
+			entry-latency-us = <300>;
+			exit-latency-us = <1450>;
+			min-residency-us = <3230>;
+			arm,psci-suspend-param = <0x40000003>;
+			local-timer-stop;
+		};
+
+		GOLD_PLUS_CPU_RAIL_OFF: gold-plus-c4 {  /* C4 */
+			compatible = "arm,idle-state";
+			idle-state-name = "rail-pc";
+			entry-latency-us = <500>;
+			exit-latency-us = <1350>;
+			min-residency-us = <7480>;
+			arm,psci-suspend-param = <0x40000004>;
+			local-timer-stop;
+		};
+
+		CLUSTER_PWR_DN: cluster-d4 { /* D4 */
+			compatible = "domain-idle-state";
+			idle-state-name = "l3-off";
+			entry-latency-us = <1050>;
+			exit-latency-us = <2500>;
+			min-residency-us = <9309>;
+			arm,psci-suspend-param = <0x41000044>;
+		};
+
+		APSS_OFF: cluster-e3 { /* E3 */
+			compatible = "domain-idle-state";
+			idle-state-name = "llcc-off";
+			entry-latency-us = <2700>;
+			exit-latency-us = <3500>;
+			min-residency-us = <13959>;
+			arm,psci-suspend-param = <0x4100c344>;
+		};
+	};
+
+	soc: soc { };
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0 0 0 0xffffffff>;
+	compatible = "simple-bus";
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		CPU_PD0: cpu-pd0 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD1: cpu-pd1 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD2: cpu-pd2 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD3: cpu-pd3 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD4: cpu-pd4 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD5: cpu-pd5 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CLUSTER_PD: cluster-pd {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&CLUSTER_PWR_DN &APSS_OFF>;
+		};
+	};
+
+	intc: interrupt-controller@17200000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		#redistributor-regions = <1>;
+		redistributor-stride = <0x0 0x20000>;
+		reg = <0x17200000 0x10000>,	/* GICD */
+		      <0x17260000 0x100000>;	/* GICR * 8 */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+	};
+};

qcom/platform_map.bzl

@@ -181,6 +181,11 @@ _platform_map = {
         ],
         "binary_compatible_with": ["cliffs", "volcano"],
     },
+    "anorak": {
+        "dtb_list": [
+            {"name": "anorak.dtb"},
+        ],
+    },
     "niobe": {
         "dtb_list": [
             {"name": "niobe.dtb"},