#include <dt-bindings/clock/qcom,gcc-sm6150.h>
#include <dt-bindings/clock/qcom,scc-sm6150.h>
#include "quin-vm-common.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. SA6155P Guest Virtual Machine";
	qcom,msm-name = "SA6155P";
	qcom,msm-id = <377 0x10000>;

	aliases {
		hsuart0 = &qupv3_se7_4uart;
		sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			capacity-dmips-mhz = <1024>;

		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x1>;
			capacity-dmips-mhz = <1024>;
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x2>;
			capacity-dmips-mhz = <347>;
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x3>;
			capacity-dmips-mhz = <347>;
		};

		CPU4: cpu@4 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x4>;
			capacity-dmips-mhz = <347>;
		};

		CPU5: cpu@5 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x5>;
			capacity-dmips-mhz = <347>;
		};

		CPU6: cpu@6 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x6>;
			capacity-dmips-mhz = <347>;
		};

		CPU7: cpu@7 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x7>;
			capacity-dmips-mhz = <347>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU2>;
				};

				core1 {
					cpu = <&CPU3>;
				};

				core2 {
					cpu = <&CPU4>;
				};

				core3 {
					cpu = <&CPU5>;
				};

				core4 {
					cpu = <&CPU6>;
				};

				core5 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	firmware: firmware {
			scm {
			compatible = "qcom,scm";
		};
	};
};


&soc {
	VDD_CX_LEVEL: VDD_MX_LEVEL: S2A_LEVEL:
		pm6155_1_s2_level: regulator-pm6155-1-s2-level {
		compatible = "qcom,stub-regulator";
		regulator-name = "pm6155_1_s2_level";
		regulator-min-microvolt
			= <RPMH_REGULATOR_LEVEL_RETENTION>;
		regulator-max-microvolt
			= <RPMH_REGULATOR_LEVEL_MAX>;
	};

	/* PWR_CTR1_VDD_1P8 supply */
	vreg_conn_1p8: vreg_conn_1p8 {
		compatible = "regulator-fixed";
		regulator-name = "vreg_conn_1p8";
		startup-delay-us = <4000>;
		enable-active-high;
		gpio = <&pm6155_1_gpios 1 0>;
	};

	/* PWR_CTR2_VDD_PA supply */
	vreg_conn_pa: vreg_conn_pa {
		compatible = "regulator-fixed";
		regulator-name = "vreg_conn_pa";
		startup-delay-us = <4000>;
		enable-active-high;
		gpio = <&pm6155_1_gpios 6 0>;
	};

	apps_smmu: apps-smmu@15000000 {
		compatible = "qcom,qsmmu-v500";
		reg = <0x15000000 0x80000>,
			<0x150c2000 0x20>;
		reg-names = "base", "tcu-base";
		#iommu-cells = <2>;
		qcom,skip-init;
		qcom,use-3-lvl-tables;
		qcom,handoff-smrs = <0xffff 0x0>;
		qcom,multi-match-handoff-smr;
		qcom,disable-atos;
		#global-interrupts = <1>;
		#size-cells = <1>;
		#address-cells = <1>;
		ranges;
		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
	};

	dma_dev@0x0 {
		compatible = "qcom,iommu-dma";
		memory-region = <&system_cma>;
	};

	qtee_shmbridge {
		compatible = "qcom,tee-shared-memory-bridge";
		/*Boolean property to disable shmbridge*/
		qcom,disable-shmbridge-support;
	};

	qcom_seecom: qseecom@86d00000 {
		compatible = "qcom,qseecom";
		reg = <0x86d00000 0xe00000>;
		reg-names = "secapp-region";
		memory-region = <&qseecom_mem>;
		qcom,hlos-num-ce-hw-instances = <1>;
		qcom,hlos-ce-hw-instance = <0>;
		qcom,qsee-ce-hw-instance = <0>;
		qcom,disk-encrypt-pipe-pair = <2>;
		qcom,no-clock-support;
		qcom,qsee-reentrancy-support = <2>;
	};

	qcom_rng: qrng@793000 {
		compatible = "qcom,msm-rng";
		reg = <0x793000 0x1000>;
		qcom,no-qrng-config;
		qcom,no-clock-support;
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,sm6150-pdc", "qcom,pdc";
		reg = <0xb220000 0x30000>;
		qcom,pdc-ranges = <6 486 1>, <8 488 4>, <94 609 1>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};

	sdhc_2: sdhci@8804000 {
		compatible = "qcom,sdhci-msm-v5";
		reg = <0x8804000 0x1000>;
		reg-names = "hc";

		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
			<&gcc GCC_SDCC2_APPS_CLK>;
		clock-names = "iface", "core";

		bus-width = <4>;
		/*TBD */
		no-sdio;
		no-mmc;
		qcom,restore-after-cx-collapse;

		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
		qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;

		qcom,devfreq,freq-table = <50000000 201500000>;

		vdd-supply = <&pm6155_1_l10>;
		qcom,vdd-voltage-level = <2950000 2950000>;
		qcom,vdd-current-level = <0 800000>;
		vdd-io-supply = <&pm6155_1_l2>;
		qcom,vdd-io-voltage-level = <1800000 3100000>;
		qcom,vdd-io-current-level = <0 22000>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&sdc2_on>;
		pinctrl-1 = <&sdc2_off>;

		cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
		status = "disabled";

	};

	msm_gpu_hyp: qcom,hgsl {
		compatible = "qcom,hgsl";

		/* 6155 have no Doorbell, only keep ifence */
		db-off = <1>;
	};

	bluetooth: bt-qca-auto-converged {
		compatible = "qcom,qca-auto-converged";
		pinctrl-names = "default";
		pinctrl-0 = <&bt_en_active>;
		/* BT_EN */
		qcom,bt-reset-gpio = <&tlmm 85 0>;
		/* PWR_CTR1_VDD_PA */
		qcom,bt-vdd-ctrl1-supply = <&vreg_conn_pa>;
		/* PWR_CTR2_VDD_1P8 */
		qcom,bt-vdd-ctrl2-supply = <&vreg_conn_1p8>;
		qcom,bt-vdd-rfa1-supply = <&pm6155_1_s6>;
		qcom,bt-vdd-rfa2-supply = <&pm6155_1_s5>;
		qcom,bt-vdd-rfa3-supply = <&pm6155_1_l15>;

		/* <vol_min, vol_max, load_curr, is_retention_supp> */
		qcom,bt-vdd-rfa1-config = <1350000 1350000 0 0>;
		qcom,bt-vdd-rfa2-config = <2040000 2040000 0 0>;
		qcom,bt-vdd-rfa3-config = <1904000 1904000 0 0>;
	};
};

&regulator {
	usb30_prim_gdsc: usb30_prim_gdsc {
		regulator-name = "usb30_prim_gdsc";
	};

	usb20_sec_gdsc: usb20_sec_gdsc {
		regulator-name = "usb20_sec_gdsc";
	};

	pcie_0_gdsc: pcie_0_gdsc {
		regulator-name = "pcie_0_gdsc";
	};

	L2A: pm6155_1_l2: regulator-pm6155-1-l2 {
		regulator-name = "ldoa2";
		regulator-min-microvolt = <1650000>;
		regulator-max-microvolt = <3100000>;
	};

	L5A: pm6155_1_l5: regulator-pm6155-1-l5 {
		regulator-name = "ldoa5";
		regulator-min-microvolt = <875000>;
		regulator-max-microvolt = <975000>;
	};

	L10A: pm6155_1_l10: regulator-pm6155-1-l10 {
		regulator-name = "ldoa10";
		regulator-min-microvolt = <2950000>;
		regulator-max-microvolt = <3312000>;
	};

	L12A: pm6155_1_l12: regulator-pm6155-1-l12 {
		regulator-name = "ldoa12";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1890000>;
	};

	L13A: pm6155_1_l13: regulator-pm6155-1-l13 {
		regulator-name = "ldoa13";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3230000>;
	};

	S6A: pm6155_1_s6: regulator-pm6155-1-s6 {
		regulator-name = "smpa6";
		regulator-min-microvolt = <947000>;
		regulator-max-microvolt = <1404000>;
	};

	S5A: pm6155_1_s5: regulator-pm6155-1-s5 {
		regulator-name = "smpa5";
		regulator-min-microvolt = <1896000>;
		regulator-max-microvolt = <2040000>;
	};

	L15A: pm6155_1_l15: regulator-pm6155-1-l15 {
		regulator-name = "ldoa15";
		regulator-min-microvolt = <1904000>;
		regulator-max-microvolt = <1904000>;
	};
};

#include "sm6150-pinctrl.dtsi"
#include "sa6155p-vm-usb.dtsi"
#include "sa6155p-vm-pcie.dtsi"
#include "sa6155p-vm-qupv3.dtsi"
#include "pm6155-vm.dtsi"
#include "sm6150-slpi-pinctrl.dtsi"
#include "sa6155p-vm-ssc-qupv3.dtsi"

&tlmm {
	qcom,gpio-irq-map = <99 94>;
};

&qupv3_0 {
	qcom,iommu-dma = "bypass";
};

&qupv3_1 {
	qcom,iommu-dma = "bypass";
};

&qupv3_2 {
	qcom,iommu-dma = "bypass";
	status = "disabled";
};

&scc {
	vdd_cx-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&slpi_tlmm {
	status = "ok";
};

&hab {
	/delete-node/ mmidgrp1400;
	/delete-node/ mmidgrp1500;
};

&pcie0_msi {
	status = "ok";
};

&pcie0 {
	status = "ok";
};

&qupv3_se7_4uart {
	status = "ok";
};