mirror of
https://github.com/oplus-giulia-dev/android_kernel_oneplus_sm8650-devicetrees
synced 2025-11-04 14:45:59 +08:00
c112925641
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at 3da6de37c76b ("Snap for
8113462 from e98653b1be1521039c56a905ccc4860bac47118c to
android-mainline-keystone-qcom-release").
Change-Id: I05e4ecc6512d1e8b085f4495b16eb559a0a94de0
64 lines
1.3 KiB
YAML
64 lines
1.3 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Altera mSGDMA IP core
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maintainers:
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- Olivier Dautricourt <olivier.dautricourt@orolia.com>
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description: |
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Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)
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intellectual property (IP)
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allOf:
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- $ref: "dma-controller.yaml#"
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properties:
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compatible:
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const: altr,socfpga-msgdma
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reg:
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items:
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- description: Control and Status Register Slave Port
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- description: Descriptor Slave Port
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- description: Response Slave Port (Optional)
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minItems: 2
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reg-names:
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items:
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- const: csr
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- const: desc
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- const: resp
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minItems: 2
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interrupts:
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maxItems: 1
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"#dma-cells":
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const: 1
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description:
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The cell identifies the channel id (must be 0)
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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msgdma_controller: dma-controller@ff200b00 {
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compatible = "altr,socfpga-msgdma";
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reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;
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reg-names = "csr", "desc", "resp";
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interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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};
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