mirror of
https://github.com/oplus-giulia-dev/android_kernel_oneplus_sm8650-devicetrees
synced 2025-11-04 06:44:04 +08:00
405 lines
13 KiB
Plaintext
405 lines
13 KiB
Plaintext
/ {
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aliases {
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spi1 = &spi_1;
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spi2 = &spi_2;
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spi3 = &spi_3;
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spi4 = &spi_4;
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spi5 = &spi_5;
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spi6 = &spi_6;
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i2c1 = &i2c_1;
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i2c2 = &i2c_2;
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i2c3 = &i2c_3;
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i2c4 = &i2c_4;
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i2c5 = &i2c_5;
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i2c6 = &i2c_6;
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};
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};
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&soc {
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dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */
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#dma-cells = <4>;
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compatible = "qcom,sps-dma";
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reg = <0x7884000 0x2b000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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qcom,summing-threshold = <0x10>;
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};
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blsp1_uart5: serial@78b3000 { /* BLSP1 UART5 */
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compatible = "qcom,msm-uartdm-v1.4",
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"qcom,msm-uartdm";
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reg = <0x78b3000 0x200>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core", "iface";
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clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp1_uart5_console_tx5_active>,<&blsp1_uart5_console_rx5_active>;
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pinctrl-1 = <&blsp1_uart5_console_tx5_sleep>,<&blsp1_uart5_console_rx5_sleep>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pcnoc MASTER_BLSP_1 &pcnoc SLAVE_BLSP_1>;
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status = "disabled";
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};
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blsp1_uart3: uart@78b1000 {
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compatible = "qcom,msm-hsuart-v14";
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reg = <0x78b1000 0x200>,
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<0x7884000 0x2b000>;
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reg-names = "core_mem", "bam_mem";
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interrupts-extended = <&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<&intc GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 1 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <0>;
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qcom,inject-rx-on-wakeup;
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qcom,rx-char-to-inject = <0xFD>;
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qcom,bam-tx-ep-pipe-index = <4>;
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qcom,bam-rx-ep-pipe-index = <5>;
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qcom,master-id = <86>;
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clock-names = "core_clk", "iface_clk";
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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pinctrl-names = "sleep", "default", "shutdown", "active";
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pinctrl-0 = <&blsp1_uart3_hs_tx_sleep>,<&blsp1_uart3_hs_rx_sleep>,
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<&blsp1_uart3_hs_cts_sleep>,<&blsp1_uart3_hs_rfr_sleep>;
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pinctrl-1 = <&blsp1_uart3_hs_tx_sleep>,<&blsp1_uart3_hs_rx_sleep>,
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<&blsp1_uart3_hs_cts_sleep>,<&blsp1_uart3_hs_rfr_sleep>;
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pinctrl-2 = <&blsp1_uart3_hs_tx_sleep>,<&blsp1_uart3_hs_rx_sleep>,
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<&blsp1_uart3_hs_cts_sleep>,<&blsp1_uart3_hs_rfr_sleep>;
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pinctrl-3 = <&blsp1_uart3_hs_tx_active>,<&blsp1_uart3_hs_rx_active>,
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<&blsp1_uart3_hs_cts_active>,<&blsp1_uart3_hs_rfr_active>;
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interconnect-names ="blsp-ddr";
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interconnects = <&pcnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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status = "disabled";
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};
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i2c_1: i2c@78B5000 { /* BLSP1 QUP1 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78B5000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 12 64 0x20000020 0x20>,
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<&dma_blsp1 13 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <86>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_1_sda1_active &i2c_1_scl1_active>;
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pinctrl-1 = <&i2c_1_sda1_sleep &i2c_1_scl1_sleep>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pcnoc MASTER_BLSP_1 &pcnoc SLAVE_BLSP_1>;
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status = "disabled";
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};
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i2c_2: i2c@78B6000 { /* BLSP1 QUP2 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78B6000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 14 64 0x20000020 0x20>,
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<&dma_blsp1 15 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <86>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_2_sda2_active &i2c_2_scl2_active>;
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pinctrl-1 = <&i2c_2_sda2_sleep &i2c_2_scl2_sleep>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pcnoc MASTER_BLSP_1 &pcnoc SLAVE_BLSP_1>;
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status = "disabled";
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};
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i2c_3: i2c@78B7000 { /* BLSP1 QUP3 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78B7000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 16 64 0x20000020 0x20>,
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<&dma_blsp1 17 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <86>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_3_sda3_active &i2c_3_scl3_active>;
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pinctrl-1 = <&i2c_3_sda3_sleep &i2c_3_scl3_sleep>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pcnoc MASTER_BLSP_1 &pcnoc SLAVE_BLSP_1>;
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status = "disabled";
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};
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i2c_4: i2c@78B8000 { /* BLSP1 QUP4 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78B8000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 18 64 0x20000020 0x20>,
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<&dma_blsp1 19 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <86>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_4_sda4_active &i2c_4_scl4_active>;
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pinctrl-1 = <&i2c_4_sda4_sleep &i2c_4_scl4_sleep>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pcnoc MASTER_BLSP_1 &pcnoc SLAVE_BLSP_1>;
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status = "disabled";
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};
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i2c_5: i2c@78B9000 { /* BLSP1 QUP5 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78B9000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 20 64 0x20000020 0x20>,
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<&dma_blsp1 21 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <86>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_5_sda5_active &i2c_5_scl5_active>;
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pinctrl-1 = <&i2c_5_sda5_sleep &i2c_5_scl5_sleep>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pcnoc MASTER_BLSP_1 &pcnoc SLAVE_BLSP_1>;
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status = "disabled";
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};
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i2c_6: i2c@78BA000 { /* BLSP1 QUP6 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78BA000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 22 64 0x20000020 0x20>,
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<&dma_blsp1 23 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <86>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_6_sda6_active &i2c_6_scl6_active>;
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pinctrl-1 = <&i2c_6_sda6_sleep &i2c_6_scl6_sleep>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pcnoc MASTER_BLSP_1 &pcnoc SLAVE_BLSP_1>;
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status = "disabled";
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};
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spi_1: spi@78B5000 { /* BLSP1 QUP1 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x78B5000 0x600>,
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<0x7884000 0x2b000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <12>;
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qcom,bam-producer-pipe-index = <13>;
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qcom,master-id = <86>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_1_mosi1_default &spi_1_miso1_default
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&spi_1_cs1_active &spi_1_clk1_default>;
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pinctrl-1 = <&spi_1_mosi1_sleep &spi_1_miso1_sleep
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&spi_1_cs1_sleep &spi_1_clk1_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pcnoc MASTER_BLSP_1 &pcnoc SLAVE_BLSP_1>;
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status = "disabled";
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};
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spi_2: spi@78B6000 { /* BLSP1 QUP2 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x78B6000 0x600>,
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<0x7884000 0x2b000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <14>;
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qcom,bam-producer-pipe-index = <15>;
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qcom,master-id = <86>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_2_mosi2_default &spi_2_miso2_default
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&spi_2_cs2_active &spi_2_clk2_default>;
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pinctrl-1 = <&spi_2_mosi2_sleep &spi_2_miso2_sleep
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&spi_2_cs2_sleep &spi_2_clk2_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pcnoc MASTER_BLSP_1 &pcnoc SLAVE_BLSP_1>;
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status = "disabled";
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};
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spi_3: spi@78B7000 { /* BLSP1 QUP3 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x78B7000 0x600>,
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<0x7884000 0x2b000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <16>;
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qcom,bam-producer-pipe-index = <17>;
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qcom,master-id = <86>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_3_mosi3_default &spi_3_miso3_default
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&spi_3_cs3_active &spi_3_clk3_default>;
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pinctrl-1 = <&spi_3_mosi3_sleep &spi_3_miso3_sleep
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&spi_3_cs3_sleep &spi_3_clk3_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pcnoc MASTER_BLSP_1 &pcnoc SLAVE_BLSP_1>;
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status = "disabled";
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};
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spi_4: spi@78B8000 { /* BLSP1 QUP4 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x78B8000 0x600>,
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<0x7884000 0x2b000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <18>;
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qcom,bam-producer-pipe-index = <19>;
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qcom,master-id = <86>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_4_mosi4_default &spi_4_miso4_default
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&spi_4_cs4_active &spi_4_clk4_default>;
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pinctrl-1 = <&spi_4_mosi4_sleep &spi_4_miso4_sleep
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&spi_4_cs4_sleep &spi_4_clk4_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pcnoc MASTER_BLSP_1 &pcnoc SLAVE_BLSP_1>;
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status = "disabled";
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};
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spi_5: spi@78B9000 { /* BLSP1 QUP5 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x78B9000 0x600>,
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<0x7884000 0x2b000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <20>;
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qcom,bam-producer-pipe-index = <21>;
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qcom,master-id = <86>;
|
|
qcom,use-pinctrl;
|
|
pinctrl-names = "spi_default", "spi_sleep";
|
|
pinctrl-0 = <&spi_5_mosi5_default &spi_5_miso5_default
|
|
&spi_5_cs5_active &spi_5_clk5_default>;
|
|
pinctrl-1 = <&spi_5_mosi5_sleep &spi_5_miso5_sleep
|
|
&spi_5_cs5_sleep &spi_5_clk5_sleep>;
|
|
clock-names = "iface_clk", "core_clk";
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>;
|
|
interconnect-names = "blsp-ddr";
|
|
interconnects = <&pcnoc MASTER_BLSP_1 &pcnoc SLAVE_BLSP_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_6: spi@78BA000 { /* BLSP1 QUP6 */
|
|
compatible = "qcom,spi-qup-v2";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg-names = "spi_physical", "spi_bam_physical";
|
|
reg = <0x78BA000 0x600>,
|
|
<0x7884000 0x2b000>;
|
|
interrupt-names = "spi_irq", "spi_bam_irq";
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,use-bam;
|
|
qcom,ver-reg-exists;
|
|
qcom,bam-consumer-pipe-index = <22>;
|
|
qcom,bam-producer-pipe-index = <23>;
|
|
qcom,master-id = <86>;
|
|
qcom,use-pinctrl;
|
|
pinctrl-names = "spi_default", "spi_sleep";
|
|
pinctrl-0 = <&spi_6_mosi6_default &spi_6_miso6_default
|
|
&spi_6_cs6_active &spi_6_clk6_default>;
|
|
pinctrl-1 = <&spi_6_mosi6_sleep &spi_6_miso6_sleep
|
|
&spi_6_cs6_sleep &spi_6_clk6_sleep>;
|
|
clock-names = "iface_clk", "core_clk";
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
|
<&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>;
|
|
interconnect-names = "blsp-ddr";
|
|
interconnects = <&pcnoc MASTER_BLSP_1 &pcnoc SLAVE_BLSP_1>;
|
|
status = "disabled";
|
|
};
|
|
};
|