mirror of
https://github.com/oplus-giulia-dev/android_kernel_oneplus_sm8650-devicetrees
synced 2025-11-04 06:44:04 +08:00
1010 lines
26 KiB
Plaintext
1010 lines
26 KiB
Plaintext
#include <dt-bindings/clock/qcom,gcc-niobe.h>
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#include <dt-bindings/gpio/gpio.h>
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&soc {
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pcie0: qcom,pcie@1c00000 {
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compatible = "qcom,pci-msm";
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reg = <0x1c00000 0x3000>,
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<0x1c06000 0x2000>,
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<0x60000000 0xf1d>,
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<0x60000f20 0xa8>,
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<0x60001000 0x1000>,
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<0x60100000 0x100000>,
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<0x1c03000 0x1000>,
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<0x01D07000 0x4000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "mhi", "pcie_sm";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0x60300000 0x0 0x1d00000>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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msi-parent = <&pcie0_msi>;
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perst-gpio = <&tlmm 0 GPIO_ACTIVE_HIGH>;
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wake-gpio = <&tlmm 1 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_perst_default
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&pcie0_clkreq_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_perst_default
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&pcie0_clkreq_sleep
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&pcie0_wake_default>;
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gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000>;
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interconnect-names = "icc_path";
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interconnects = <&pcie_anoc MASTER_PCIE_0_PCIE_CRM_HW_0
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&mc_virt SLAVE_EBI1_PCIE_CRM_HW_0>;
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clocks = <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
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clock-names = "gcc_cnoc_pcie_sf_axi_clk";
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clock-frequency = <0>;
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clock-suppressible = <1>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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dma-coherent;
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qcom,smmu-sid-base = <0x1480>;
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iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
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<0x100 &apps_smmu 0x1481 0x1>;
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qcom,boot-option = <0x1>;
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qcom,aux-clk-freq = <20>; /* 19.2 MHz */
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qcom,drv-supported;
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qcom,drv-l1ss-timeout-us = <5000>;
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qcom,l1-2-th-scale = <2>;
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qcom,l1-2-th-value = <150>;
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qcom,slv-addr-space-size = <0x4000000>;
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qcom,ep-latency = <10>;
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qcom,num-parf-testbus-sel = <0xb9>;
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qcom,pcie-clkreq-offset = <0x2c48>;
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qcom,pcie-phy-ver = <111>;
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qcom,phy-status-offset = <0x214>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x240>;
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qcom,phy-sequence = <0x0240 0x03 0x0
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0x00c0 0x01 0x0
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0x00cc 0x62 0x0
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0x00d0 0x02 0x0
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0x0060 0xf8 0x0
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0x0064 0x01 0x0
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0x0000 0x93 0x0
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0x0004 0x01 0x0
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0x00e0 0x90 0x0
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0x00e4 0x82 0x0
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0x00f4 0x07 0x0
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0x0070 0x02 0x0
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0x0010 0x02 0x0
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0x0074 0x16 0x0
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0x0014 0x16 0x0
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0x0078 0x36 0x0
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0x0018 0x36 0x0
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0x0110 0x08 0x0
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0x00bc 0x0a 0x0
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0x0120 0x42 0x0
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0x0080 0x04 0x0
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0x0084 0x0d 0x0
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0x0020 0x0a 0x0
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0x0024 0x1a 0x0
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0x0088 0x41 0x0
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0x0028 0x34 0x0
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0x0090 0xab 0x0
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0x0094 0xaa 0x0
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0x0098 0x01 0x0
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0x0030 0x55 0x0
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0x0034 0x55 0x0
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0x0038 0x01 0x0
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0x0140 0x14 0x0
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0x0164 0x34 0x0
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0x003c 0x01 0x0
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0x001c 0x04 0x0
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0x0174 0x16 0x0
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0x01bc 0x0f 0x0
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0x0170 0xa0 0x0
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0x11a4 0x38 0x0
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0x10dc 0x11 0x0
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0x1160 0xbf 0x0
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0x1164 0xbf 0x0
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0x1168 0xb7 0x0
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0x116c 0xef 0x0
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0x115c 0x3f 0x0
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0x1174 0x5c 0x0
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0x1178 0x9c 0x0
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0x117c 0x1a 0x0
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0x1180 0x8f 0x0
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0x1170 0xdc 0x0
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0x1188 0x94 0x0
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0x118c 0x5b 0x0
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0x1190 0x1a 0x0
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0x1194 0x89 0x0
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0x10cc 0x00 0x0
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0x1008 0x09 0x0
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0x1014 0x05 0x0
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0x104c 0x08 0x0
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0x1050 0x08 0x0
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0x10d8 0x0f 0x0
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0x1118 0x1c 0x0
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0x10f8 0x07 0x0
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0x11f8 0x08 0x0
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0x1600 0x00 0x0
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0x0e84 0x15 0x0
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0x0e90 0x3f 0x0
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0x0ee4 0x02 0x0
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0x0e40 0x06 0x0
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0x0e3c 0x18 0x0
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0x19a4 0x38 0x0
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0x18dc 0x11 0x0
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0x1960 0xbf 0x0
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0x1964 0xbf 0x0
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0x1968 0xb7 0x0
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0x196c 0xef 0x0
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0x195c 0x3f 0x0
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0x1974 0x5c 0x0
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0x1978 0x9c 0x0
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0x197c 0x1a 0x0
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0x1980 0x8f 0x0
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0x1970 0xdc 0x0
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0x1988 0x94 0x0
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0x198c 0x5b 0x0
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0x1990 0x1a 0x0
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0x1994 0x89 0x0
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0x18cc 0x00 0x0
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0x1808 0x09 0x0
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0x1814 0x05 0x0
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0x184c 0x08 0x0
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0x1850 0x08 0x0
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0x18d8 0x0f 0x0
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0x1918 0x1c 0x0
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0x18f8 0x07 0x0
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0x19f8 0x08 0x0
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0x1684 0x15 0x0
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0x1690 0x3f 0x0
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0x16e4 0x02 0x0
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0x1640 0x06 0x0
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0x163c 0x18 0x0
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0x02dc 0x05 0x0
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0x0388 0x77 0x0
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0x0398 0x0b 0x0
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0x06a4 0x1e 0x0
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0x06f4 0x27 0x0
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0x03e0 0x0f 0x0
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0x060c 0x1d 0x0
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0x0614 0x07 0x0
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0x0620 0xc1 0x0
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0x0694 0x00 0x0
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0x03d0 0x8c 0x0
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0x0368 0x17 0x0
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0x0370 0x2e 0x0
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0x0200 0x00 0x0
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0x0244 0x03 0x0>;
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qcom,parf-debug-reg = <0x01b0 0x0024 0x0028 0x0224 0x0500
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0x04d0 0x04d4 0x03c0 0x0630 0x0230
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0x0000>;
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qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x01f4 0x0730
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0x0734 0x0738 0x073c>;
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qcom,phy-debug-reg = <0x01cc 0x01d0 0x01d4 0x01d8 0x01dc
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0x01e0 0x01e4 0x01f8 0x0ed0 0x16d0
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0x0edc 0x16dc 0x11e0 0x19e0 0x0a00
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0x1200 0x0a04 0x1204 0x0a08 0x1208
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0x0a0c 0x120c 0x0a10 0x1210 0x0a14
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0x1214 0x0a18 0x1218 0x0c20 0x1420
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0x0214 0x0218 0x021c 0x0220 0x0224
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0x0228 0x022c 0x0230 0x0234 0x0238
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0x023c 0x0600 0x0604>;
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qcom,pcie-clkreq-gpio = <126>;
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qcom,pcie-sm-branch-offset = <0x1000>;
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qcom,pcie-sm-start-offset = <0x1090>;
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qcom,pcie-sm-seq = <0x1c018081>, <0x70074002>, <0x50028000>,
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<0x28007003>, <0x80804002>, <0x70021c01>,
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<0x18002802>, <0x70005000>, <0x10004000>,
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<0x80814002>, <0x18001c01>, <0x1c018080>,
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<0x0000100>;
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qcom,pcie-sm-branch-seq = <0x4>, <0x1c>, <0x24>, <0x2c>, <0x0>,
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<0x0>, <0x0>;
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qcom,pcie-sm-debug = <0x1040>, /* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_VAL */
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<0x1048>, /* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_MASK */
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<0x1050>, /* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_VAL */
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<0x1058>, /* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_MASK */
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<0x1060>, /* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_VAL */
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<0x1068>, /* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_MASK */
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<0x1070>, /* PCIE_SMs_SEQ_PWR_CTRL_STATUS */
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<0x1078>, /* PCIE_SMs_SEQ_WAIT_EVENT_STATUS */
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<0x1080>, /* PCIE_SMs_SEQ_BR_EVENT_STATUS */
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<0x1088>, /* PCIE_SMs_SEQ_PC_VAL */
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<0x1090>, /* PCIE_SMs_SEQ_START */
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<0x1094>, /* PCIE_SMs_CLKREQ_GATE */
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<0x1098>, /* PCIE_SMs_CLKREQ_UNGATE */
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<0x109C>; /* PCIE_SMs_CLKREQ_GATE_REQ_STATUS */
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status = "disabled";
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie0_msi: qcom,pcie0_msi@0x17210040 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x17210040 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
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status = "ok";
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};
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pcie1: qcom,pcie@1c10000 {
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compatible = "qcom,pci-msm";
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reg = <0x1c10000 0x3000>,
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<0x1c16000 0x2000>,
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<0x64000000 0xf1d>,
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<0x64000f20 0xa8>,
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<0x64001000 0x1000>,
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<0x64100000 0x100000>,
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<0x1c13000 0x1000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "mhi";
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cell-index = <1>;
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x64200000 0x64200000 0x0 0x100000>,
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<0x02000000 0x0 0x64300000 0x64300000 0x0 0x1d00000>;
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interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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msi-parent = <&pcie1_msi>;
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perst-gpio = <&tlmm 63 GPIO_ACTIVE_HIGH>;
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wake-gpio = <&tlmm 64 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie1_perst_default
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&pcie1_clkreq_default
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&pcie1_wake_default>;
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pinctrl-1 = <&pcie1_perst_default
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&pcie1_clkreq_sleep
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&pcie1_wake_default>;
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gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>;
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gdsc-phy-vdd-supply = <&gcc_pcie_1_phy_gdsc>;
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vreg-1p2-supply = <&L1D>;
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vreg-0p9-supply = <&L10B>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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vreg-mx-supply = <&VDD_MXA_LEVEL>;
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qcom,vreg-1p2-voltage-level = <1200000 1200000 21710>;
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qcom,vreg-0p9-voltage-level = <912000 880000 179340>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000
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/* Gen4 */
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RPMH_REGULATOR_LEVEL_NOM
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RPMH_REGULATOR_LEVEL_NOM
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100000000>;
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interconnect-names = "icc_path";
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interconnects = <&pcie_anoc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
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clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_1_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
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<&tcsrcc TCSR_PCIE_1_CLKREF_EN>,
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<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
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<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
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<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
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<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
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<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
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<&gcc GCC_PCIE_1_PIPE_DIV2_CLK>,
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<&gcc GCC_PCIE_1_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_1_PHY_AUX_CLK_SRC>,
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<&pcie_1_pipe_clk>,
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<&pcie_1_phy_aux_clk>;
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clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
|
|
"pcie_aux_clk", "pcie_cfg_ahb_clk",
|
|
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
|
|
"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
|
|
"pcie_rate_change_clk",
|
|
"gcc_ddrss_pcie_sf_qtb_clk",
|
|
"pcie_aggre_noc_axi_clk",
|
|
"gcc_cnoc_pcie_sf_axi_clk",
|
|
"pcie_cfg_noc_pcie_anoc_ahb_clk",
|
|
"pcie_pipe_clk_mux", "pcie_1_pipe_div2_clk",
|
|
"pcie_phy_aux_clk", "pcie_phy_aux_clk_mux",
|
|
"pcie_pipe_clk_ext_src", "pcie_phy_aux_clk_ext_src";
|
|
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
|
|
<100000000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
|
|
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
|
|
<0>, <0>, <0>, <1>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
|
|
|
|
resets = <&gcc GCC_PCIE_1_BCR>,
|
|
<&gcc GCC_PCIE_1_PHY_BCR>;
|
|
reset-names = "pcie_1_core_reset",
|
|
"pcie_1_phy_reset";
|
|
|
|
dma-coherent;
|
|
qcom,smmu-sid-base = <0x1500>;
|
|
iommu-map = <0x0 &apps_smmu 0x1500 0x1>,
|
|
<0x100 &apps_smmu 0x1501 0x1>;
|
|
|
|
qcom,boot-option = <0x1>;
|
|
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
|
|
qcom,drv-supported;
|
|
qcom,drv-l1ss-timeout-us = <5000>;
|
|
qcom,l1-2-th-scale = <2>;
|
|
qcom,l1-2-th-value = <150>;
|
|
qcom,slv-addr-space-size = <0x4000000>;
|
|
qcom,ep-latency = <10>;
|
|
qcom,num-parf-testbus-sel = <0xb9>;
|
|
|
|
qcom,pcie-clkreq-offset = <0x2c48>;
|
|
|
|
qcom,pcie-phy-ver = <109>;
|
|
qcom,phy-status-offset = <0x1214>;
|
|
qcom,phy-status-bit = <7>;
|
|
qcom,phy-power-down-offset = <0x1240>;
|
|
|
|
qcom,phy-sequence = <0x1240 0x03 0x0
|
|
0x0030 0x1d 0x0
|
|
0x0034 0x03 0x0
|
|
0x0078 0x01 0x0
|
|
0x007c 0x00 0x0
|
|
0x0080 0x51 0x0
|
|
0x00ac 0x34 0x0
|
|
0x0208 0x0c 0x0
|
|
0x020c 0x0a 0x0
|
|
0x0218 0x04 0x0
|
|
0x0220 0x16 0x0
|
|
0x0234 0x00 0x0
|
|
0x029c 0x80 0x0
|
|
0x02a0 0x7c 0x0
|
|
0x02b4 0x05 0x0
|
|
0x02d4 0x10 0x0
|
|
0x02e8 0x0a 0x0
|
|
0x030c 0x0d 0x0
|
|
0x0320 0x0b 0x0
|
|
0x0348 0x1c 0x0
|
|
0x0388 0x20 0x0
|
|
0x0394 0x30 0x0
|
|
0x03dc 0x09 0x0
|
|
0x03f4 0x14 0x0
|
|
0x03f8 0xb3 0x0
|
|
0x03fc 0x58 0x0
|
|
0x0400 0x9a 0x0
|
|
0x0404 0x26 0x0
|
|
0x0408 0xb6 0x0
|
|
0x040c 0xee 0x0
|
|
0x0410 0xdb 0x0
|
|
0x0414 0xdb 0x0
|
|
0x0418 0xa0 0x0
|
|
0x041c 0xdf 0x0
|
|
0x0420 0x78 0x0
|
|
0x0424 0x76 0x0
|
|
0x0428 0xff 0x0
|
|
0x02e0 0x00 0x0
|
|
0x0830 0x1d 0x0
|
|
0x0834 0x03 0x0
|
|
0x0878 0x01 0x0
|
|
0x087c 0x00 0x0
|
|
0x0880 0x51 0x0
|
|
0x08ac 0x34 0x0
|
|
0x0a08 0x0c 0x0
|
|
0x0a0c 0x0a 0x0
|
|
0x0a18 0x04 0x0
|
|
0x0a20 0x16 0x0
|
|
0x0a34 0x00 0x0
|
|
0x0a9c 0x80 0x0
|
|
0x0aa0 0x7c 0x0
|
|
0x0ab4 0x05 0x0
|
|
0x0ad4 0x10 0x0
|
|
0x0ae8 0x0a 0x0
|
|
0x0b0c 0x0d 0x0
|
|
0x0b20 0x0b 0x0
|
|
0x0b48 0x1c 0x0
|
|
0x0b88 0x20 0x0
|
|
0x0b94 0x30 0x0
|
|
0x0bdc 0x09 0x0
|
|
0x0bf4 0x14 0x0
|
|
0x0bf8 0xb3 0x0
|
|
0x0bfc 0x58 0x0
|
|
0x0c00 0x9a 0x0
|
|
0x0c04 0x26 0x0
|
|
0x0c08 0xb6 0x0
|
|
0x0c0c 0xee 0x0
|
|
0x0c10 0xdb 0x0
|
|
0x0c14 0xdb 0x0
|
|
0x0c18 0xa0 0x0
|
|
0x0c1c 0xdf 0x0
|
|
0x0c20 0x78 0x0
|
|
0x0c24 0x76 0x0
|
|
0x0c28 0xff 0x0
|
|
0x0ae0 0x00 0x0
|
|
0x0ea0 0x01 0x0
|
|
0x0eb4 0x00 0x0
|
|
0x0ec4 0x02 0x0
|
|
0x0ec8 0x0d 0x0
|
|
0x0ed4 0x12 0x0
|
|
0x0ed8 0x12 0x0
|
|
0x0edc 0xdb 0x0
|
|
0x0ee0 0x9a 0x0
|
|
0x0ee4 0x38 0x0
|
|
0x0ee8 0xb6 0x0
|
|
0x0eec 0x64 0x0
|
|
0x0ef0 0x1f 0x0
|
|
0x0ef4 0x1f 0x0
|
|
0x0ef8 0x1f 0x0
|
|
0x0efc 0x1f 0x0
|
|
0x0f00 0x1f 0x0
|
|
0x0f04 0x1f 0x0
|
|
0x0f0c 0x1f 0x0
|
|
0x0f14 0x1f 0x0
|
|
0x0f1c 0x1f 0x0
|
|
0x0f28 0x5b 0x0
|
|
0x1000 0x26 0x0
|
|
0x1004 0x03 0x0
|
|
0x1010 0x06 0x0
|
|
0x1014 0x16 0x0
|
|
0x1018 0x36 0x0
|
|
0x101c 0x04 0x0
|
|
0x1020 0x0a 0x0
|
|
0x1024 0x1a 0x0
|
|
0x1028 0x68 0x0
|
|
0x1030 0xab 0x0
|
|
0x1034 0xaa 0x0
|
|
0x1038 0x02 0x0
|
|
0x103c 0x12 0x0
|
|
0x1060 0xf8 0x0
|
|
0x1064 0x01 0x0
|
|
0x1070 0x06 0x0
|
|
0x1074 0x16 0x0
|
|
0x1078 0x36 0x0
|
|
0x107c 0x0a 0x0
|
|
0x1080 0x04 0x0
|
|
0x1084 0x0d 0x0
|
|
0x1088 0x41 0x0
|
|
0x1090 0xab 0x0
|
|
0x1094 0xaa 0x0
|
|
0x1098 0x01 0x0
|
|
0x109c 0x00 0x0
|
|
0x10bc 0x0a 0x0
|
|
0x10c0 0x01 0x0
|
|
0x10cc 0x62 0x0
|
|
0x10d0 0x02 0x0
|
|
0x10d8 0x40 0x0
|
|
0x10dc 0x14 0x0
|
|
0x10e0 0x90 0x0
|
|
0x10e4 0x82 0x0
|
|
0x10f4 0x0f 0x0
|
|
0x1110 0x08 0x0
|
|
0x1120 0x46 0x0
|
|
0x1124 0x04 0x0
|
|
0x1140 0x14 0x0
|
|
0x1164 0x34 0x0
|
|
0x1170 0xa0 0x0
|
|
0x1174 0x06 0x0
|
|
0x1184 0x88 0x0
|
|
0x1188 0x14 0x0
|
|
0x1198 0x0f 0x0
|
|
0x1378 0x2e 0x0
|
|
0x1390 0xcc 0x0
|
|
0x13f8 0x00 0x0
|
|
0x13fc 0x22 0x0
|
|
0x141c 0xc1 0x0
|
|
0x129c 0x87 0x0
|
|
0x12a0 0x05 0x0
|
|
0x12a4 0xa1 0x0
|
|
0x1450 0x0f 0x0
|
|
0x1490 0x00 0x0
|
|
0x14a0 0x16 0x0
|
|
0x14f0 0x27 0x0
|
|
0x14f4 0x27 0x0
|
|
0x1508 0x02 0x0
|
|
0x155c 0x2e 0x0
|
|
0x157c 0x03 0x0
|
|
0x1584 0x28 0x0
|
|
0x13dc 0x04 0x0
|
|
0x13e0 0x02 0x0
|
|
0x1418 0xc0 0x0
|
|
0x140c 0x1d 0x0
|
|
0x158c 0x0f 0x0
|
|
0x15ac 0xf2 0x0
|
|
0x15c0 0xf2 0x0
|
|
0x1370 0x17 0x0
|
|
0x1200 0x00 0x0
|
|
0x1244 0x03 0x0>;
|
|
|
|
status = "disabled";
|
|
|
|
pcie1_rp: pcie1_rp {
|
|
reg = <0 0 0 0 0>;
|
|
};
|
|
};
|
|
|
|
pcie1_msi: qcom,pcie1_msi@17210040 {
|
|
compatible = "qcom,pci-msi";
|
|
msi-controller;
|
|
interrupt-parent = <&intc>;
|
|
reg = <0x17210040 0x0>;
|
|
interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
status = "ok";
|
|
};
|
|
|
|
pcie2: qcom,pcie@1c08000 {
|
|
compatible = "qcom,pci-msm";
|
|
|
|
reg = <0x1c08000 0x3000>,
|
|
<0x1c0e000 0x2000>,
|
|
<0x40000000 0xf1d>,
|
|
<0x40000f20 0xa8>,
|
|
<0x40001000 0x1000>,
|
|
<0x40100000 0x100000>,
|
|
<0x1c0b000 0x1000>;
|
|
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "mhi";
|
|
|
|
cell-index = <2>;
|
|
linux,pci-domain = <2>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1d00000>;
|
|
|
|
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
|
|
"int_d";
|
|
|
|
msi-parent = <&pcie2_msi>;
|
|
|
|
perst-gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
|
|
card-presence-pin = <&tlmm 71 GPIO_ACTIVE_HIGH>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&pcie2_perst_default>;
|
|
pinctrl-1 = <&pcie2_perst_default>;
|
|
|
|
gdsc-core-vdd-supply = <&gcc_pcie_2_gdsc>;
|
|
gdsc-phy-vdd-supply = <&gcc_pcie_2_phy_gdsc>;
|
|
vreg-1p2-supply = <&L1D>;
|
|
vreg-0p9-supply = <&L1B>;
|
|
vreg-cx-supply = <&VDD_CX_LEVEL>;
|
|
vreg-mx-supply = <&VDD_MXA_LEVEL>;
|
|
qcom,vreg-1p2-voltage-level = <1200000 1200000 21710>;
|
|
qcom,vreg-0p9-voltage-level = <912000 880000 179340>;
|
|
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
|
RPMH_REGULATOR_LEVEL_NOM 0>;
|
|
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
|
RPMH_REGULATOR_LEVEL_NOM 0>;
|
|
qcom,bw-scale = /* Gen1 */
|
|
<RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
19200000
|
|
/* Gen2 */
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
19200000
|
|
/* Gen3 */
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
100000000
|
|
/* Gen4 */
|
|
RPMH_REGULATOR_LEVEL_NOM
|
|
RPMH_REGULATOR_LEVEL_NOM
|
|
100000000>;
|
|
|
|
interconnect-names = "icc_path";
|
|
interconnects = <&pcie_anoc MASTER_PCIE_2 &mc_virt SLAVE_EBI1>;
|
|
|
|
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_PCIE_2_AUX_CLK>,
|
|
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_2_SLV_AXI_CLK>,
|
|
<&tcsrcc TCSR_PCIE_2_CLKREF_EN>,
|
|
<&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
|
|
<&gcc GCC_PCIE_2_PHY_RCHNG_CLK>,
|
|
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
|
|
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
|
|
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
|
|
<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
|
|
<&gcc GCC_PCIE_2_PIPE_CLK_SRC>,
|
|
<&gcc GCC_PCIE_2_PIPE_DIV2_CLK>,
|
|
<&gcc GCC_PCIE_2_PHY_AUX_CLK>,
|
|
<&gcc GCC_PCIE_2_PHY_AUX_CLK_SRC>,
|
|
<&pcie_2_pipe_clk>,
|
|
<&pcie_2_phy_aux_clk>;
|
|
clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
|
|
"pcie_aux_clk", "pcie_cfg_ahb_clk",
|
|
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
|
|
"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
|
|
"pcie_rate_change_clk",
|
|
"gcc_ddrss_pcie_sf_qtb_clk",
|
|
"pcie_aggre_noc_axi_clk",
|
|
"gcc_cnoc_pcie_sf_axi_clk",
|
|
"pcie_cfg_noc_pcie_anoc_ahb_clk",
|
|
"pcie_pipe_clk_mux", "pcie_2_pipe_div2_clk",
|
|
"pcie_phy_aux_clk", "pcie_phy_aux_clk_mux",
|
|
"pcie_pipe_clk_ext_src", "pcie_phy_aux_clk_ext_src";
|
|
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
|
|
<100000000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
|
|
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
|
|
<0>, <0>, <0>, <1>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
|
|
|
|
resets = <&gcc GCC_PCIE_2_BCR>,
|
|
<&gcc GCC_PCIE_2_PHY_BCR>;
|
|
reset-names = "pcie_2_core_reset",
|
|
"pcie_2_phy_reset";
|
|
|
|
dma-coherent;
|
|
qcom,smmu-sid-base = <0x1400>;
|
|
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
|
|
<0x100 &apps_smmu 0x1401 0x1>;
|
|
|
|
qcom,boot-option = <0x1>;
|
|
qcom,no-client-based-bw-voting;
|
|
qcom,apss-based-l1ss-sleep;
|
|
qcom,drv-l1ss-timeout-us = <5000>;
|
|
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
|
|
qcom,slv-addr-space-size = <0x20000000>;
|
|
qcom,ep-latency = <10>;
|
|
qcom,num-parf-testbus-sel = <0xb9>;
|
|
qcom,l1-2-th-scale = <2>;
|
|
qcom,l1-2-th-value = <150>;
|
|
|
|
qcom,pcie-clkreq-offset = <0x2c48>;
|
|
|
|
qcom,pcie-phy-ver = <115>;
|
|
qcom,phy-aux-clk-config1-offset = <0x1450>;
|
|
qcom,phy-status-offset = <0x1214>;
|
|
qcom,phy-status-bit = <7>;
|
|
qcom,phy-power-down-offset = <0x1240>;
|
|
|
|
qcom,phy-sequence = <0x1240 0x03 0x0
|
|
0x0030 0x1f 0x0
|
|
0x0034 0x07 0x0
|
|
0x0078 0x01 0x0
|
|
0x007c 0x10 0x0
|
|
0x0080 0x51 0x0
|
|
0x00ac 0x34 0x0
|
|
0x0208 0x0c 0x0
|
|
0x020c 0x0a 0x0
|
|
0x0218 0x04 0x0
|
|
0x0220 0x16 0x0
|
|
0x0234 0x00 0x0
|
|
0x029c 0x82 0x0
|
|
0x02a0 0x00 0x0
|
|
0x02b0 0x00 0x0
|
|
0x02b4 0x05 0x0
|
|
0x02d4 0x10 0x0
|
|
0x02e8 0x0a 0x0
|
|
0x030c 0x0d 0x0
|
|
0x0320 0x0b 0x0
|
|
0x0348 0x1c 0x0
|
|
0x0388 0x20 0x0
|
|
0x0394 0x38 0x0
|
|
0x03dc 0x01 0x0
|
|
0x03f4 0x14 0x0
|
|
0x03f8 0xb3 0x0
|
|
0x03fc 0x58 0x0
|
|
0x0400 0x9a 0x0
|
|
0x0404 0x26 0x0
|
|
0x0408 0xb6 0x0
|
|
0x040c 0xee 0x0
|
|
0x0410 0x9b 0x0
|
|
0x0414 0xa4 0x0
|
|
0x0418 0xe0 0x0
|
|
0x041c 0xdf 0x0
|
|
0x0420 0x78 0x0
|
|
0x0424 0x76 0x0
|
|
0x0428 0xf7 0x0
|
|
0x02e0 0x00 0x0
|
|
0x0830 0x1f 0x0
|
|
0x0834 0x07 0x0
|
|
0x0878 0x01 0x0
|
|
0x087c 0x10 0x0
|
|
0x0880 0x51 0x0
|
|
0x08ac 0x34 0x0
|
|
0x0a08 0x0c 0x0
|
|
0x0a0c 0x0a 0x0
|
|
0x0a18 0x04 0x0
|
|
0x0a20 0x16 0x0
|
|
0x0a34 0x00 0x0
|
|
0x0a9c 0x82 0x0
|
|
0x0aa0 0x00 0x0
|
|
0x0ab0 0x00 0x0
|
|
0x0ab4 0x05 0x0
|
|
0x0ad4 0x10 0x0
|
|
0x0ae8 0x0a 0x0
|
|
0x0b0c 0x0d 0x0
|
|
0x0b20 0x0b 0x0
|
|
0x0b48 0x1c 0x0
|
|
0x0b88 0x20 0x0
|
|
0x0b94 0x38 0x0
|
|
0x0bdc 0x01 0x0
|
|
0x0bf4 0x14 0x0
|
|
0x0bf8 0xb3 0x0
|
|
0x0bfc 0x58 0x0
|
|
0x0c00 0x9a 0x0
|
|
0x0c04 0x26 0x0
|
|
0x0c08 0xb6 0x0
|
|
0x0c0c 0xee 0x0
|
|
0x0c10 0x9b 0x0
|
|
0x0c14 0xa4 0x0
|
|
0x0c18 0xe0 0x0
|
|
0x0c1c 0xdf 0x0
|
|
0x0c20 0x78 0x0
|
|
0x0c24 0x76 0x0
|
|
0x0c28 0xf7 0x0
|
|
0x0ae0 0x00 0x0
|
|
0x0ea0 0x01 0x0
|
|
0x0eb4 0x88 0x0
|
|
0x0eb8 0x00 0x0
|
|
0x0ec4 0x02 0x0
|
|
0x0ec8 0x0d 0x0
|
|
0x0ed4 0x12 0x0
|
|
0x0ed8 0x12 0x0
|
|
0x0edc 0xdb 0x0
|
|
0x0ee0 0x9a 0x0
|
|
0x0ee4 0x38 0x0
|
|
0x0ee8 0xb6 0x0
|
|
0x0eec 0x64 0x0
|
|
0x0ef0 0x1f 0x0
|
|
0x0ef4 0x1f 0x0
|
|
0x0ef8 0x1f 0x0
|
|
0x0efc 0x1f 0x0
|
|
0x0f00 0x1f 0x0
|
|
0x0f04 0x1f 0x0
|
|
0x0f0c 0x1f 0x0
|
|
0x0f14 0x1f 0x0
|
|
0x0f1c 0x1f 0x0
|
|
0x0f28 0x5b 0x0
|
|
0x1000 0x26 0x0
|
|
0x1004 0x03 0x0
|
|
0x1010 0x06 0x0
|
|
0x1014 0x16 0x0
|
|
0x1018 0x36 0x0
|
|
0x101c 0x04 0x0
|
|
0x1020 0x0a 0x0
|
|
0x1024 0x1a 0x0
|
|
0x1028 0x68 0x0
|
|
0x1030 0xab 0x0
|
|
0x1034 0xaa 0x0
|
|
0x1038 0x02 0x0
|
|
0x103c 0x12 0x0
|
|
0x1060 0xf8 0x0
|
|
0x1064 0x01 0x0
|
|
0x1070 0x06 0x0
|
|
0x1074 0x16 0x0
|
|
0x1078 0x36 0x0
|
|
0x107c 0x0a 0x0
|
|
0x1080 0x04 0x0
|
|
0x1084 0x0d 0x0
|
|
0x1088 0x41 0x0
|
|
0x1090 0xab 0x0
|
|
0x1094 0xaa 0x0
|
|
0x1098 0x01 0x0
|
|
0x109c 0x00 0x0
|
|
0x10bc 0x0a 0x0
|
|
0x10c0 0x01 0x0
|
|
0x10cc 0x62 0x0
|
|
0x10d0 0x02 0x0
|
|
0x10d8 0x40 0x0
|
|
0x10dc 0x14 0x0
|
|
0x10e0 0x90 0x0
|
|
0x10e4 0x82 0x0
|
|
0x10f4 0x0f 0x0
|
|
0x1110 0x08 0x0
|
|
0x1120 0x46 0x0
|
|
0x1124 0x04 0x0
|
|
0x1140 0x14 0x0
|
|
0x1164 0x34 0x0
|
|
0x1170 0xa0 0x0
|
|
0x1174 0x06 0x0
|
|
0x1184 0x88 0x0
|
|
0x1188 0x14 0x0
|
|
0x1198 0x0f 0x0
|
|
0x1378 0x2e 0x0
|
|
0x1390 0xcc 0x0
|
|
0x13f8 0x00 0x0
|
|
0x13fc 0x22 0x0
|
|
0x141c 0xc1 0x0
|
|
0x129c 0x83 0x0
|
|
0x12a0 0x09 0x0
|
|
0x12a4 0xa2 0x0
|
|
0x1450 0x02 0x0
|
|
0x1490 0x00 0x0
|
|
0x14a0 0x16 0x0
|
|
0x14f0 0x27 0x0
|
|
0x14f4 0x27 0x0
|
|
0x1508 0x02 0x0
|
|
0x155c 0x2e 0x0
|
|
0x157c 0x03 0x0
|
|
0x1584 0x28 0x0
|
|
0x13dc 0x04 0x0
|
|
0x13e0 0x02 0x0
|
|
0x1418 0xc0 0x0
|
|
0x140c 0x1d 0x0
|
|
0x158c 0x0f 0x0
|
|
0x15ac 0xf2 0x0
|
|
0x15c0 0xf2 0x0
|
|
0x1370 0x17 0x0
|
|
0x1200 0x00 0x0
|
|
0x1244 0x03 0x0>;
|
|
|
|
pcie2_rp: pcie2_rp {
|
|
reg = <0 0 0 0 0>;
|
|
};
|
|
};
|
|
|
|
pcie2_msi: qcom,pcie2_msi@17210040 {
|
|
msi-controller;
|
|
compatible = "qcom,pci-msi";
|
|
interrupt-parent = <&intc>;
|
|
reg = <0x17210040 0x0>;
|
|
interrupts = <GIC_SPI 832 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 833 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 834 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 835 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 836 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 837 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 838 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 839 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 840 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 841 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 842 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 843 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 844 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 845 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 846 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 847 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 848 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 849 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 850 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 851 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 852 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 853 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 854 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 856 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 857 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 858 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 859 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 860 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 861 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 862 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 863 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
status = "ok";
|
|
};
|
|
};
|