mirror of
https://github.com/oplus-giulia-dev/android_kernel_oneplus_sm8650-devicetrees
synced 2025-11-04 06:44:04 +08:00
250 lines
6.5 KiB
Plaintext
250 lines
6.5 KiB
Plaintext
&soc {
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pcie0: qcom,pcie@1c08000 {
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compatible = "qcom,pci-msm";
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cell-index = <0>;
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reg = <0x1c08000 0x4000>,
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<0x1c0e000 0x1000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xa8>,
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<0x40001000 0x1000>,
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<0x40100000 0x100000>,
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<0x40200000 0x100000>,
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<0x40300000 0x1fd00000>;
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reg-names = "parf", "phy", "dm_core", "elbi",
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"iatu", "conf", "io", "bars";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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qcom,phy-sequence = <0x0800 0x01 0x0
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0x0804 0x03 0x0
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0x0034 0x18 0x0
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0x0038 0x10 0x0
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0x0070 0x0f 0x0
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0x00c8 0x01 0x0
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0x0128 0x00 0x0
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0x0144 0xff 0x0
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0x0148 0x1f 0x0
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0x0194 0x06 0x0
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0x0048 0x0f 0x0
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0x0178 0x00 0x0
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0x019c 0x01 0x0
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0x018c 0x20 0x0
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0x0184 0x0a 0x0
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0x00b4 0x20 0x0
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0x000c 0x09 0x0
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0x00ac 0x04 0x0
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0x00d0 0x82 0x0
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0x00e4 0x03 0x0
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0x00e0 0x55 0x0
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0x00dc 0x55 0x0
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0x0054 0x00 0x0
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0x0050 0x0d 0x0
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0x004c 0x04 0x0
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0x0174 0x35 0x0
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0x003c 0x02 0x0
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0x0040 0x1f 0x0
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0x0078 0x04 0x0
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0x0084 0x16 0x0
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0x0090 0x30 0x0
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0x010c 0x00 0x0
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0x0108 0x80 0x0
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0x00a8 0x01 0x0
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0x000c 0x0a 0x0
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0x0010 0x01 0x0
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0x001c 0x31 0x0
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0x0020 0x01 0x0
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0x0014 0x02 0x0
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0x0018 0x00 0x0
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0x0024 0x2f 0x0
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0x0028 0x19 0x0
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0x0268 0x45 0x0
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0x0194 0x06 0x0
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0x024c 0x02 0x0
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0x02ac 0x12 0x0
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0x0510 0x1c 0x0
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0x051c 0x14 0x0
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0x04d8 0x01 0x0
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0x04dc 0x00 0x0
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0x04e0 0xdb 0x0
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0x0448 0x4b 0x0
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0x041c 0x04 0x0
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0x0410 0x04 0x0
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0x0074 0x19 0x0
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0x0854 0x04 0x0
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0x09ac 0x00 0x0
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0x08a0 0x40 0x0
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0x09e0 0x00 0x0
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0x09dc 0x40 0x0
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0x09a8 0x00 0x0
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0x08a4 0x40 0x0
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0x08a8 0x73 0x0
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0x09b0 0x07 0x0
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0x09d8 0x99 0x0
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0x0824 0x15 0x0
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0x0828 0x0e 0x0
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0x0800 0x00 0x0
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0x0808 0x03 0x0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_clkreq_default
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&pcie0_perst_default
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&pcie0_wake_default>;
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perst-gpio = <&tlmm 101 0>;
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wake-gpio = <&tlmm 100 0>;
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gdsc-core-vdd-supply = <&pcie_0_gdsc>;
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vreg-1p2-supply = <&L12A>;
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vreg-0p9-supply = <&L5A>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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qcom,vreg-1p2-voltage-level = <1800000 1800000 24000>;
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qcom,vreg-0p9-voltage-level = <925000 925000 24000>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
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RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
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RPMH_REGULATOR_LEVEL_NOM 100000000>;
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qcom,no-l0s-supported;
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qcom,no-l1-supported;
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qcom,no-l1ss-supported;
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qcom,no-aux-clk-sync;
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msi-parent = <&pcie0_msi>;
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qcom,max-link-speed = <0x2>;
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qcom,ep-latency = <10>;
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qcom,slv-addr-space-size = <0x20000000>;
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qcom,phy-status-offset = <0x974>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x804>;
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qcom,core-preset = <0x77777777>;
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qcom,boot-option = <0x1>;
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linux,pci-domain = <0>;
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qcom,pcie-phy-ver = <2609>;
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qcom,use-19p2mhz-aux-clk;
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qcom,smmu-sid-base = <0x0400>;
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iommu-map = <0x0 &apps_smmu 0x0400 0x1>,
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<0x100 &apps_smmu 0x0401 0x1>,
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<0x200 &apps_smmu 0x0402 0x1>,
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<0x300 &apps_smmu 0x0403 0x1>,
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<0x400 &apps_smmu 0x0404 0x1>,
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<0x500 &apps_smmu 0x0405 0x1>,
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<0x600 &apps_smmu 0x0406 0x1>,
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<0x700 &apps_smmu 0x0407 0x1>,
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<0x800 &apps_smmu 0x0408 0x1>,
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<0x900 &apps_smmu 0x0409 0x1>,
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<0xa00 &apps_smmu 0x040a 0x1>,
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<0xb00 &apps_smmu 0x040b 0x1>,
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<0xc00 &apps_smmu 0x040c 0x1>,
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<0xd00 &apps_smmu 0x040d 0x1>,
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<0xe00 &apps_smmu 0x040e 0x1>,
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<0xf00 &apps_smmu 0x040f 0x1>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&dummycc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_CLK>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
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<&gcc GCC_PCIE_PHY_AUX_CLK>;
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clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_ldo", "pcie_0_slv_q2a_axi_clk",
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"pcie_phy_refgen_clk","pcie_phy_aux_clk";
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clock-frequency = <0>, <0>, <19200000>, <0>, <0>,
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<0>, <0>, <0>, <100000000>, <0>;
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clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
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<0>, <0>, <0>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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status = "disabled";
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pcie_rc0: pcie_rc0 {
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#address-cells = <5>;
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#size-cells = <0>;
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reg = <0 0 0 0 0>;
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pci-ids = "17cb:010a";
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};
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};
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pcie0_msi: qcom,pcie0_msi@17a00040 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x17a00040 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 672 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 673 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 674 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 675 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 676 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 677 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 678 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 679 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 680 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 681 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 682 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 683 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 684 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 685 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 686 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 687 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 688 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 689 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 690 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 691 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 692 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 693 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 694 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 695 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 696 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 697 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 698 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 699 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 700 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 701 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 702 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 703 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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};
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