mirror of
https://github.com/oplus-giulia-dev/android_kernel_oneplus_sm8650-devicetrees
synced 2025-11-04 06:44:04 +08:00
ce9ce2cc41
Add a snapshot for sa8155 lagvm from msm-5.15 branch at
commit 86a37b915a9f ("ARM: dts: msm: Add virt-ssr node for
linux gvm").
Change-Id: I35cfa77a0f3637202f1c05d59b254c995675996f
140 lines
3.9 KiB
Plaintext
140 lines
3.9 KiB
Plaintext
&soc {
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/* QUPv3 SE Instances
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* Qup0 0: SE 0
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* Qup0 1: SE 1
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* Qup0 2: SE 2
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* Qup0 3: SE 3
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* Qup0 4: SE 4
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* Qup0 5: SE 5
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* Qup0 6: SE 6
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* Qup0 7: SE 7
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* Qup1 0: SE 8
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* Qup1 1: SE 9
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* Qup1 2: SE 10
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* Qup1 3: SE 11
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* Qup1 4: SE 12
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* Qup1 5: SE 13
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* Qup2 0: SE 14
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* Qup2 1: SE 15
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* Qup2 2: SE 16
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* Qup2 3: SE 17
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* Qup2 4: SE 18
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* Qup2 5: SE 19
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*/
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/* QUPv3_0 wrapper instance */
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qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x8c0000 0x6000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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iommus = <&apps_smmu 0xc3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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status = "ok";
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/* I2C instance for SDR Card*/
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qupv3_se2_i2c: i2c@888000 {
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compatible = "qcom,i2c-geni";
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reg = <0x888000 0x4000>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_i2c_active>;
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pinctrl-1 = <&qupv3_se2_i2c_sleep>;
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status = "disabled";
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};
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};
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/* QUPv3_1 wrapper instance */
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qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0xac0000 0x6000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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iommus = <&apps_smmu 0x603 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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status = "ok";
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/* Debug UART Instance */
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qupv3_se12_2uart: qcom,qup_uart@a90000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0xa90000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se12_2uart_active>;
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pinctrl-1 = <&qupv3_se12_2uart_sleep>;
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status = "disabled";
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};
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};
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/* QUPv3_2 wrapper instance */
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qupv3_2: qcom,qupv3_2_geni_se@cc0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0xcc0000 0x6000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
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iommus = <&apps_smmu 0x7a3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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status = "ok";
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/* HS UART Instance */
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qupv3_se17_4uart: qcom,qup_uart@c8c000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0xc8c000 0x4000>;
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reg-names = "se_phys";
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interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 46 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
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pinctrl-names = "default", "active", "sleep", "shutdown";
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pinctrl-0 = <&qupv3_se17_default_ctsrtsrx>,
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<&qupv3_se17_default_tx>;
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pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
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<&qupv3_se17_tx>;
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pinctrl-2 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
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<&qupv3_se17_tx>;
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pinctrl-3 = <&qupv3_se17_default_ctsrtsrx>,
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<&qupv3_se17_default_tx>;
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qcom,wakeup-byte = <0xFD>;
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status = "disabled";
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};
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qupv3_se19_i2c: i2c@c94000 {
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compatible = "qcom,i2c-geni";
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reg = <0xc94000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se19_i2c_active>;
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pinctrl-1 = <&qupv3_se19_i2c_sleep>;
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status = "disabled";
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};
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};
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};
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