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android_kernel_oneplus_sm86…/qcom/sdmshrike.dtsi

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#include <dt-bindings/clock/qcom,camcc-sc8180x.h>
#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
#include <dt-bindings/clock/qcom,npucc-sm8150.h>
#include <dt-bindings/clock/qcom,scc-sm8150.h>
#include <dt-bindings/clock/qcom,videocc-sm8150.h>
#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sc8180x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/spmi/spmi.h>
/ {
model = "Qualcomm Technologies, Inc. SDMSHRIKE";
compatible = "qcom,sdmshrike";
qcom,msm-name = "SDMSHRIKE";
qcom,msm-id = <340 0x10000>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
ddr-regions { };
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS slot */
ufshc2 = &ufshc2_mem; /* Embedded 2nd UFS slot */
mmc1 = &sdhc_2; /* SDC2 SD Card slot */
serial0 = &qupv3_se12_2uart;
hsuart0 = &qupv3_se17_4uart;
hsuart1 = &qupv3_se9_2uart;
spi22 = &qupv3_se22_spi;
i2c7 = &qupv3_se20_i2c;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&SILVER_OFF>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-size = <0x400000>;
cache-level = <3>;
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&SILVER_OFF>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_1>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
cpu-idle-states = <&SILVER_OFF>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_2>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
#cooling-cells = <2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
cpu-idle-states = <&SILVER_OFF>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_3>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x400>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF>;
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <431>;
cache-size = <0x10000>;
next-level-cache = <&L2_4>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
#cooling-cells = <2>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x500>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF>;
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <431>;
cache-size = <0x10000>;
next-level-cache = <&L2_5>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x600>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF>;
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <431>;
cache-size = <0x10000>;
next-level-cache = <&L2_6>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x700>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF>;
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <431>;
cache-size = <0x10000>;
next-level-cache = <&L2_7>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
};
idle-states {
SILVER_OFF: silver-c4 { /* C4 */
compatible = "arm,idle-state";
idle-state-name = "rail-pc";
entry-latency-us = <355>;
exit-latency-us = <909>;
min-residency-us = <3934>;
arm,psci-suspend-param = <0x40000004>;
local-timer-stop;
};
GOLD_OFF: gold-c4 { /* C4 */
compatible = "arm,idle-state";
idle-state-name = "rail-pc";
entry-latency-us = <2411>;
exit-latency-us = <1461>;
min-residency-us = <4488>;
arm,psci-suspend-param = <0x40000004>;
local-timer-stop;
};
APSS_OFF: cluster-e3 { /* E3 */
compatible = "domain-idle-state";
idle-state-name = "llcc-off";
entry-latency-us = <3263>;
exit-latency-us = <6562>;
min-residency-us = <9987>;
arm,psci-suspend-param = <0x4100a344>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: cpu-pd0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD1: cpu-pd1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD2: cpu-pd2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD3: cpu-pd3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD4: cpu-pd4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD5: cpu-pd5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD6: cpu-pd6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD7: cpu-pd7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CLUSTER_PD: cluster-pd {
#power-domain-cells = <0>;
domain-idle-states = <&APSS_OFF>;
};
};
chosen {
bootargs = "kpti=0 ssbd=force-off qcom_dma_heaps.enable_bitstream_contig_heap=y ufshcd-core.use_mcq_mode=n rcupdate.rcu_expedited=1 cpufreq.default_governor=performance ufshcd_core.uic_cmd_timeout=2000";
};
firmware: firmware {
android {
compatible = "android,firmware";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/platform/soc
/1d84000.ufshc/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
fsmgr_flags = "wait,slotselect,avb";
status = "ok";
};
};
};
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: hyp_mem@85700000 {
no-map;
reg = <0x0 0x85700000 0x0 0x600000>;
};
xbl_aop_mem: xbl_aop_mem@85e00000 {
no-map;
reg = <0x0 0x85e00000 0x0 0x120000>;
};
flex_sec_apps_mem: flex_sec_apps_regions@85ffd000 {
no-map;
reg = <0x0 0x85ffd000 0x0 0x3000>;
};
aop_cmd_db: memory@85f20000 {
compatible = "qcom,cmd-db";
reg = <0x0 0x85f20000 0x0 0x20000>;
no-map;
};
smem_region: smem@86000000 {
no-map;
reg = <0x0 0x86000000 0x0 0x200000>;
};
removed_regions: removed_regions@86200000 {
no-map;
reg = <0x0 0x86200000 0x0 0x5500000>;
};
pil_camera_mem: camera_region@8b700000 {
no-map;
reg = <0x0 0x8b700000 0x0 0x500000>;
};
pil_npu_mem: pil_npu_region@8bd80000 {
no-map;
reg = <0x0 0x8bd80000 0x0 0x80000>;
};
rproc_adsp_mem: rproc_adsp_region@8be00000 {
no-map;
reg = <0x0 0x8be00000 0x0 0x1a00000>;
};
pil_modem_mem: modem_region@8d800000 {
no-map;
reg = <0x0 0x8d800000 0x0 0x9600000>;
};
pil_video_mem: pil_video_region@96e00000 {
no-map;
reg = <0x0 0x96e00000 0x0 0x500000>;
};
pil_slpi_mem: pil_slpi_region@97300000 {
no-map;
reg = <0x0 0x97300000 0x0 0x1400000>;
};
pil_ipa_fw_mem: pil_ipa_fw_region@98700000 {
no-map;
reg = <0x0 0x98700000 0x0 0x10000>;
};
pil_ipa_gsi_mem: pil_ipa_gsi_region@98710000 {
no-map;
reg = <0x0 0x98710000 0x0 0x5000>;
};
gpu_micro_code_mem: gpu_micro_code_region@98715000 {
no-map;
reg = <0x0 0x98715000 0x0 0x2000>;
};
pil_spss_mem: pil_spss_region@98800000 {
no-map;
reg = <0x0 0x98800000 0x0 0x100000>;
};
rproc_cdsp_mem: rproc_cdsp_region@98900000 {
no-map;
reg = <0x0 0x98900000 0x0 0x1400000>;
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0x9e400000 0x0 0x1400000>;
};
cont_splash_memory: splash_region {
reg = <0x0 0x9c000000 0x0 0x02400000>;
label = "cont_splash_region";
};
adsp_mem: adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
cdsp_mem: cdsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x400000>;
};
user_contig_mem: user_contig_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x800000>;
};
secure_display_memory: secure_display_region { /* Secure UI */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0xA000000>;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
size = <0 0x2400000>;
};
/* global autoconfigured region for contiguous allocations */
system_cma: linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2800000>;
linux,cma-default;
};
kinfo_mem: debug_kinfo_region {
alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
size = <0x0 0x1000>;
no-map;
};
};
soc: soc { };
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0x17a00000 0x10000>, /* GICD */
<0x17a60000 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
timer@17c20000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17c20000 0x1000>;
clock-frequency = <19200000>;
frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c23000 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c25000 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c26000 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c29000 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c2b000 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c2d000 0x1000>;
status = "disabled";
};
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
clock-output-names = "xo_board";
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-output-names = "sleep_clk";
};
};
/*
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>;
};
*/
qcom,msm-imem@146bf000 {
compatible = "qcom,msm-imem";
reg = <0x146bf000 0x1000>;
ranges = <0x0 0x146bf000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 0x4>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 0xc>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
};
dload_mode {
compatible = "qcom,dload-mode";
};
tcsr: syscon@1fc0000 {
compatible = "syscon";
reg = <0x1fc0000 0x30000>;
};
qcom,mpm2-sleep-counter@c221000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0xc221000 0x1000>;
clock-frequency = <32768>;
};
vendor_hooks: qcom,cpu-vendor-hooks {
compatible = "qcom,cpu-vendor-hooks";
};
mini_dump_mode {
compatible = "qcom,minidump";
status = "ok";
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x18200000 0x10000>,
<0x18210000 0x10000>,
<0x18220000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
qcom,drv-count = <3>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&CLUSTER_PD>;
apps_rsc_drv2: drv@2 {
qcom,drv-id = <2>;
qcom,tcs-offset = <0xd00>;
channel@0 {
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>,
<FAST_PATH_TCS 0>;
};
rpmhcc: clock-controller {
compatible = "qcom,sm8150-rpmh-clk";
#clock-cells = <1>;
status = "okay";
};
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
};
};
cluster-device {
compatible = "qcom,lpm-cluster-dev";
power-domains = <&CLUSTER_PD>;
};
disp_rsc: rsc@af20000 {
label = "disp_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0xaf20000 0x10000>;
reg-names = "drv-0";
qcom,drv-count = <1>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
disp_rsc_drv0: drv@0 {
qcom,drv-id = <0>;
qcom,tcs-offset = <0x1c00>;
channel@0 {
qcom,tcs-config = <SLEEP_TCS 1>,
<WAKE_TCS 1>,
<ACTIVE_TCS 2>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 0>;
};
disp_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
};
};
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,pdc";
reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
ddr_bwprofiler {
compatible = "qcom,ddr_bwprofiler";
clocks = <&aoss_qmp QDSS_CLK>;
clock-names = "qdss_clk";
};
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sc8180x", "syscon";
reg = <0x100000 0x1f0000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
protected-clocks = <GCC_NPU_AXI_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
};
scc: clock-controller@2b10000 {
compatible = "qcom,sc8180x-scc";
reg = <0x2b10000 0x30000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
#clock-cells = <1>;
status = "disabled";
};
gpucc: clock-controller@2c90000 {
compatible = "qcom,sc8180x-gpucc", "syscon";
reg = <0x2c90000 0x9000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", "gcc_gpu_gpll0_div_clk_src";
#clock-cells = <1>;
#reset-cells = <1>;
};
npucc: clock-controller@9910000 {
compatible = "qcom,sm8150-npucc", "syscon";
reg = <0x9910000 0x10000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_gdsc-supply = <&npu_core_gdsc>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>,
<&gcc GCC_NPU_GPLL0_CLK_SRC>, <&gcc GCC_NPU_AXI_CLK>;
clock-names = "bi_tcxo", "gcc_npu_gpll0_div_clk_src",
"gcc_npu_gpll0_clk_src", "gcc_npu_axi_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
videocc: clock-controller@ab00000 {
compatible = "qcom,sm8150-videocc", "syscon";
reg = <0xab00000 0x10000>;
reg-names = "cc_base";
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
clock-names = "cfg_ahb_clk", "bi_tcxo";
#clock-cells = <1>;
#reset-cells = <1>;
};
camcc: clock-controller@ad00000 {
compatible = "qcom,sc8180x-camcc", "syscon";
reg = <0xad00000 0x20000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
clock-names = "cfg_ahb_clk", "bi_tcxo", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
dispcc: clock-controller@af00000 {
compatible = "qcom,sc8180x-dispcc", "syscon";
reg = <0xaf00000 0x20000>;
reg-names = "cc_base";
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
clocks = <&gcc GCC_DISP_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
clock-names = "cfg_ahb_clk", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
apsscc: syscon@182a0000 {
compatible = "syscon";
reg = <0x182a0000 0x1c>;
};
mccc: syscon@90b0000 {
compatible = "syscon";
reg = <0x90b0000 0x54>;
};
debugcc: debug-clock-controller@0 {
compatible = "qcom,sc8180x-debugcc";
qcom,gcc = <&gcc>;
qcom,videocc = <&videocc>;
qcom,camcc = <&camcc>;
qcom,dispcc = <&dispcc>;
qcom,npucc = <&npucc>;
qcom,gpucc = <&gpucc>;
qcom,apsscc = <&apsscc>;
qcom,mccc = <&mccc>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&camcc 0>,
<&dispcc 0>,
<&gcc 0>,
<&gpucc 0>,
<&npucc 0>,
<&videocc 0>;
clock-names = "xo_clk_src",
"camcc",
"dispcc",
"gcc",
"gpucc",
"npucc",
"videocc";
#clock-cells = <1>;
};
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0x18323000 0x1400>, <0x18325800 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <2>;
};
config_noc: interconnect@1500000 {
reg = <0x1500000 0x7400>;
compatible = "qcom,sc8180x-config-noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1620000 {
reg = <0x1620000 0x21400>;
compatible = "qcom,sc8180x-system-noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
ipa_virt: interconnect@0 {
compatible = "qcom,sc8180x-ipa-virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
camnoc_virt: interconnect@1 {
compatible = "qcom,sc8180x-camnoc-virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
reg = <0x16E0000 0x1A080>;
compatible = "qcom,sc8180x-aggre1-noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_CARD_2_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_MP_AXI_CLK>;
};
aggre2_noc: interconnect@1700000 {
reg = <0x1700000 0x3A080>;
compatible = "qcom,sc8180x-aggre2-noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
compute_noc: interconnect@1716000 {
reg = <0x1716008 0x10>;
compatible = "qcom,sc8180x-compute-noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@1740000 {
reg = <0x1740000 0x1C100>;
compatible = "qcom,sc8180x-mmss-noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos", "disp";
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
};
dc_noc: interconnect@9160000 {
reg = <0x9160000 0x3200>;
compatible = "qcom,sc8180x-dc-noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
gem_noc: interconnect@9680000 {
reg = <0x9680000 0x58200>;
compatible = "qcom,sc8180x-gem-noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos", "disp";
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>;
};
mc_virt: interconnect@2 {
compatible = "qcom,sc8180x-mc-virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos", "disp";
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
};
thermal_zones: thermal-zones {
};
sram@c3f0000 {
compatible = "qcom,rpmh-stats-v3";
reg = <0xc3f0000 0x400>;
qcom,qmp = <&aoss_qmp>;
ss-name = "modem", "adsp", "adsp_island",
"cdsp", "slpi", "slpi_island",
"apss";
};
spmi_bus: qcom,spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0x1000>,
<0xc600000 0x2000000>,
<0xe600000 0x100000>,
<0xe700000 0xa0000>,
<0xc40a000 0x700>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
cell-index = <0>;
qcom,channel = <0>;
qcom,ee = <0>;
};
tcsr_mutex_block: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x20000>;
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_block 0 0x1000>;
#hwlock-cells = <1>;
};
smem: qcom,smem@8600000 {
compatible = "qcom,smem";
memory-region = <&smem_region>;
hwlocks = <&tcsr_mutex 3>;
};
apcs: syscon@17c0000c {
compatible = "syscon";
reg = <0x17c0000c 0x4>;
};
apss_shared: mailbox@17c00000 {
compatible = "qcom,sm8150-apss-shared";
reg = <0x17c00000 0x1000>;
#mbox-cells = <1>;
};
qcom,secure-buffer {
compatible = "qcom,secure-buffer";
qcom,vmid-cp-camera-preview-ro;
};
qcom,mem-buf {
compatible = "qcom,mem-buf";
qcom,mem-buf-capabilities = "supplier";
qcom,vmid = <3>;
};
qcom,mem-buf-msgq {
compatible = "qcom,mem-buf-msgq";
};
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sm8150-aoss-qmp";
reg = <0x0c300000 0x400>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
#power-domain-cells = <1>;
};
qmp_aop: qcom,qmp-aop@c300000 {
compatible = "qcom,qmp-mbox";
qcom,qmp = <&aoss_qmp>;
label = "aop";
#mbox-cells = <1>;
};
sp_scsr_block: syscon@1880000 {
compatible = "syscon";
reg = <0x1880000 0x10000>;
};
intsp: qcom,qsee_irq {
compatible = "qcom,sm8150-qsee-irq";
syscon = <&sp_scsr_block>;
interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>,
<0 349 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sp_ipc0",
"sp_ipc1";
interrupt-controller;
#interrupt-cells = <3>;
};
qcom,qsee_irq_bridge {
compatible = "qcom,qsee-ipc-irq-bridge";
qcom,qsee-ipc-irq-spss {
qcom,dev-name = "qsee_ipc_irq_spss";
label = "spss";
interrupt-parent = <&intsp>;
interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>;
};
};
qcom,glinkpkt {
compatible = "qcom,glinkpkt";
qcom,glinkpkt-apr-apps2 {
qcom,glinkpkt-edge = "adsp";
qcom,glinkpkt-ch-name = "apr_apps2";
qcom,glinkpkt-dev-name = "apr_apps2";
};
};
qcom,smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 0 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 0 6>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
cdsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
cdsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
wdog: qcom,wdt@17c10000 {
compatible = "qcom,msm-watchdog";
reg = <0x17c10000 0x1000>;
reg-names = "wdt-base";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
cache-controller@9200000 {
compatible = "qcom,sdmshrike-llcc";
reg = <0x9200000 0x3d0000>, <0x9600000 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
cap-based-alloc-and-pwr-collapse;
};
qcom,chd {
compatible = "qcom,core-hang-detect";
label = "core";
qcom,chd-percpu-info = <&CPU0 0x18000058 0x18000060>,
<&CPU1 0x18010058 0x18010060>,
<&CPU2 0x18020058 0x18020060>,
<&CPU3 0x18030058 0x18030060>,
<&CPU4 0x18040058 0x18040060>,
<&CPU5 0x18050058 0x18050060>,
<&CPU6 0x18060058 0x18060060>,
<&CPU7 0x18070058 0x18070060>;
};
cpu_pmu: cpu-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
llcc_pmu: llcc-pmu@90cc000 {
compatible = "qcom,llcc-pmu-ver2";
reg = <0x090cc000 0x300>;
reg-names = "lagg-base";
};
qcom,pmu {
compatible = "qcom,pmu";
qcom,pmu-events-tbl =
< 0x0008 0xFF 0xFF 0xFF >,
< 0x0011 0xFF 0xFF 0xFF >,
< 0x0017 0xFF 0xFF 0xFF >,
< 0x002A 0xFF 0xFF 0xFF >,
< 0x1000 0xFF 0xFF 0xFF >;
};
ddr_freq_table: ddr-freq-table {
qcom,freq-tbl =
< 200000 >,
< 300000 >,
< 451000 >,
< 547000 >,
< 681000 >,
< 768000 >,
< 1017000 >,
< 1296000 >,
< 1555000 >,
< 1804000 >,
< 2092000 >;
};
llcc_freq_table: llcc-freq-table {
qcom,freq-tbl =
< 150000 >,
< 200000 >,
< 403000 >,
< 533000 >,
< 666000 >,
< 777000 >;
};
qcom_dcvs: qcom,dcvs {
compatible = "qcom,dcvs";
#address-cells = <1>;
#size-cells = <1>;
ranges;
qcom_ddr_dcvs_hw: ddr {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <0>;
qcom,bus-width = <4>;
qcom,freq-tbl = <&ddr_freq_table>;
ddr_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
interconnects = <&mc_virt MASTER_LLCC
&mc_virt SLAVE_EBI1>;
};
};
qcom_llcc_dcvs_hw: llcc {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <1>;
qcom,bus-width = <16>;
qcom,freq-tbl = <&llcc_freq_table>;
llcc_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
interconnects = <&gem_noc MASTER_APPSS_PROC
&gem_noc SLAVE_LLCC>;
};
};
qcom_l3_dcvs_hw: l3 {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <2>;
qcom,bus-width = <32>;
qcom,ftbl-row-size = <0x20>;
reg = <0x18321000 0x4000>, <0x18321110 0x500>;
reg-names = "l3-base", "l3tbl-base";
l3_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
qcom,shared-offset = <0x0920>;
};
};
};
qcom_memlat: qcom,memlat {
compatible = "qcom,memlat";
ddr {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
qcom,sampling-path = <&ddr_dcvs_sp>;
qcom,miss-ev = <0x1000>;
silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,cpufreq-memfreq-tbl =
< 300000 200000 >,
< 576000 451000 >,
< 672000 768000 >,
< 864000 1017000 >,
< 1171200 1555800 >,
< 1267200 1804000 >;
qcom,sampling-enabled;
};
gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cpufreq-memfreq-tbl =
< 300000 200000 >,
< 576000 451000 >,
< 768000 768000 >,
< 960000 1017000 >,
< 1248000 1555000 >,
< 1593600 1804000 >,
< 1689600 1804000 >;
qcom,sampling-enabled;
};
gold-compute {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cpufreq-memfreq-tbl =
< 1593600 200000 >,
< 2016000 1017000 >,
< 2054400 2092000 >;
qcom,sampling-enabled;
qcom,compute-mon;
};
};
llcc {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
qcom,sampling-path = <&llcc_dcvs_sp>;
qcom,miss-ev = <0x2A>;
silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,cpufreq-memfreq-tbl =
< 300000 150000 >,
< 576000 200000 >,
< 672000 403000 >,
< 864000 533000 >,
< 1171200 666000 >,
< 1267200 777000 >;
qcom,sampling-enabled;
};
gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cpufreq-memfreq-tbl =
< 300000 200000 >,
< 576000 451000 >,
< 768000 768000 >,
< 960000 1017000 >,
< 1248000 1555000 >,
< 1593600 1804000 >,
< 1689600 2092000 >;
qcom,sampling-enabled;
};
};
l3 {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_l3_dcvs_hw>;
qcom,sampling-path = <&l3_dcvs_sp>;
qcom,miss-ev = <0x17>;
silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,cpufreq-memfreq-tbl =
< 300000 300000 >,
< 576000 576000 >,
< 672000 768000 >,
< 864000 960000 >,
< 1171200 1228800 >,
< 1267200 1344000 >,
< 1766400 1651200 >;
qcom,sampling-enabled;
};
gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cpufreq-memfreq-tbl =
< 300000 300000 >,
< 576000 576000 >,
< 768000 768000 >,
< 960000 960000 >,
< 1248000 1228800 >,
< 1593600 1344000 >,
< 2841600 1651200 >;
qcom,sampling-enabled;
};
};
};
bwmon_llcc: qcom,bwmon-llcc@90b6400 {
compatible = "qcom,bwmon4";
reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,count-unit = <0x10000>;
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
};
bwmon_ddr: qcom,bwmon-ddr@90cd000 {
compatible = "qcom,bwmon5";
reg = <0x90cd000 0x1000>;
reg-names = "base";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
qcom,hw-timer-hz = <19200000>;
qcom,count-unit = <0x10000>;
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
};
adsp_pas: remoteproc-adsp@17300000 {
compatible = "qcom,sdmshrike-adsp-pas";
reg = <0x17300000 0x00100>;
status = "ok";
cx-supply = <&VDD_CX_LEVEL>;
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
reg-names = "cx";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,qmp = <&aoss_qmp>;
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
interconnect-names = "crypto_ddr";
memory-region = <&rproc_adsp_mem>;
/* Inputs from ssc */
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<&adsp_smp2p_in 0 0>,
<&adsp_smp2p_in 2 0>,
<&adsp_smp2p_in 1 0>,
<&adsp_smp2p_in 3 0>;
interrupt-names = "wdog",
"fatal",
"handover",
"ready",
"stop-ack";
/* Outputs to turing */
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink_edge: glink-edge {
qcom,remote-pid = <2>;
transport = "smem";
mboxes = <&apss_shared 8>;
mbox-names = "adsp_smem";
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
label = "adsp";
qcom,glink-label = "lpass";
cpu-affinity = <1 2>;
qcom,adsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,apr_tal_rpmsg {
qcom,glink-channels = "apr_audio_svc";
qcom,intents = <0x200 20>;
};
qcom,msm_fastrpc_rpmsg {
compatible = "qcom,msm-fastrpc-rpmsg";
qcom,glink-channels = "fastrpcglink-apps-dsp";
qcom,intents = <0x64 64>;
};
qcom,adsp_glink_ssr {
qcom,glink-channels = "glink_ssr";
};
};
};
cdsp_pas: remoteproc-cdsp@0x8300000 {
compatible = "qcom,sm8150-cdsp-pas";
reg = <0x8300000 0x100000>;
status = "ok";
cx-supply = <&VDD_CX_LEVEL>;
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
reg-names = "cx";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,qmp = <&aoss_qmp>;
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
interconnect-names = "crypto_ddr";
memory-region = <&rproc_cdsp_mem>;
/* Inputs from ssc */
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 0 0>,
<&cdsp_smp2p_in 2 0>,
<&cdsp_smp2p_in 1 0>,
<&cdsp_smp2p_in 3 0>,
<&cdsp_smp2p_in 7 0>;
interrupt-names = "wdog",
"fatal",
"handover",
"ready",
"stop-ack",
"shutdown-ack";
/* Outputs to turing */
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
qcom,remote-pid = <5>;
transport = "smem";
mboxes = <&apss_shared 4>;
mbox-names = "cdsp_smem";
interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
label = "cdsp";
qcom,glink-label = "cdsp";
qcom,cdsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,msm_fastrpc_rpmsg {
compatible = "qcom,msm-fastrpc-rpmsg";
qcom,glink-channels = "fastrpcglink-apps-dsp";
qcom,intents = <0x64 64>;
};
qcom,msm_cdsprm_rpmsg {
compatible = "qcom,msm-cdsprm-rpmsg";
qcom,glink-channels = "cdsprmglink-apps-dsp";
qcom,intents = <0x20 12>;
};
qcom,cdsp_glink_ssr {
qcom,glink-channels = "glink_ssr";
};
};
};
sdhc2_opp_table: sdhc2-opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-peak-kBps = <1600000 280000>;
opp-avg-kBps = <50000 0>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
opp-peak-kBps = <5600000 1500000>;
opp-avg-kBps = <104000 0>;
};
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x8804000 0x1000>;
reg-names = "hc_mem";
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface", "core";
bus-width = <4>;
qcom,restore-after-cx-collapse;
iommus = <&apps_smmu 0x06A0 0x0>;
qcom,iommu-dma = "fastmap";
dma-coherent;
interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
operating-points-v2 = <&sdhc2_opp_table>;
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
qcom,devfreq,freq-table = <50000000 200000000>;
status = "disabled";
qos0 {
mask = <0x0f>;
vote = <70>;
};
qos1 {
mask = <0xf0>;
vote = <70>;
};
};
ufsphy_mem: ufsphy_mem@1d87000 {
reg = <0x1d87000 0xe00>; /* PHY regs */
reg-names = "phy_mem";
#phy-cells = <0>;
lanes-per-direction = <2>;
clock-names = "ref_clk_src",
"ref_clk",
"ref_aux_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_MEM_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
resets = <&ufshc_mem 0>;
status = "disabled";
};
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>,
<0x1d90000 0x8000>;
reg-names = "ufs_mem", "ufs_ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
#reset-cells = <1>;
lanes-per-direction = <2>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<37500000 300000000>,
<0 0>,
<0 0>,
<37500000 300000000>,
<37500000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
interconnects =
<&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC
&config_noc SLAVE_UFS_MEM_0_CFG>;
interconnect-names = "ufs-ddr", "cpu-ufs";
qcom,ufs-bus-bw,name = "ufshc_mem";
qcom,ufs-bus-bw,num-cases = <26>;
qcom,ufs-bus-bw,num-paths = <2>;
qcom,ufs-bus-bw,vectors-KBps =
/*
* During HS G3 UFS runs at nominal voltage corner, vote
* higher bandwidth to push other buses in the data path
* to run at nominal to achieve max throughput.
* 4GBps pushes BIMC to run at nominal.
* 200MBps pushes CNOC to run at nominal.
* Vote for half of this bandwidth for HS G3 1-lane.
* For max bandwidth, vote high enough to push the buses
* to run in turbo voltage corner.
*/
<0 0>, <0 0>, /* No vote */
<922 0>, <1000 0>, /* PWM G1 */
<1844 0>, <1000 0>, /* PWM G2 */
<3688 0>, <1000 0>, /* PWM G3 */
<7376 0>, <1000 0>, /* PWM G4 */
<1844 0>, <1000 0>, /* PWM G1 L2 */
<3688 0>, <1000 0>, /* PWM G2 L2 */
<7376 0>, <1000 0>, /* PWM G3 L2 */
<14752 0>, <1000 0>, /* PWM G4 L2 */
<127796 0>, <1000 0>, /* HS G1 RA */
<255591 0>, <1000 0>, /* HS G2 RA */
<2097152 0>, <102400 0>, /* HS G3 RA */
<4194304 0>, <204800 0>, /* HS G4 RA */
<255591 0>, <1000 0>, /* HS G1 RA L2 */
<511181 0>, <1000 0>, /* HS G2 RA L2 */
<4194304 0>, <204800 0>, /* HS G3 RA L2 */
<8388608 0>, <409600 0>, /* HS G4 RA L2 */
<149422 0>, <1000 0>, /* HS G1 RB */
<298189 0>, <1000 0>, /* HS G2 RB */
<2097152 0>, <102400 0>, /* HS G3 RB */
<4194304 0>, <204800 0>, /* HS G4 RB */
<298189 0>, <1000 0>, /* HS G1 RB L2 */
<596378 0>, <1000 0>, /* HS G2 RB L2 */
/* As UFS working in HS G3 RB L2 mode, aggregated
* bandwidth (AB) should take care of providing
* optimum throughput requested. However, as tested,
* in order to scale up CNOC clock, instantaneous
* bindwidth (IB) needs to be given a proper value too.
*/
<4194304 0>, <204800 409600>, /* HS G3 RB L2 */
<8388608 0>, <409600 409600>, /* HS G4 RB L2 */
<7643136 0>, <307200 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
"MAX";
reset-gpios = <&tlmm 190 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
iommus = <&apps_smmu 0x300 0x0>;
qcom,iommu-dma = "fastmap";
dma-coherent;
status = "disabled";
qos0 {
mask = <0xf0>;
vote = <44>;
};
qos1 {
mask = <0x0f>;
vote = <44>;
};
};
ufs2phy_mem: ufsphy2_mem@1d67000 {
reg = <0x1d67000 0xe00>; /* PHY regs */
reg-names = "phy_mem";
#phy-cells = <0>;
lanes-per-direction = <2>;
clock-names = "ref_clk_src",
"ref_clk",
"ref_aux_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_CARD_CLKREF_CLK>,
<&gcc GCC_UFS_CARD_2_PHY_AUX_CLK>;
resets = <&ufshc2_mem 0>;
status = "disabled";
};
ufshc2_mem: ufshc2@1d64000 {
compatible = "qcom,ufshc";
reg = <0x1d64000 0x3000>;
reg-names = "ufs_mem";
interrupts = <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs2phy_mem>;
phy-names = "ufsphy";
#reset-cells = <1>;
lanes-per-direction = <2>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_CARD_2_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_CARD_2_AXI_CLK>,
<&gcc GCC_UFS_CARD_2_AHB_CLK>,
<&gcc GCC_UFS_CARD_2_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_CARD_2_ICE_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_CARD_2_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_CARD_2_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_CARD_2_RX_SYMBOL_1_CLK>;
freq-table-hz =
<37500000 300000000>,
<0 0>,
<0 0>,
<37500000 300000000>,
<37500000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
interconnects =
<&aggre1_noc MASTER_UFS_GEN4 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC
&config_noc SLAVE_UFS_MEM_1_CFG>;
interconnect-names = "ufs-ddr", "cpu-ufs";
qcom,ufs-bus-bw,name = "ufshc2_mem";
qcom,ufs-bus-bw,num-cases = <26>;
qcom,ufs-bus-bw,num-paths = <2>;
qcom,ufs-bus-bw,vectors-KBps =
/*
* During HS G3 UFS runs at nominal voltage corner, vote
* higher bandwidth to push other buses in the data path
* to run at nominal to achieve max throughput.
* 4GBps pushes BIMC to run at nominal.
* 200MBps pushes CNOC to run at nominal.
* Vote for half of this bandwidth for HS G3 1-lane.
* For max bandwidth, vote high enough to push the buses
* to run in turbo voltage corner.
*/
<0 0>, <0 0>, /* No vote */
<922 0>, <1000 0>, /* PWM G1 */
<1844 0>, <1000 0>, /* PWM G2 */
<3688 0>, <1000 0>, /* PWM G3 */
<7376 0>, <1000 0>, /* PWM G4 */
<1844 0>, <1000 0>, /* PWM G1 L2 */
<3688 0>, <1000 0>, /* PWM G2 L2 */
<7376 0>, <1000 0>, /* PWM G3 L2 */
<14752 0>, <1000 0>, /* PWM G4 L2 */
<127796 0>, <1000 0>, /* HS G1 RA */
<255591 0>, <1000 0>, /* HS G2 RA */
<2097152 0>, <102400 0>, /* HS G3 RA */
<4194304 0>, <204800 0>, /* HS G4 RA */
<255591 0>, <1000 0>, /* HS G1 RA L2 */
<511181 0>, <1000 0>, /* HS G2 RA L2 */
<4194304 0>, <204800 0>, /* HS G3 RA L2 */
<8388608 0>, <409600 0>, /* HS G4 RA L2 */
<149422 0>, <1000 0>, /* HS G1 RB */
<298189 0>, <1000 0>, /* HS G2 RB */
<2097152 0>, <102400 0>, /* HS G3 RB */
<4194304 0>, <204800 0>, /* HS G4 RB */
<298189 0>, <1000 0>, /* HS G1 RB L2 */
<596378 0>, <1000 0>, /* HS G2 RB L2 */
/* As UFS working in HS G3 RB L2 mode, aggregated
* bandwidth (AB) should take care of providing
* optimum throughput requested. However, as tested,
* in order to scale up CNOC clock, instantaneous
* bindwidth (IB) needs to be given a proper value too.
*/
<4194304 0>, <204800 409600>, /* HS G3 RB L2 */
<8388608 0>, <409600 409600>, /* HS G4 RB L2 */
<7643136 0>, <307200 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
"MAX";
reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_UFS_CARD_2_BCR>;
reset-names = "rst";
iommus = <&apps_smmu 0x0 0x0>;
qcom,iommu-dma = "fastmap";
dma-coherent;
secondary-storage;
status = "disabled";
/* PM QoS */
qos0 {
mask = <0xf0>;
vote = <44>;
};
qos1 {
mask = <0x0f>;
vote = <44>;
};
};
qtee_shmbridge {
compatible = "qcom,tee-shared-memory-bridge";
qcom,disable-shmbridge-support;
};
qcom_qseecom: qseecom@87900000 {
compatible = "qcom,qseecom";
reg = <0x87900000 0x2200000>;
reg-names = "secapp-region";
memory-region = <&qseecom_mem>;
qcom,hlos-num-ce-hw-instances = <1>;
qcom,hlos-ce-hw-instance = <0>;
qcom,qsee-ce-hw-instance = <0>;
qcom,disk-encrypt-pipe-pair = <2>;
qcom,support-fde;
qcom,no-clock-support;
qcom,fde-key-size;
qcom,appsbl-qseecom-support;
qcom,commonlib64-loaded-by-uefi;
qcom,qsee-reentrancy-support = <2>;
};
qcom_cedev: qcedev@1de0000 {
compatible = "qcom,qcedev";
reg = <0x1de0000 0x20000>,
<0x1dc4000 0x28000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
qcom,bam-pipe-pair = <2>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,ce-hw-shared;
qcom,bam-ee = <0>;
qcom,smmu-s1-enable;
qcom,no-clock-support;
interconnect-names = "data_path";
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
iommus = <&apps_smmu 0x0512 0x0000>,
<&apps_smmu 0x051C 0x0005>,
<&apps_smmu 0x051D 0x0005>,
<&apps_smmu 0x051F 0x0000>;
qcom,iommu-dma = "atomic";
dma-coherent;
qcom_cedev_ns_cb {
compatible = "qcom,qcedev,context-bank";
label = "ns_context";
iommus = <&apps_smmu 0x0504 0x0013>,
<&apps_smmu 0x0508 0x0001>,
<&apps_smmu 0x0514 0x0013>,
<&apps_smmu 0x0518 0x0005>;
dma-coherent;
};
qcom_cedev_s_cb {
compatible = "qcom,qcedev,context-bank";
label = "secure_context";
iommus = <&apps_smmu 0x0513 0x0000>,
<&apps_smmu 0x051E 0x0000>;
qcom,iommu-vmid = <0x9>;
qcom,secure-context-bank;
dma-coherent;
};
};
qcom_rng: qrng@793000 {
compatible = "qcom,msm-rng";
reg = <0x793000 0x1000>;
qcom,no-qrng-config;
interconnect-names = "data_path";
interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_PRNG>;
clock-names = "km_clk_src";
clocks = <&gcc GCC_PRNG_AHB_CLK>;
};
qcom_smcinvoke: smcinvoke@87900000 {
compatible = "qcom,smcinvoke";
reg = <0x87900000 0x2200000>;
reg-names = "secapp-region";
};
qcom_tzlog: tz-log@146bf720 {
compatible = "qcom,tz-log";
reg = <0x146bf720 0x3000>;
qcom,hyplog-enabled;
hyplog-address-offset = <0x410>;
hyplog-size-offset = <0x414>;
};
qcom,sps {
compatible = "qcom,msm-sps-4k";
qcom,pipe-attr-ee;
};
kryo-erp {
compatible = "arm,arm64-kryo-cpu-erp";
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "l1-l2-faultirq",
"l1-l2-errirq",
"l3-scu-errirq",
"l3-scu-faultirq";
};
qcom,msm-cdsp-loader {
compatible = "qcom,cdsp-loader";
qcom,proc-img-to-load = "cdsp";
qcom,rproc-handle = <&cdsp_pas>;
};
qcom,msm-adsprpc-mem {
compatible = "qcom,msm-adsprpc-mem-region";
memory-region = <&adsp_mem>;
};
msm_fastrpc: qcom,msm_fastrpc {
compatible = "qcom,msm-fastrpc-compute";
qcom,fastrpc-adsp-audio-pdr;
qcom,rpc-latency-us = <235>;
qcom,adsp-remoteheap-vmid = <3 5 6>;
qcom,msm_fastrpc_compute_cb1 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x1001 0x0460>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
};
qcom,msm_fastrpc_compute_cb2 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x1002 0x0460>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
};
qcom,msm_fastrpc_compute_cb3 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x1003 0x0460>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
};
qcom,msm_fastrpc_compute_cb4 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x1004 0x0460>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
};
qcom,msm_fastrpc_compute_cb5 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x1005 0x0460>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
};
qcom,msm_fastrpc_compute_cb6 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x1006 0x0460>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
};
qcom,msm_fastrpc_compute_cb7 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x1007 0x0460>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
};
qcom,msm_fastrpc_compute_cb8 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x1008 0x0460>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
};
qcom,msm_fastrpc_compute_cb9 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
qcom,secure-context-bank;
iommus = <&apps_smmu 0x1009 0x0460>;
qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
};
qcom,msm_fastrpc_compute_cb10 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&apps_smmu 0x1b23 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
};
qcom,msm_fastrpc_compute_cb11 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&apps_smmu 0x1b24 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
};
qcom,msm_fastrpc_compute_cb12 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&apps_smmu 0x1b25 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable";
dma-coherent;
};
};
msm_gpu: qcom,kgsl-3d0@2c00000 { };
google,debug-kinfo {
compatible = "google,debug-kinfo";
memory-region = <&kinfo_mem>;
};
};
&firmware {
qcom_scm {
compatible = "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
};
};
#include "sdmshrike-pinctrl.dtsi"
#include "sa8195-regulator.dtsi"
#include "sdmshrike-dma-heaps.dtsi"
#include "sm8150-slpi-pinctrl.dtsi"
#include "sa8195-gdsc.dtsi"
#include "msm-arm-smmu-sdmshrike.dtsi"
#include "sdmshrike-debug.dtsi"
#include "sa8195-usb.dtsi"
#include "sm8150-npu.dtsi"
&slpi_tlmm {
status = "ok";
};
&emac_gdsc {
status = "ok";
};
&pcie_0_gdsc {
qcom,support-hw-trigger;
status = "ok";
};
&pcie_1_gdsc {
qcom,support-hw-trigger;
status = "ok";
};
&pcie_2_gdsc {
qcom,support-hw-trigger;
status = "ok";
};
&pcie_3_gdsc {
qcom,support-hw-trigger;
status = "ok";
};
&ufs_card_2_gdsc {
status = "ok";
};
&ufs_card_gdsc {
status = "ok";
};
&ufs_phy_gdsc {
status = "ok";
};
&usb30_mp_gdsc {
status = "ok";
};
&usb30_prim_gdsc {
status = "ok";
};
&usb30_sec_gdsc {
status = "ok";
};
&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
status = "ok";
};
&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
status = "ok";
};
&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
status = "ok";
};
&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
status = "ok";
};
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
status = "ok";
};
&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
status = "ok";
};
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
status = "ok";
};
&hlos1_vote_turing_mmu_tbu0_gdsc {
status = "ok";
};
&hlos1_vote_turing_mmu_tbu1_gdsc {
status = "ok";
};
&bps_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MMCX_LEVEL>;
qcom,support-hw-trigger;
status = "ok";
};
&ife_0_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MMCX_LEVEL>;
status = "ok";
};
&ife_1_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MMCX_LEVEL>;
status = "ok";
};
&ife_2_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MMCX_LEVEL>;
status = "ok";
};
&ife_3_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MMCX_LEVEL>;
status = "ok";
};
&ipe_0_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MMCX_LEVEL>;
qcom,support-hw-trigger;
status = "ok";
};
&ipe_1_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MMCX_LEVEL>;
qcom,support-hw-trigger;
status = "ok";
};
&titan_top_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MMCX_LEVEL>;
status = "ok";
};
&mdss_core_gdsc {
clocks = <&gcc GCC_DISP_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MMCX_LEVEL>;
qcom,support-hw-trigger;
status = "ok";
};
&gpu_cx_gdsc {
status = "ok";
};
&gpu_gx_gdsc {
parent-supply = <&VDD_GFX_LEVEL>;
status = "ok";
};
&npu_core_gdsc {
clocks = <&gcc GCC_NPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
status = "ok";
};
&mvs0_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MMCX_LEVEL>;
qcom,support-hw-trigger;
status = "ok";
};
&mvs1_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MMCX_LEVEL>;
qcom,support-hw-trigger;
status = "ok";
};
&mvsc_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MMCX_LEVEL>;
status = "ok";
};
#include "sa8195-thermal.dtsi"
#include "sa8195-qupv3.dtsi"
#include "sa8195-ssc-qupv3.dtsi"
&qupv3_se12_2uart {
status = "ok";
};
&qupv3_se17_4uart {
status = "ok";
};
&qupv3_se9_2uart {
status = "ok";
};
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