mirror of
https://github.com/oplus-giulia-dev/android_kernel_oneplus_sm8650-devicetrees
synced 2025-11-04 06:44:04 +08:00
58ab816eb3
Add interconnect property for "qup-core", "qup-config", "qup-ddr" path for SM6150 target. Change-Id: Ib76283b83f40e7a2332714eb7fe2ab4477a035fa
383 lines
12 KiB
Plaintext
383 lines
12 KiB
Plaintext
&soc {
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/*
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* QUPv3 North & South Instances
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* North 0 : SE 4
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* North 1 : SE 5
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* North 2 : SE 6
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* North 3 : SE 7
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* South 0 : SE 0
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* South 1 : SE 1
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* South 2 : SE 2
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* South 3 : SE 3
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*/
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gpi_dma0: qcom,gpi-dma@800000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x800000 0x60000>;
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reg-names = "gpi-top";
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <8>;
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qcom,gpii-mask = <0x0f>;
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qcom,ev-factor = <2>;
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iommus = <&apps_smmu 0x00d6 0x0>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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status = "disabled";
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};
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/* QUPv3 South Instances */
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qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x8c0000 0x6000>;
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#address-cells = <1>;
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#size-cells = <1>;
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iommus = <&apps_smmu 0xc3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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ranges;
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status = "ok";
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/* Debug UART Instance for CDP/MTP platform */
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/* Ported */
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qupv3_se0_2uart: qcom,qup_uart@0x880000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x880000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_2uart_active>;
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pinctrl-1 = <&qupv3_se0_2uart_sleep>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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status = "ok";
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};
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/* I2C */
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qupv3_se1_i2c: i2c@884000 {
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compatible = "qcom,i2c-geni";
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reg = <0x884000 0x4000>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_i2c_active>;
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pinctrl-1 = <&qupv3_se1_i2c_sleep>;
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status = "disabled";
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};
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qupv3_se2_i2c: i2c@888000 {
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compatible = "qcom,i2c-geni";
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reg = <0x888000 0x4000>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_i2c_active>;
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pinctrl-1 = <&qupv3_se2_i2c_sleep>;
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status = "disabled";
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};
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qupv3_se3_i2c: i2c@88c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x88c000 0x4000>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_i2c_active>;
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pinctrl-1 = <&qupv3_se3_i2c_sleep>;
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status = "disabled";
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};
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/* SPI */
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qupv3_se2_spi: spi@888000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x888000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_spi_active>;
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pinctrl-1 = <&qupv3_se2_spi_sleep>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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};
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gpi_dma1: qcom,gpi-dma@a00000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0xa00000 0x60000>;
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reg-names = "gpi-top";
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interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <8>;
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qcom,ev-factor = <2>;
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qcom,gpii-mask = <0x0f>;
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iommus = <&apps_smmu 0x0376 0x0>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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status = "ok";
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};
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/* QUPv3 North instances */
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qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0xac0000 0x6000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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iommus = <&apps_smmu 0x363 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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ranges;
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status = "ok";
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/* GNSS UART Instance for CDP/MTP platform */
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qupv3_se4_2uart: qcom,qup_uart@a80000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0xa80000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
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dmas = <&gpi_dma1 0 0 2 64 0>,
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<&gpi_dma1 1 0 2 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default","sleep";
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pinctrl-0 = <&qupv3_se4_2uart_active>;
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pinctrl-1 = <&qupv3_se4_2uart_sleep>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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/* I2C */
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qupv3_se4_i2c: i2c@a80000 {
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compatible = "qcom,i2c-geni";
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reg = <0xa80000 0x4000>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_i2c_active>;
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pinctrl-1 = <&qupv3_se4_i2c_sleep>;
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status = "disabled";
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};
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qupv3_se5_i2c: i2c@a84000 {
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compatible = "qcom,i2c-geni";
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reg = <0xa84000 0x4000>;
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interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_i2c_active>;
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pinctrl-1 = <&qupv3_se5_i2c_sleep>;
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status = "disabled";
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};
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qupv3_se6_i2c: i2c@a88000 {
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compatible = "qcom,i2c-geni";
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reg = <0xa88000 0x4000>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_i2c_active>;
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pinctrl-1 = <&qupv3_se6_i2c_sleep>;
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status = "disabled";
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};
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qupv3_se7_i2c: i2c@a8c000 {
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compatible = "qcom,i2c-geni";
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reg = <0xa8c000 0x4000>;
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interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se7_i2c_active>;
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pinctrl-1 = <&qupv3_se7_i2c_sleep>;
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status = "disabled";
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};
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/* SPI */
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qupv3_se4_spi: spi@a80000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xa80000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_spi_active>;
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pinctrl-1 = <&qupv3_se4_spi_sleep>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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qupv3_se6_spi: spi@a88000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xa88000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_spi_active>;
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pinctrl-1 = <&qupv3_se6_spi_sleep>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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qupv3_se7_spi: spi@a8c000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xa8c000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se7_spi_active>;
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pinctrl-1 = <&qupv3_se7_spi_sleep>;
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interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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/*
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* HS UART instances. HS UART usecases can be supported on these
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* instances only.
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*/
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qupv3_se7_4uart: qcom,qup_uart@0xa8c000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0xa8c000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
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<&aggre1_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "active", "sleep", "shutdown";
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pinctrl-0 = <&qupv3_se7_default_ctsrtsrx>,
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<&qupv3_se7_default_tx>;
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pinctrl-1 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>,
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<&qupv3_se7_tx>;
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pinctrl-2 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>,
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<&qupv3_se7_tx>;
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|
pinctrl-3 = <&qupv3_se7_default_ctsrtsrx>,
|
|
<&qupv3_se7_default_tx>;
|
|
interrupts-extended = <&intc GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&tlmm 13 0>;
|
|
qcom,wakeup-byte = <0xFD>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|