mirror of
https://github.com/oplus-giulia-dev/android_kernel_oneplus_sm8650-devicetrees
synced 2025-11-04 06:44:04 +08:00
316 lines
10 KiB
Plaintext
316 lines
10 KiB
Plaintext
&soc {
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/* QUPv3 SSC Instances */
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qupv3_2: qcom,qupv3_2_geni_se@626c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x626c0000 0x6000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&scc SCC_QUPV3_M_HCLK_CLK>,
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<&scc SCC_QUPV3_S_HCLK_CLK>;
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iommus = <&apps_smmu 0x1783 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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status = "ok";
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ssc_qup {
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compatible = "qcom,geni-se-ssc-qup";
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clock-names = "corex", "core2x";
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clocks = <&scc SCC_QUPV3_CORE_CLK>,
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<&scc SCC_QUPV3_2XCORE_CLK>;
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qcom,subsys-name = "lpass";
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status = "ok";
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};
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/* 2-Wire UART instance */
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qupv3_se8_2uart: qcom,qup_uart@62680000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x62680000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default","sleep";
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pinctrl-0 = <&qupv3_se8_2uart_tx_active>,
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<&qupv3_se8_2uart_rx_active>;
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pinctrl-1 = <&qupv3_se8_2uart_sleep>;
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interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
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qcom,ssr-enable;
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status = "disabled";
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};
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/* I2C */
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qupv3_se8_i2c: i2c@62680000 {
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compatible = "qcom,i2c-geni";
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reg = <0x62680000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se8_i2c_active>;
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pinctrl-1 = <&qupv3_se8_i2c_sleep>;
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qcom,ssr-enable;
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status = "disabled";
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};
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qupv3_se9_i2c: i2c@62684000 {
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compatible = "qcom,i2c-geni";
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reg = <0x62684000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE1_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se9_i2c_active>;
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pinctrl-1 = <&qupv3_se9_i2c_sleep>;
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qcom,ssr-enable;
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status = "disabled";
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};
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qupv3_se10_i2c: i2c@62688000 {
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compatible = "qcom,i2c-geni";
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reg = <0x62688000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se10_i2c_active>;
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pinctrl-1 = <&qupv3_se10_i2c_sleep>;
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qcom,ssr-enable;
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status = "disabled";
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};
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qupv3_se11_i2c: i2c@6268c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x6268c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE3_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se11_i2c_active>;
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pinctrl-1 = <&qupv3_se11_i2c_sleep>;
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qcom,ssr-enable;
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status = "disabled";
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};
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qupv3_se12_i2c: i2c@62690000 {
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compatible = "qcom,i2c-geni";
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reg = <0x62690000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE4_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se12_i2c_active>;
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pinctrl-1 = <&qupv3_se12_i2c_sleep>;
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qcom,ssr-enable;
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status = "disabled";
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};
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qupv3_se13_i2c: i2c@62694000 {
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compatible = "qcom,i2c-geni";
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reg = <0x62694000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE5_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se13_i2c_active>;
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pinctrl-1 = <&qupv3_se13_i2c_sleep>;
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qcom,ssr-enable;
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status = "disabled";
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};
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/* SPI */
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qupv3_se8_spi: spi@62680000 {
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compatible = "qcom,spi-geni";
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reg = <0x62680000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&scc SCC_QUPV3_SE0_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se8_spi_data_active>,
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<&qupv3_se8_spi_clk_active>,
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<&qupv3_se8_spi_cs_active>;
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pinctrl-1 = <&qupv3_se8_spi_sleep>;
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spi-max-frequency = <50000000>;
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qcom,disable-dma;
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qcom,ssr-enable;
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status = "disabled";
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};
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qupv3_se9_spi: spi@62684000 {
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compatible = "qcom,spi-geni";
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reg = <0x62684000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE1_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se9_spi_active>;
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pinctrl-1 = <&qupv3_se9_spi_sleep>;
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spi-max-frequency = <50000000>;
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qcom,disable-dma;
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qcom,ssr-enable;
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status = "disabled";
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};
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qupv3_se10_spi: spi@62688000 {
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compatible = "qcom,spi-geni";
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reg = <0x62688000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE2_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se10_spi_active>;
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pinctrl-1 = <&qupv3_se10_spi_sleep>;
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spi-max-frequency = <50000000>;
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qcom,disable-dma;
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qcom,ssr-enable;
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status = "disabled";
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};
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qupv3_se11_spi: spi@6268c000 {
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compatible = "qcom,spi-geni";
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reg = <0x6268c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE3_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se11_spi_data_active>,
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<&qupv3_se11_spi_ctrl_active>;
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pinctrl-1 = <&qupv3_se11_spi_sleep>;
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spi-max-frequency = <50000000>;
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qcom,disable-dma;
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qcom,ssr-enable;
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status = "disabled";
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};
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qupv3_se12_spi: spi@62690000 {
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compatible = "qcom,spi-geni";
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reg = <0x62690000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE4_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se12_spi_data_active>,
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<&qupv3_se12_spi_ctrl_active>;
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pinctrl-1 = <&qupv3_se12_spi_sleep>;
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spi-max-frequency = <50000000>;
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qcom,disable-dma;
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qcom,ssr-enable;
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status = "disabled";
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};
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qupv3_se13_spi: spi@62694000 {
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compatible = "qcom,spi-geni";
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reg = <0x62694000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&scc SCC_QUPV3_SE5_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>,
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<&system_noc MASTER_LPASS_ANOC &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se13_spi_data_active>,
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<&qupv3_se13_spi_ctrl_active>;
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pinctrl-1 = <&qupv3_se13_spi_sleep>;
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spi-max-frequency = <50000000>;
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qcom,disable-dma;
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qcom,ssr-enable;
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status = "disabled";
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};
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};
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};
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