mirror of
https://github.com/oplus-giulia-dev/android_kernel_oneplus_sm8650-devicetrees
synced 2025-11-04 06:44:04 +08:00
195 lines
3.7 KiB
Plaintext
195 lines
3.7 KiB
Plaintext
&soc {
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msm_npu: qcom,msm_npu@9800000 {
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compatible = "qcom,msm-npu";
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status = "ok";
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reg = <0x9800000 0x15000>,
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<0x9900000 0x10000>,
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<0x9960200 0x600>;
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reg-names = "tcm", "core", "bwmon";
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interrupts = <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq";
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iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>;
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memory-region = <&pil_npu_mem>;
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clocks = <&aoss_qmp>,
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<&gcc GCC_NPU_AT_CLK>,
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<&gcc GCC_NPU_TRIG_CLK>,
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<&npucc NPU_CC_ARMWIC_CORE_CLK>,
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<&npucc NPU_CC_CAL_DP_CLK>,
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<&npucc NPU_CC_CAL_DP_CDC_CLK>,
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<&npucc NPU_CC_CONF_NOC_AHB_CLK>,
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<&npucc NPU_CC_COMP_NOC_AXI_CLK>,
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<&npucc NPU_CC_NPU_CORE_CLK>,
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<&npucc NPU_CC_NPU_CORE_CTI_CLK>,
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<&npucc NPU_CC_NPU_CORE_APB_CLK>,
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<&npucc NPU_CC_NPU_CORE_ATB_CLK>,
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<&npucc NPU_CC_NPU_CPC_CLK>,
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<&npucc NPU_CC_NPU_CPC_TIMER_CLK>,
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<&npucc NPU_CC_QTIMER_CORE_CLK>,
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<&npucc NPU_CC_SLEEP_CLK>,
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<&npucc NPU_CC_BWMON_CLK>,
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<&npucc NPU_CC_PERF_CNT_CLK>,
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<&npucc NPU_CC_BTO_CORE_CLK>;
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clock-names = "qdss_clk",
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"at_clk",
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"trig_clk",
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"armwic_core_clk",
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"cal_dp_clk",
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"cal_dp_cdc_clk",
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"conf_noc_ahb_clk",
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"comp_noc_axi_clk",
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"npu_core_clk",
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"npu_core_cti_clk",
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"npu_core_apb_clk",
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"npu_core_atb_clk",
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"npu_cpc_clk",
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"npu_cpc_timer_clk",
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"qtimer_core_clk",
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"sleep_clk",
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"bwmon_clk",
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"perf_cnt_clk",
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"bto_core_clk";
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vdd-supply = <&npu_core_gdsc>;
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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qcom,proxy-reg-names ="vdd", "vdd_cx";
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qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
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mboxes = <&qmp_aop 0>;
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mbox-names = "aop";
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#cooling-cells = <2>;
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interconnects = <&compute_noc MASTER_NPU &compute_noc SLAVE_CDSP_MEM_NOC>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IMEM_CFG>;
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interconnect-names = "icc-npu-cdspmem", "icc-cpu-imemcfg";
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// qcom,npubw-dev = <&npu_npu_ddr_bw>;
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qcom,npu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,npu-pwrlevels";
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initial-pwrlevel = <4>;
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qcom,npu-pwrlevel@0 {
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reg = <0>;
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vreg = <1>;
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clk-freq = <0
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0
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0
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100000000
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300000000
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300000000
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19200000
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150000000
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100000000
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37500000
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19200000
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60000000
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100000000
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19200000
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19200000
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0
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19200000
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300000000
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19200000
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19200000>;
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};
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qcom,npu-pwrlevel@1 {
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reg = <1>;
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vreg = <2>;
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clk-freq = <0
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0
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0
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150000000
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350000000
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350000000
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37500000
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200000000
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150000000
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75000000
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19200000
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120000000
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150000000
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19200000
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19200000
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0
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19200000
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350000000
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19200000
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19200000>;
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};
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qcom,npu-pwrlevel@2 {
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reg = <2>;
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vreg = <3>;
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clk-freq = <0
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0
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0
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200000000
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400000000
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400000000
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37500000
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300000000
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200000000
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75000000
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19200000
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120000000
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200000000
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19200000
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19200000
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0
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19200000
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400000000
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19200000
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19200000>;
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};
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qcom,npu-pwrlevel@3 {
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reg = <3>;
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vreg = <4>;
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clk-freq = <0
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0
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0
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300000000
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600000000
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600000000
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75000000
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403000000
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300000000
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150000000
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19200000
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240000000
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300000000
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19200000
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19200000
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0
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19200000
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600000000
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19200000
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19200000>;
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};
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qcom,npu-pwrlevel@4 {
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reg = <4>;
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vreg = <6>;
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clk-freq = <0
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0
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0
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350000000
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715000000
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715000000
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75000000
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533000000
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350000000
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150000000
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19200000
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240000000
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350000000
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19200000
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19200000
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0
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19200000
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715000000
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19200000
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19200000>;
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};
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};
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};
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};
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