mirror of
https://github.com/oplus-giulia-dev/android_kernel_oneplus_sm8650-devicetrees
synced 2025-11-04 06:44:04 +08:00
356 lines
11 KiB
Plaintext
356 lines
11 KiB
Plaintext
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
|
|
#include <dt-bindings/phy/qcom,sm8150-qmp-usb3.h>
|
|
|
|
&soc {
|
|
/* Primary USB port related controller */
|
|
usb0: ssusb@a600000 {
|
|
compatible = "qcom,dwc-usb3-msm";
|
|
reg = <0xa600000 0x100000>;
|
|
reg-names = "core_base";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 9 IRQ_TYPE_EDGE_RISING>,
|
|
<&pdc 8 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "pwr_event_irq","dp_hs_phy_irq",
|
|
"dm_hs_phy_irq";
|
|
qcom,use-pdc-interrupts;
|
|
|
|
USB3_GDSC-supply = <&usb30_prim_gdsc>;
|
|
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
|
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
|
|
|
|
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
|
"utmi_clk", "sleep_clk";
|
|
|
|
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
|
reset-names = "core_reset";
|
|
|
|
qcom,core-clk-rate = <200000000>;
|
|
qcom,core-clk-rate-hs = <66666667>;
|
|
|
|
interconnect-names = "usb-ddr", "ddr-usb";
|
|
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
|
|
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
|
|
|
|
/*
|
|
* Establish dependency on smmu driver so that depopulate path of
|
|
* deferred probe doesn't run into existing bug in smmu driver.
|
|
*/
|
|
|
|
dummy-supply = <&apps_smmu>;
|
|
|
|
dwc3@a600000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0xa600000 0xcd00>;
|
|
iommus = <&apps_smmu 0x140 0x0>;
|
|
qcom,iommu-dma = "atomic";
|
|
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
|
|
snps,disable-clk-gating;
|
|
snps,has-lpm-erratum;
|
|
snps,hird-threshold = /bits/ 8 <0x0>;
|
|
snps,is-utmi-l1-suspend;
|
|
snps,usb2-gadget-lpm-disable;
|
|
tx-fifo-resize;
|
|
maximum-speed = "high-speed";
|
|
dr_mode = "otg";
|
|
usb-role-switch;
|
|
};
|
|
|
|
/*
|
|
qcom,usbbam@a704000 {
|
|
compatible = "qcom,usb-bam-msm";
|
|
reg = <0xa704000 0x17000>;
|
|
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
qcom,usb-bam-fifo-baseaddr = <0x146bb000>;
|
|
qcom,usb-bam-num-pipes = <4>;
|
|
qcom,disable-clk-gating;
|
|
qcom,usb-bam-override-threshold = <0x4001>;
|
|
qcom,usb-bam-max-mbps-highspeed = <400>;
|
|
qcom,usb-bam-max-mbps-superspeed = <3600>;
|
|
qcom,reset-bam-on-connect;
|
|
|
|
qcom,pipe0 {
|
|
label = "ssusb-qdss-in-0";
|
|
qcom,usb-bam-mem-type = <2>;
|
|
qcom,dir = <1>;
|
|
qcom,pipe-num = <0>;
|
|
qcom,peer-bam = <0>;
|
|
qcom,peer-bam-physical-address = <0x6064000>;
|
|
qcom,src-bam-pipe-index = <0>;
|
|
qcom,dst-bam-pipe-index = <0>;
|
|
qcom,data-fifo-offset = <0x0>;
|
|
qcom,data-fifo-size = <0x1800>;
|
|
qcom,descriptor-fifo-offset = <0x1800>;
|
|
qcom,descriptor-fifo-size = <0x800>;
|
|
};
|
|
};
|
|
*/
|
|
};
|
|
|
|
/* Primary USB port related High Speed PHY */
|
|
usb2_phy0: hsphy@88e2000 {
|
|
compatible = "qcom,usb-hsphy-snps-femto";
|
|
reg = <0x88e2000 0x110>,
|
|
<0x007801f8 0x4>;
|
|
reg-names = "hsusb_phy_base",
|
|
"phy_rcal_reg";
|
|
|
|
vdd-supply = <&L5A>;
|
|
vdda18-supply = <&L12A>;
|
|
vdda33-supply = <&L2A>;
|
|
qcom,vdd-voltage-level = <0 880000 880000>;
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
|
|
clock-names = "ref_clk_src", "ref_clk";
|
|
|
|
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
|
reset-names = "phy_reset";
|
|
qcom,param-override-seq = <0x43 0x70>;
|
|
qcom,rcal-mask = <0x1e00000>;
|
|
};
|
|
|
|
usb_nop_phy: usb_nop_phy {
|
|
compatible = "usb-nop-xceiv";
|
|
};
|
|
|
|
/* Secondary USB port related controller */
|
|
usb1: ssusb@a800000 {
|
|
compatible = "qcom,dwc-usb3-msm";
|
|
reg = <0x0a800000 0x100000>;
|
|
reg-names = "core_base";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 11 IRQ_TYPE_EDGE_RISING>,
|
|
<&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 10 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "pwr_event_irq","dp_hs_phy_irq",
|
|
"ss_phy_irq","dm_hs_phy_irq";
|
|
qcom,use-pdc-interrupts;
|
|
qcom,default-mode-host;
|
|
|
|
USB3_GDSC-supply = <&usb30_sec_gdsc>;
|
|
clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
|
|
<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
|
|
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_SEC_SLEEP_CLK>;
|
|
|
|
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
|
"utmi_clk", "sleep_clk";
|
|
|
|
resets = <&gcc GCC_USB30_SEC_BCR>;
|
|
reset-names = "core_reset";
|
|
|
|
qcom,core-clk-rate = <200000000>;
|
|
qcom,core-clk-rate-hs = <66666667>;
|
|
|
|
interconnect-names = "usb-ddr", "ddr-usb";
|
|
interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>,
|
|
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>;
|
|
|
|
/*
|
|
* Establish dependency on smmu driver so that depopulate path of
|
|
* deferred probe doesn't run into existing bug in smmu driver.
|
|
*/
|
|
|
|
dummy-supply = <&apps_smmu>;
|
|
|
|
dwc3@a800000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0a800000 0xd941>;
|
|
iommus = <&apps_smmu 0x160 0x0>;
|
|
qcom,iommu-dma = "atomic";
|
|
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
|
|
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
usb-phy = <&usb2_phy1>, <&usb_qmp_phy>;
|
|
snps,disable-clk-gating;
|
|
snps,has-lpm-erratum;
|
|
snps,hird-threshold = /bits/ 8 <0x0>;
|
|
snps,ssp-u3-u0-quirk;
|
|
snps,is-utmi-l1-suspend;
|
|
snps,usb2-gadget-lpm-disable;
|
|
snps,dis-u1-entry-quirk;
|
|
snps,dis-u2-entry-quirk;
|
|
tx-fifo-resize;
|
|
maximum-speed = "super-speed";
|
|
dr_mode = "otg";
|
|
usb-role-switch;
|
|
};
|
|
};
|
|
|
|
/* Secondary USB port related High Speed PHY */
|
|
usb2_phy1: hsphy@88e3000 {
|
|
compatible = "qcom,usb-hsphy-snps-femto";
|
|
reg = <0x88e3000 0x110>,
|
|
<0x007801f8 0x4>;
|
|
reg-names = "hsusb_phy_base",
|
|
"phy_rcal_reg";
|
|
|
|
vdd-supply = <&L5A>;
|
|
vdda18-supply = <&L12A>;
|
|
vdda33-supply = <&L2A>;
|
|
qcom,vdd-voltage-level = <0 880000 880000>;
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
|
|
clock-names = "ref_clk_src", "ref_clk";
|
|
|
|
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
|
|
reset-names = "phy_reset";
|
|
qcom,param-override-seq = <0x43 0x70
|
|
0x01 0xb0>;
|
|
qcom,rcal-mask = <0x1e00000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&usb2phy_ac_en2_default>;
|
|
};
|
|
|
|
/* Secondary USB port related QMP PHY */
|
|
usb_qmp_phy: ssphy@88eb000 {
|
|
compatible = "qcom,usb-ssphy-qmp-v2";
|
|
reg = <0x88eb000 0x1000>,
|
|
<0x088eb88c 0x4>;
|
|
reg-names = "qmp_phy_base",
|
|
"pcs_clamp_enable_reg";
|
|
|
|
vdd-supply = <&L5A>;
|
|
qcom,vdd-voltage-level = <0 880000 880000>;
|
|
qcom,vdd-max-load-uA = <47000>;
|
|
core-supply = <&L8C>;
|
|
qcom,qmp-phy-init-seq =
|
|
/* <reg_offset, valuey> */
|
|
<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
|
|
USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01
|
|
USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e
|
|
USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x02
|
|
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16
|
|
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04
|
|
USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24
|
|
USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08
|
|
USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34
|
|
USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06
|
|
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16
|
|
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e
|
|
USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01
|
|
USB3_UNI_QSERDES_COM_SSC_PER1 0x31
|
|
USB3_UNI_QSERDES_COM_SSC_PER2 0x01
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02
|
|
USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xa4
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xaf
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb6
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc
|
|
USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05
|
|
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f
|
|
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff
|
|
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f
|
|
USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f
|
|
USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a
|
|
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54
|
|
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x00
|
|
USB3_UNI_QSERDES_RX_GM_CAL 0x1f
|
|
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f
|
|
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a
|
|
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a
|
|
USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04
|
|
USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
|
|
USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80
|
|
USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04
|
|
USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e
|
|
USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00
|
|
USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0
|
|
USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20
|
|
USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06
|
|
USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12
|
|
USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95
|
|
USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40
|
|
USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0xe4
|
|
USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0xd0
|
|
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10
|
|
USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13
|
|
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7
|
|
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
|
|
USB3_UNI_PCS_RX_SIGDET_LVL 0xaa
|
|
USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
|
|
USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8
|
|
USB3_UNI_PCS_CDR_RESET_TIME 0x0a
|
|
USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88
|
|
USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13
|
|
USB3_UNI_PCS_EQ_CONFIG1 0x4b
|
|
USB3_UNI_PCS_EQ_CONFIG5 0x10
|
|
USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21
|
|
USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c>;
|
|
|
|
qcom,qmp-phy-reg-offset =
|
|
<USB3_UNI_PCS_PCS_STATUS1
|
|
USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
|
|
USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
|
|
USB3_UNI_PCS_POWER_DOWN_CONTROL
|
|
USB3_UNI_PCS_SW_RESET
|
|
USB3_UNI_PCS_START_CONTROL>;
|
|
|
|
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
|
|
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
|
|
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
|
|
clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
|
|
"ref_clk", "com_aux_clk";
|
|
|
|
resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
|
|
<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
|
|
reset-names = "phy_reset", "phy_phy_reset";
|
|
};
|
|
};
|