74f8106930
Add frequency limiter interrupt and enable reset for GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR for Cape GPU. Change-Id: I6444381aab6ec8f139eb7dd8d3221d3ebcdf2457
355 lines
8.2 KiB
Plaintext
355 lines
8.2 KiB
Plaintext
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#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
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&soc {
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msm_gpu: qcom,kgsl-3d0@3d00000 {
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compatible = "qcom,adreno-gpu-gen7-4-0", "qcom,kgsl-3d0";
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status = "ok";
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reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
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<0x03d50000 0x10000>, <0x3d8b000 0x2000>,
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<0x03d9e000 0x1000>, <0x10900000 0x80000>,
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<0x634000 0x1000>;
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reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
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"isense_cntl", "cx_misc", "qdss_gfx",
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"rdpm_cx";
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interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 286 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq", "freq_limiter_irq";
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resets = <&clock_gpucc GPUCC_GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR>;
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reset-names = "freq_limiter_irq_clear";
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clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
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<&clock_gpucc GPU_CC_AHB_CLK>,
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<&aoss_qmp>;
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clock-names = "gcc_gpu_memnoc_gfx",
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"gcc_gpu_snoc_dvm_gfx",
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"gpu_cc_ahb", "apb_pclk";
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qcom,gpu-model = "Adreno730v3";
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qcom,chipid = <0x07030002>;
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qcom,initial-pwrlevel = <11>;
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qcom,no-nap;
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qcom,min-access-length = <32>;
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qcom,ubwc-mode = <4>;
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qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
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qcom,tzone-names = "gpuss-0", "gpuss-1";
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interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
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interconnect-names = "gpu_icc_path";
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qcom,bus-table-cnoc =
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<0>, /* Off */
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<100>; /* On */
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qcom,bus-table-ddr =
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<MHZ_TO_KBPS(0, 4)>, /* index=0 */
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<MHZ_TO_KBPS(200, 4)>, /* index=1 */
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<MHZ_TO_KBPS(451, 4)>, /* index=2 */
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<MHZ_TO_KBPS(547, 4)>, /* index=3 */
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<MHZ_TO_KBPS(681, 4)>, /* index=4 */
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<MHZ_TO_KBPS(768, 4)>, /* index=5 */
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<MHZ_TO_KBPS(1555, 4)>, /* index=6 */
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<MHZ_TO_KBPS(1708, 4)>, /* index=7 */
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<MHZ_TO_KBPS(2092, 4)>, /* index=8 */
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<MHZ_TO_KBPS(2736, 4)>, /* index=9 */
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<MHZ_TO_KBPS(3196, 4)>, /* index=10 */
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<MHZ_TO_KBPS(3350, 4)>; /* index=11 */
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zap-shader {
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memory-region = <&gpu_microcode_mem>;
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};
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/* Power levels */
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qcom,gpu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <900000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <11>;
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qcom,bus-max = <11>;
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qcom,acd-level = <0x882b5ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <862000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <11>;
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qcom,bus-max = <11>;
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qcom,acd-level = <0x882b5ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_TURBO>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <815000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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qcom,acd-level = <0x882b5ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <765000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <11>;
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qcom,acd-level = <0x882c5ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <710000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <6>;
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qcom,bus-max = <11>;
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qcom,acd-level = <0x882c5ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <645000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <6>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882d5ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <580000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <6>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <515000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <6>;
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qcom,bus-max = <8>;
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qcom,acd-level = <0x882e5ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <439000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <3>;
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qcom,bus-max = <8>;
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qcom,acd-level = <0xc0285ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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qcom,gpu-pwrlevel@9 {
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reg = <9>;
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qcom,gpu-freq = <364000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <1>;
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qcom,bus-max = <6>;
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qcom,acd-level = <0xc0285ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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qcom,gpu-pwrlevel@10 {
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reg = <10>;
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qcom,gpu-freq = <324000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <2>;
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qcom,bus-min = <1>;
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qcom,bus-max = <6>;
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qcom,acd-level = <0xc02a5ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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qcom,gpu-pwrlevel@11 {
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reg = <11>;
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qcom,gpu-freq = <285000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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qcom,bus-freq = <2>;
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qcom,bus-min = <1>;
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qcom,bus-max = <5>;
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qcom,acd-level = <0xc02c5ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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qcom,gpu-pwrlevel@12 {
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reg = <12>;
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qcom,gpu-freq = <220000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
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qcom,bus-freq = <2>;
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qcom,bus-min = <1>;
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qcom,bus-max = <5>;
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qcom,acd-level = <0xc8285ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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};
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qcom,gpu-mempools {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools";
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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qcom,mempool-reserved = <2048>;
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};
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/* 8K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <8192>;
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qcom,mempool-reserved = <1024>;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@2 {
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reg = <2>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-reserved = <256>;
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};
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/* 128K Page Pool configuration */
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qcom,gpu-mempool@3 {
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reg = <3>;
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qcom,mempool-page-size = <131072>;
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qcom,mempool-reserved = <128>;
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};
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/* 256K Page Pool configuration */
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qcom,gpu-mempool@4 {
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reg = <4>;
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qcom,mempool-page-size = <262144>;
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qcom,mempool-reserved = <80>;
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};
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/* 1M Page Pool configuration */
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qcom,gpu-mempool@5 {
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reg = <5>;
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qcom,mempool-page-size = <1048576>;
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qcom,mempool-reserved = <32>;
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};
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};
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};
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kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
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compatible = "qcom,kgsl-smmu-v2";
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reg = <0x03da0000 0x40000>;
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vddcx-supply = <&gpu_cc_cx_gdsc>;
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gfx3d_user: gfx3d_user {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x0 0x400>;
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qcom,iommu-dma = "disabled";
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};
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gfx3d_lpac: gfx3d_lpac {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x1 0x400>;
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qcom,iommu-dma = "disabled";
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};
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gfx3d_secure: gfx3d_secure {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x2 0x400>;
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qcom,iommu-dma = "disabled";
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};
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};
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gmu: qcom,gmu@3d69000 {
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compatible = "qcom,gen7-gmu";
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reg = <0x3d68000 0x37000>,
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<0xb290000 0x10000>,
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<0x03D40000 0x10000>;
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reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
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interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
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<0 305 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hfi", "gmu";
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regulator-names = "vddcx", "vdd";
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vddcx-supply = <&gpu_cc_cx_gdsc>;
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vdd-supply = <&gpu_cc_gx_gdsc>;
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clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,
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<&clock_gpucc GPU_CC_CXO_CLK>,
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<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&clock_gpucc GPU_CC_AHB_CLK>,
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<&clock_gpucc GPU_CC_HUB_CX_INT_CLK>,
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<&aoss_qmp>;
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clock-names = "gmu_clk", "cxo_clk", "axi_clk",
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"memnoc_clk", "ahb_clk", "hub_clk", "apb_pclk";
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iommus = <&kgsl_smmu 0x5 0x400>;
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qcom,iommu-dma = "disabled";
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mboxes = <&qmp_aop 0>;
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mbox-names = "aop";
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};
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};
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