Files
android_kernel_xiaomi_sm845…/qcom/neo-qxr-hmt.dtsi
Priyansh Jain 2f25b19ea1 ARM: dts: msm: Add skin wlan mitigation rule for neo hmt variant
Add skin wlan mitigation rule for neo hmt variant based on latest
recommendation.

Change-Id: I7838433d09c0cb960610a7b227159fdcc3a2540c
2023-07-25 23:21:33 -07:00

181 lines
3.6 KiB
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#include <dt-bindings/interconnect/qcom,neo.h>
#include "neo-qxr.dtsi"
&wpss_etm {
status = "disabled";
};
&reserved_memory {
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
};
};
&pcie0 {
status = "ok";
};
&pcie_noc {
status = "ok";
};
&gem_noc {
status = "ok";
};
&mc_virt {
status = "ok";
};
&cnss_pins {
cnss_wlan_en_active: cnss_wlan_en_active {
mux {
pins = "gpio45";
function = "gpio";
};
config {
pins = "gpio45";
drive-strength = <16>;
output-high;
bias-pull-up;
};
};
cnss_wlan_en_sleep: cnss_wlan_en_sleep {
mux {
pins = "gpio45";
function = "gpio";
};
config {
pins = "gpio45";
drive-strength = <2>;
output-low;
bias-pull-down;
};
};
};
&pcie0_rp {
#address-cells = <5>;
#size-cells = <0>;
cnss_pci: cnss_pci {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group>;
memory-region = <&cnss_wlan_mem>;
#address-cells = <1>;
#size-cells = <1>;
cnss_pci_iommu_group: cnss_pci_iommu_group {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
"non-fatal";
};
};
};
&soc {
wlan_kiwi: qcom,cnss-kiwi@b0000000 {
compatible = "qcom,cnss-kiwi";
reg = <0xb0000000 0x10000>;
reg-names = "smmu_iova_ipa";
wlan-en-gpio = <&tlmm 45 0>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
qcom,wlan;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x780000>;
use-pm-domain;
qcom,same-dt-multi-dev;
mboxes = <&qmp_aop 0>;
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 1600000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 1600000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz*/
<30000 1600000>,
/* high: 240-1200 Mbps snoc/anoc: 200 Mhz */
<100000 3200000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
<175000 6553200>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */
<175000 6553200>,
/* super high: DBS mode snoc/anoc: 403 Mhz */
<175000 6553200>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 3200000>,
/** ICC Path 2 **/
<0 0>,
/* ddr: 451.2 MHz */
<2250 902212>,
/* ddr: 451.2 MHz */
<7500 902212>,
/* ddr: 451.2 MHz */
<30000 902212>,
/* ddr: 451.2 MHz */
<100000 902212>,
/* ddr: 1555 MHz */
<175000 3110362>,
/* ddr: 2092 MHz */
<175000 4185562>,
/* ddr: 2133 MHz */
<175000 4300537>,
/* ddr: 547.2 MHz */
<7500 1094362>;
cnss_cdev_apss: qcom,cnss_cdev1 {
#cooling-cells = <2>;
};
};
bluetooth_kiwi: bt_wcn6x5x {
compatible = "qcom,kiwi";
pinctrl-names = "default";
pinctrl-0 = <&bt_en_sleep>;
};
};
&thermal_zones {
sys-therm-1 {
cooling-maps {
cnss_cdev0 {
trip = <&sys_therm1_config0>;
cooling-device = <&cnss_cdev_apss 3 3>;
};
cnss_cdev1 {
trip = <&sys_therm1_config1>;
cooling-device = <&cnss_cdev_apss 4 4>;
};
cnss_cdev2 {
trip = <&sys_therm1_config2>;
cooling-device = <&cnss_cdev_apss 5 5>;
};
};
};
};