mirror of
https://github.com/oplus-giulia-dev/android_kernel_oneplus_sm8650-devicetrees
synced 2025-11-04 14:45:59 +08:00
wlan: dts: add support for PineappleP HDK
Add support for PineappleP HDK. Change-Id: I78d35125e5a1b75d760f5569757299051fa9293b CRs-Fixed: 3568444
This commit is contained in:
Yu Wang
1
Kbuild
1
Kbuild
@@ -37,6 +37,7 @@ endif
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ifeq ($(CONFIG_ARCH_PINEAPPLE),y)
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dtbo-y += pineapple-kiwi-cnss.dtbo
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dtbo-y += pineapplep-hdk-kiwi-cnss.dtbo
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endif
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ifeq ($(CONFIG_ARCH_MONACO),y)
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11
pineapplep-hdk-kiwi-cnss.dts
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11
pineapplep-hdk-kiwi-cnss.dts
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@@ -0,0 +1,11 @@
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/dts-v1/;
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/plugin/;
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#include "pineapplep-hdk-kiwi-cnss.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. PineappleP HDK";
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compatible = "qcom,pineapplep-hdk", "qcom,pineapplep", "qcom,hdk";
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qcom,msm-id = <577 0x10000>, <577 0x20000>;
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qcom,board-id = <0x1f 0>;
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};
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188
pineapplep-hdk-kiwi-cnss.dtsi
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188
pineapplep-hdk-kiwi-cnss.dtsi
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@@ -0,0 +1,188 @@
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#include <dt-bindings/interconnect/qcom,pineapple.h>
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&tlmm {
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cnss_pins {
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cnss_wlan_en_active: cnss_wlan_en_active {
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mux {
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pins = "gpio16";
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function = "gpio";
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};
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config {
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pins = "gpio16";
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drive-strength = <16>;
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output-high;
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bias-pull-up;
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};
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};
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cnss_wlan_en_sleep: cnss_wlan_en_sleep {
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mux {
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pins = "gpio16";
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function = "gpio";
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};
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config {
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pins = "gpio16";
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drive-strength = <2>;
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output-low;
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bias-pull-down;
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};
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};
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};
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};
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&reserved_memory {
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cnss_wlan_mem: cnss_wlan_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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};
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};
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&soc {
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wlan_kiwi: qcom,cnss-kiwi@b0000000 {
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compatible = "qcom,cnss-kiwi";
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reg = <0xb0000000 0x10000>;
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reg-names = "smmu_iova_ipa";
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qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>;
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supported-ids = <0x1107>;
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wlan-en-gpio = <&tlmm 16 0>;
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qcom,bt-en-gpio = <&tlmm 17 0>;
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qcom,sw-ctrl-gpio = <&tlmm 18 0>;
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/* List of GPIOs to be setup for interrupt wakeup capable */
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mpm_wake_set_gpios = <18 19>;
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pinctrl-names = "wlan_en_active", "wlan_en_sleep";
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pinctrl-0 = <&cnss_wlan_en_active>;
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pinctrl-1 = <&cnss_wlan_en_sleep>;
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qcom,wlan;
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qcom,wlan-rc-num = <0>;
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qcom,wlan-ramdump-dynamic = <0x780000>;
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qcom,wlan-cbc-enabled;
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cnss-enable-self-recovery;
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use-pm-domain;
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qcom,same-dt-multi-dev;
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/* For AOP communication, use direct QMP instead of mailbox */
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qcom,qmp = <&aoss_qmp>;
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vdd-wlan-io-supply = <&L15B>;
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qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
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vdd-wlan-io12-supply = <&L3C>;
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qcom,vdd-wlan-io12-config = <1200000 1200000 0 0 1>;
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vdd-wlan-supply = <&S4I>;
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qcom,vdd-wlan-config = <940000 940000 0 0 1>;
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vdd-wlan-aon-supply = <&S2C>;
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qcom,vdd-wlan-aon-config = <976000 976000 0 0 1>;
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vdd-wlan-dig-supply = <&S3C>;
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qcom,vdd-wlan-dig-config = <916000 916000 0 0 1>;
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vdd-wlan-rfa1-supply = <&S6C>;
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qcom,vdd-wlan-rfa1-config = <1864000 1864000 0 0 1>;
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vdd-wlan-rfa2-supply = <&S1C>;
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qcom,vdd-wlan-rfa2-config = <1316000 1316000 0 0 1>;
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interconnects =
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<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
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<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
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interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
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qcom,icc-path-count = <2>;
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qcom,bus-bw-cfg-count = <9>;
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qcom,bus-bw-cfg =
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/** ICC Path 1 **/
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<0 0>, /* no vote */
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/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
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<2250 1600000>,
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/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
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<7500 1600000>,
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/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
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<30000 1600000>,
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/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
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<100000 1600000>,
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/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
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<175000 6448000>,
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/* ultra high: DBS mode snoc/anoc: 403 Mhz */
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<312500 6448000>,
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/* super high: DBS mode snoc/anoc: 533 Mhz */
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<587500 8528000>,
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/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
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<7500 3200000>,
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/** ICC Path 2 **/
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<0 0>,
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/* idle: 0-18 Mbps ddr: 547.2 MHz */
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<2250 2188800>,
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/* low: 18-60 Mbps ddr: 547.2 MHz */
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<7500 2188800>,
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/* medium: 60-240 Mbps ddr: 547.2 MHz */
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<30000 2188800>,
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/* high: 240-1200 Mbps ddr: 547.2 MHz */
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<100000 2188800>,
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/* very high: > 1200 Mbps ddr: 1555 MHz */
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<175000 6220800>,
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/* ultra high: DBS mode ddr: 2092 MHz */
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<312500 8368000>,
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/* super high: DBS mode ddr: 3.2 GHz */
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<587500 12800000>,
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/* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */
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<7500 2188800>;
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qcom,vreg_pdc_map =
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"s3c", "rf",
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"l15B", "rf",
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"l3c", "rf",
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"s1c", "rf",
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"s6c", "rf",
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"s2c", "bb",
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"s4i", "bb";
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qcom,pmu_vreg_map =
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"VDD095_MX_PMU", "s2c",
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"VDD095_PMU", "s4i",
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"VDD_PMU_AON_I", "s3c",
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"VDD095_PMU_BT", "s3c",
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"VDD09_PMU_RFA_I", "s3c",
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"VDD13_PMU_PCIE_I", "s1c",
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"VDD13_PMU_RFA_I", "s1c",
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"VDD19_PMU_PCIE_I", "s6c",
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"VDD19_PMU_RFA_I", "s6c";
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qcom,pdc_init_table =
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"{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}",
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"{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}",
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"{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}",
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"{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}",
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"{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}",
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"{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}",
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"{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}",
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"{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}",
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"{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}",
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"{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}";
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};
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};
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&pcie0_rp {
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#address-cells = <5>;
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#size-cells = <0>;
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cnss_pci0: cnss_pci0 {
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reg = <0 0 0 0 0>;
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qcom,iommu-group = <&cnss_pci_iommu_group0>;
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memory-region = <&cnss_wlan_mem>;
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#address-cells = <1>;
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#size-cells = <1>;
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cnss_pci_iommu_group0: cnss_pci_iommu_group0 {
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qcom,iommu-msi-size = <0x1000>;
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qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
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qcom,iommu-geometry = <0xa0000000 0x10010000>;
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qcom,iommu-dma = "fastmap";
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qcom,iommu-pagetable = "coherent";
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qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
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"non-fatal";
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};
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};
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};
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