Commit label r2.0_00012.0 - GRAPHICS.LA.14.0.r1-08000-lanai.0

2025-11-04 06:44:04 +08:00 · 2024-11-18 09:53:41 +08:00
parent 947dff5550
commit 5313c1cc6a
17 changed files with 1282 additions and 51 deletions
--- a/8
+++ b/8
@@ -75,6 +75,14 @@ dtbo-y += gpu/cliffs-gpu.dtbo \
 		gpu/cliffs7-gpu.dtbo
 endif

+ifeq ($(CONFIG_ARCH_VOLCANO), y)
+dtbo-y += gpu/volcano-gpu.dtbo
+dtbo-y += gpu/volcano6-gpu.dtbo
+dtbo-y += gpu/volcano6p-gpu.dtbo
+dtbo-y += gpu/volcano6i-gpu.dtbo
+dtbo-y += gpu/volcano6ip-gpu.dtbo
+endif
+
 always-y    := $(dtb-y) $(dtbo-y)
 subdir-y    := $(dts-dirs)
 clean-files    := *.dtb *.dtbo
--- a/bindings/adreno.txt
+++ b/bindings/adreno.txt
@@ -5,7 +5,8 @@ Qualcomm Technologies, Inc. Adreno GPU
 Required properties:
 - compatible:		Must be "qcom,kgsl-3d0".
 			May also includes "qcom,adreno-gpu-*" for few targets.
-			Must include "qcom,adreno-gpu-a610" for Bengal/Pitti target.
+			Must include "qcom,adreno-gpu-a610" for Bengal target.
+			Must include "qcom,adreno-gpu-a611" for Pitti target.
 			Must include "qcom,adreno-gpu-a619-holi" for Holi target.
 			Must include "qcom,adreno-gpu-a621" for Neo target.
 			Must include "qcom,adreno-gpu-a660-shima" for Shima target.
@@ -18,6 +19,7 @@ Required properties:
 			Must include "qcom,adreno-gpu-gen7-9-0" for Pineapple target.
 			Must include "qcom,adreno-gpu-gen7-9-1" for Pineapple V2 target.
 			Must include "qcom,adreno-gpu-gen7-11-0" for Cliffs target.
+			Must include "qcom,adreno-gpu-gen8-3-0" for Volcano target.
 - reg:			Specifies the list of register regions for the device.
 - reg-names:		Resource names used for the register regions specified
 			in reg.
--- a/gpu/cliffs-gpu-pwrlevels.dtsi
+++ b/gpu/cliffs-gpu-pwrlevels.dtsi
@@ -17,8 +17,6 @@
 			qcom,bus-freq = <9>;
 			qcom,bus-min = <9>;
 			qcom,bus-max = <9>;
-
-			qcom,acd-level = <0xA02F5FFD>;
 		};
 		/* Turbo_L1*/
 		qcom,gpu-pwrlevel@1 {
@@ -29,8 +27,6 @@
 			qcom,bus-freq = <9>;
 			qcom,bus-min = <9>;
 			qcom,bus-max = <9>;
-
-			qcom,acd-level = <0xA02F5FFD>;
 		};

 		/* Turbo_L0 */
@@ -42,8 +38,6 @@
 			qcom,bus-freq = <9>;
 			qcom,bus-min = <9>;
 			qcom,bus-max = <9>;
-
-			qcom,acd-level = <0xA8285FFD>;
 		};

 		/* Turbo */
@@ -55,8 +49,6 @@
 			qcom,bus-freq = <9>;
 			qcom,bus-min = <7>;
 			qcom,bus-max = <9>;
-
-			qcom,acd-level = <0xA8285FFD>;
 		};

 		/* Nom_L1 */
@@ -68,8 +60,6 @@
 			qcom,bus-freq = <8>;
 			qcom,bus-min = <7>;
 			qcom,bus-max = <9>;
-
-			qcom,acd-level = <0xA8285FFD>;
 		};

 		/* Nom */
@@ -81,8 +71,6 @@
 			qcom,bus-freq = <7>;
 			qcom,bus-min = <6>;
 			qcom,bus-max = <8>;
-
-			qcom,acd-level = <0x88295FFD>;
 		};

 		/* SVS_L2 */
@@ -94,8 +82,6 @@
 			qcom,bus-freq = <7>;
 			qcom,bus-min = <6>;
 			qcom,bus-max = <8>;
-
-			qcom,acd-level = <0x88295FFD>;
 		};

 		/* SVS_L1 */
@@ -107,8 +93,6 @@
 			qcom,bus-freq = <7>;
 			qcom,bus-min = <5>;
 			qcom,bus-max = <8>;
-
-			qcom,acd-level = <0x88295FFD>;
 		};

 		/* SVS */
@@ -120,8 +104,6 @@
 			qcom,bus-freq = <4>;
 			qcom,bus-min = <2>;
 			qcom,bus-max = <7>;
-
-			qcom,acd-level = <0xA8295FFD>;
 		};

 		/* Low_SVS */
@@ -133,8 +115,6 @@
 			qcom,bus-freq = <3>;
 			qcom,bus-min = <1>;
 			qcom,bus-max = <3>;
-
-			qcom,acd-level = <0x882C5FFD>;
 		};

 		/* Low_SVS_D1 */
@@ -146,8 +126,6 @@
 			qcom,bus-freq = <1>;
 			qcom,bus-min = <1>;
 			qcom,bus-max = <3>;
-
-			qcom,acd-level = <0x882F5FFD>;
 		};
 	};
 };
--- a/gpu/cliffs-gpu.dtsi
+++ b/gpu/cliffs-gpu.dtsi
@@ -156,9 +156,6 @@
 		iommus = <&kgsl_smmu 0x5 0x000>;
 		qcom,iommu-dma = "disabled";

-		mboxes = <&qmp_aop 0>;
-		mbox-names = "aop";
-
 		qcom,ipc-core = <0x00400000 0x140000>;
 	};

--- a/gpu/cliffs7-gpu-pwrlevels.dtsi
+++ b/gpu/cliffs7-gpu-pwrlevels.dtsi
@@ -17,8 +17,6 @@
 			qcom,bus-freq = <9>;
 			qcom,bus-min = <9>;
 			qcom,bus-max = <9>;
-
-			qcom,acd-level = <0xA8285FFD>;
 		};
 		/* Turbo */
 		qcom,gpu-pwrlevel@1 {
@@ -29,8 +27,6 @@
 			qcom,bus-freq = <9>;
 			qcom,bus-min = <9>;
 			qcom,bus-max = <9>;
-
-			qcom,acd-level = <0xA8285FFD>;
 		};

 		/* Nom_L1 */
@@ -42,8 +38,6 @@
 			qcom,bus-freq = <8>;
 			qcom,bus-min = <7>;
 			qcom,bus-max = <9>;
-
-			qcom,acd-level = <0xA8285FFD>;
 		};

 		/* Nom */
@@ -55,8 +49,6 @@
 			qcom,bus-freq = <7>;
 			qcom,bus-min = <6>;
 			qcom,bus-max = <8>;
-
-			qcom,acd-level = <0x88295FFD>;
 		};

 		/* SVS_L2 */
@@ -68,8 +60,6 @@
 			qcom,bus-freq = <7>;
 			qcom,bus-min = <6>;
 			qcom,bus-max = <8>;
-
-			qcom,acd-level = <0x88295FFD>;
 		};

 		/* SVS_L1 */
@@ -81,8 +71,6 @@
 			qcom,bus-freq = <7>;
 			qcom,bus-min = <5>;
 			qcom,bus-max = <8>;
-
-			qcom,acd-level = <0x88295FFD>;
 		};

 		/* SVS */
@@ -94,8 +82,6 @@
 			qcom,bus-freq = <4>;
 			qcom,bus-min = <2>;
 			qcom,bus-max = <7>;
-
-			qcom,acd-level = <0xA8295FFD>;
 		};

 		/* Low_SVS */
@@ -107,8 +93,6 @@
 			qcom,bus-freq = <3>;
 			qcom,bus-min = <1>;
 			qcom,bus-max = <3>;
-
-			qcom,acd-level = <0x882C5FFD>;
 		};

 		/* Low_SVS_D1 */
@@ -120,8 +104,6 @@
 			qcom,bus-freq = <1>;
 			qcom,bus-min = <1>;
 			qcom,bus-max = <3>;
-
-			qcom,acd-level = <0x882F5FFD>;
 		};
 	};
 };
--- a/gpu/pineapple-v2-gpu-pwrlevels.dtsi
+++ b/gpu/pineapple-v2-gpu-pwrlevels.dtsi
@@ -383,6 +383,132 @@
 			#address-cells = <1>;
 			#size-cells = <0>;

+			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AA)>;
+
+			qcom,initial-pwrlevel = <8>;
+
+			/* SVS_L2 */
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <720000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+				qcom,bus-freq = <9>;
+				qcom,bus-min = <7>;
+				qcom,bus-max = <9>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L2>;
+			};
+
+			/* SVS_L1 */
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <680000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+				qcom,bus-freq = <7>;
+				qcom,bus-min = <5>;
+				qcom,bus-max = <9>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L1>;
+			};
+
+			/* SVS_L0 */
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <629000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <3>;
+				qcom,bus-max = <7>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L0>;
+			};
+
+			/* SVS */
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <578000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+				qcom,bus-freq = <5>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <7>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS>;
+			};
+
+			/* Low_SVS_L1 */
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <500000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+
+				qcom,bus-freq = <5>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <5>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
+			};
+
+			/* Low_SVS */
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <422000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+				qcom,bus-freq = <5>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <5>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
+			};
+
+			/* Low_SVS_D0 */
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <366000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <3>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
+			};
+
+			/* Low_SVS_D1 */
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
+				qcom,gpu-freq = <310000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+				qcom,bus-freq = <1>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <3>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
+			};
+
+			/* Low_SVS_D2 */
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
+				qcom,gpu-freq = <231000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+
+				qcom,bus-freq = <1>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <1>;
+
+				qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
+			};
+		};
+
+		qcom,gpu-pwrlevels-3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
 			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;

 			qcom,initial-pwrlevel = <11>;
--- a/gpu/pitti-gpu.dts
+++ b/gpu/pitti-gpu.dts
@@ -16,5 +16,5 @@
 	model = "Qualcomm Technologies, Inc. Pitti";
 	compatible = "qcom,pitti";
 	qcom,msm-id = <623 0x10000>;
-	qcom,board-id = <0 0>;
+	qcom,board-id = <0 0>, <0 0x501>, <0 0x600>;
 };
--- a/gpu/pitti-gpu.dtsi
+++ b/gpu/pitti-gpu.dtsi
@@ -1,7 +1,7 @@
 #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))

 &msm_gpu {
-	compatible = "qcom,kgsl-3d0", "qcom,adreno-gpu-a610";
+	compatible = "qcom,kgsl-3d0", "qcom,adreno-gpu-a611";
 	status = "ok";

 	reg = <0x5900000 0x90000>;
@@ -32,8 +32,11 @@
 		"gcc_gpu_memnoc_gfx",
 		"gpu_cc_hlos1_vote_gpu_smmu";

-	interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
-	interrupt-names = "kgsl_3d0_irq";
+	interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>, <0 181 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "kgsl_3d0_irq", "freq_limiter_irq";
+
+	resets = <&gpucc GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR>;
+	reset-names = "freq_limiter_irq_clear";

 	qcom,chipid = <0x06010100>;
 	qcom,gpu-model = "Adreno611v1";
@@ -42,17 +45,19 @@
 	vddcx-supply = <&gpu_cc_cx_gdsc>;
 	vdd-supply = <&gpu_cc_gx_gdsc>;

-	qcom,min-access-length = <64>;
+	qcom,min-access-length = <32>;

 	qcom,ubwc-mode = <2>;

 	qcom,enable-ca-jump;

+	qcom,tzone-names = "gpuss";
+
 	/* Context aware jump busy penalty in us */
 	qcom,ca-busy-penalty = <12000>;

-	nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
-	nvmem-cell-names = "speed_bin", "gaming_bin";
+	nvmem-cells = <&gpu_speed_bin>;
+	nvmem-cell-names = "speed_bin";

 	interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
 	interconnect-names = "gpu_icc_path";
--- a/gpu/volcano-gpu-pwrlevels.dtsi
+++ b/gpu/volcano-gpu-pwrlevels.dtsi
@@ -0,0 +1,344 @@
+&msm_gpu {
+	/* Power level bins */
+	qcom,gpu-pwrlevel-bins {
+		compatible = "qcom,gpu-pwrlevels-bins";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,gpu-pwrlevels-0 {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,initial-pwrlevel = <8>;
+
+			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AD)
+					SKU_CODE(PCODE_1, FC_W0)
+					SKU_CODE(PCODE_1, FC_W1)
+					SKU_CODE(PCODE_2, FC_W0)
+					SKU_CODE(PCODE_2, FC_W1)
+					SKU_CODE(PCODE_3, FC_W0)
+					SKU_CODE(PCODE_3, FC_W1)
+					SKU_CODE(PCODE_0, FC_Y1)
+					SKU_CODE(PCODE_0, FC_Y0)>;
+
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <1150000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
+
+				qcom,bus-freq-ddr7 = <9>;
+				qcom,bus-min-ddr7 = <8>;
+				qcom,bus-max-ddr7 = <9>;
+
+				qcom,bus-freq-ddr8 = <9>;
+				qcom,bus-min-ddr8 = <8>;
+				qcom,bus-max-ddr8 = <9>;
+
+				qcom,acd-level = <ACD_LEVEL_Turbo_L2>;
+			};
+
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <1050000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+
+				qcom,bus-freq-ddr7 = <9>;
+				qcom,bus-min-ddr7 = <8>;
+				qcom,bus-max-ddr7 = <9>;
+
+				qcom,bus-freq-ddr8 = <9>;
+				qcom,bus-min-ddr8 = <8>;
+				qcom,bus-max-ddr8 = <9>;
+
+				qcom,acd-level = <ACD_LEVEL_Turbo_L1>;
+			};
+
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <960000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+
+				qcom,bus-freq-ddr7 = <8>;
+				qcom,bus-min-ddr7 = <8>;
+				qcom,bus-max-ddr7 = <8>;
+
+				qcom,bus-freq-ddr8 = <7>;
+				qcom,bus-min-ddr8 = <7>;
+				qcom,bus-max-ddr8 = <8>;
+
+				qcom,acd-level = <ACD_LEVEL_Turbo>;
+			};
+
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <895000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+
+				qcom,bus-freq-ddr7 = <8>;
+				qcom,bus-min-ddr7 = <7>;
+				qcom,bus-max-ddr7 = <8>;
+
+				qcom,bus-freq-ddr8 = <7>;
+				qcom,bus-min-ddr8 = <6>;
+				qcom,bus-max-ddr8 = <8>;
+
+				qcom,acd-level = <ACD_LEVEL_Nominal_L1>;
+			};
+
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <763000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+				qcom,bus-freq-ddr7 = <7>;
+				qcom,bus-min-ddr7 = <6>;
+				qcom,bus-max-ddr7 = <8>;
+
+				qcom,bus-freq-ddr8 = <6>;
+				qcom,bus-min-ddr8 = <5>;
+				qcom,bus-max-ddr8 = <7>;
+
+				qcom,acd-level = <ACD_LEVEL_Nominal>;
+			};
+
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <688000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+				qcom,bus-freq-ddr7 = <6>;
+				qcom,bus-min-ddr7 = <5>;
+				qcom,bus-max-ddr7 = <7>;
+
+				qcom,bus-freq-ddr8 = <6>;
+				qcom,bus-min-ddr8 = <5>;
+				qcom,bus-max-ddr8 = <7>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L2>;
+			};
+
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <644000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+				qcom,bus-freq-ddr7 = <5>;
+				qcom,bus-min-ddr7 = <4>;
+				qcom,bus-max-ddr7 = <6>;
+
+				qcom,bus-freq-ddr8 = <5>;
+				qcom,bus-min-ddr8 = <4>;
+				qcom,bus-max-ddr8 = <6>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L1>;
+			};
+
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
+				qcom,gpu-freq = <510000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+				qcom,bus-freq-ddr7 = <4>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <5>;
+
+				qcom,bus-freq-ddr8 = <4>;
+				qcom,bus-min-ddr8 = <3>;
+				qcom,bus-max-ddr8 = <5>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS>;
+			};
+
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
+				qcom,gpu-freq = <362000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+				qcom,bus-freq-ddr7 = <2>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <4>;
+
+				qcom,bus-freq-ddr8 = <2>;
+				qcom,bus-min-ddr8 = <2>;
+				qcom,bus-max-ddr8 = <4>;
+
+				qcom,acd-level = <ACD_LEVEL_LowSVS>;
+			};
+
+			qcom,gpu-pwrlevel@9 {
+				reg = <9>;
+				qcom,gpu-freq = <264000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+				qcom,bus-freq-ddr7 = <2>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <4>;
+
+				qcom,bus-freq-ddr8 = <2>;
+				qcom,bus-min-ddr8 = <2>;
+				qcom,bus-max-ddr8 = <4>;
+
+				qcom,acd-level = <ACD_LEVEL_LowSVS_D1>;
+			};
+
+		};
+
+		qcom,gpu-pwrlevels-1 {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,initial-pwrlevel = <7>;
+
+			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AB)
+					SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
+
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <1050000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+
+				qcom,bus-freq-ddr7 = <9>;
+				qcom,bus-min-ddr7 = <8>;
+				qcom,bus-max-ddr7 = <9>;
+
+				qcom,bus-freq-ddr8 = <9>;
+				qcom,bus-min-ddr8 = <8>;
+				qcom,bus-max-ddr8 = <9>;
+
+				qcom,acd-level = <ACD_LEVEL_Turbo_L1>;
+			};
+
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <960000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+
+				qcom,bus-freq-ddr7 = <8>;
+				qcom,bus-min-ddr7 = <8>;
+				qcom,bus-max-ddr7 = <8>;
+
+				qcom,bus-freq-ddr8 = <7>;
+				qcom,bus-min-ddr8 = <7>;
+				qcom,bus-max-ddr8 = <8>;
+
+				qcom,acd-level = <ACD_LEVEL_Turbo>;
+			};
+
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <895000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+
+				qcom,bus-freq-ddr7 = <8>;
+				qcom,bus-min-ddr7 = <7>;
+				qcom,bus-max-ddr7 = <8>;
+
+				qcom,bus-freq-ddr8 = <7>;
+				qcom,bus-min-ddr8 = <6>;
+				qcom,bus-max-ddr8 = <8>;
+
+				qcom,acd-level = <ACD_LEVEL_Nominal_L1>;
+			};
+
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <763000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+				qcom,bus-freq-ddr7 = <7>;
+				qcom,bus-min-ddr7 = <6>;
+				qcom,bus-max-ddr7 = <8>;
+
+				qcom,bus-freq-ddr8 = <6>;
+				qcom,bus-min-ddr8 = <5>;
+				qcom,bus-max-ddr8 = <7>;
+
+				qcom,acd-level = <ACD_LEVEL_Nominal>;
+			};
+
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <688000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+				qcom,bus-freq-ddr7 = <6>;
+				qcom,bus-min-ddr7 = <5>;
+				qcom,bus-max-ddr7 = <7>;
+
+				qcom,bus-freq-ddr8 = <6>;
+				qcom,bus-min-ddr8 = <5>;
+				qcom,bus-max-ddr8 = <7>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L2>;
+			};
+
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <644000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+				qcom,bus-freq-ddr7 = <5>;
+				qcom,bus-min-ddr7 = <4>;
+				qcom,bus-max-ddr7 = <6>;
+
+				qcom,bus-freq-ddr8 = <5>;
+				qcom,bus-min-ddr8 = <4>;
+				qcom,bus-max-ddr8 = <6>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L1>;
+			};
+
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <510000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+				qcom,bus-freq-ddr7 = <4>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <5>;
+
+				qcom,bus-freq-ddr8 = <4>;
+				qcom,bus-min-ddr8 = <3>;
+				qcom,bus-max-ddr8 = <5>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS>;
+			};
+
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
+				qcom,gpu-freq = <362000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+				qcom,bus-freq-ddr7 = <2>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <4>;
+
+				qcom,bus-freq-ddr8 = <2>;
+				qcom,bus-min-ddr8 = <2>;
+				qcom,bus-max-ddr8 = <4>;
+
+				qcom,acd-level = <ACD_LEVEL_LowSVS>;
+			};
+
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
+				qcom,gpu-freq = <264000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+				qcom,bus-freq-ddr7 = <2>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <4>;
+
+				qcom,bus-freq-ddr8 = <2>;
+				qcom,bus-min-ddr8 = <2>;
+				qcom,bus-max-ddr8 = <4>;
+
+				qcom,acd-level = <ACD_LEVEL_LowSVS_D1>;
+			};
+
+		};
+	};
+};
--- a/gpu/volcano-gpu.dts
+++ b/gpu/volcano-gpu.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,gcc-volcano.h>
+#include <dt-bindings/clock/qcom,gpucc-volcano.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,volcano.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "volcano-gpu.dtsi"
+#include "volcano-gpu-pwrlevels.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Volcano SoC";
+	compatible = "qcom,volcano";
+	qcom,msm-id = <636 0x10000>;
+	qcom,board-id = <0 0>;
+};
--- a/gpu/volcano-gpu.dtsi
+++ b/gpu/volcano-gpu.dtsi
@@ -0,0 +1,228 @@
+
+#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
+
+#define UINT32_MAX 4294967295
+
+/* External feature codes */
+#define FC_UNKNOWN 0x0
+#define FC_AA 0x1
+#define FC_AB 0x2
+#define FC_AC 0x3
+#define FC_AD 0x4
+#define FC_AE 0x5
+#define FC_AF 0x6
+#define FC_AG 0x7
+#define FC_AH 0x8
+
+/* SubPart feature code */
+#define FC_W0 0x00d1
+#define FC_W1 0x00d2
+
+/* Internal feature codes */
+#define FC_Y0 0x00f1
+#define FC_Y1 0x00f2
+#define FC_Y2 0x00f3
+#define FC_Y3 0x00f4
+#define FC_Y4 0x00f5
+#define FC_Y5 0x00f6
+#define FC_Y6 0x00f7
+#define FC_Y7 0x00f8
+#define FC_Y8 0x00f9
+#define FC_Y9 0x00fa
+#define FC_YA 0x00fb
+#define FC_YB 0x00fc
+#define FC_YC 0x00fd
+#define FC_YD 0x00fe
+#define FC_YE 0x00ff
+#define FC_YF 0x0100
+
+/* Pcodes */
+#define PCODE_UNKNOWN 0
+#define PCODE_0 1
+#define PCODE_1 2
+#define PCODE_2 3
+#define PCODE_3 4
+#define PCODE_4 5
+#define PCODE_5 6
+#define PCODE_6 7
+#define PCODE_7 8
+#define PCODE_8 9
+
+#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode)
+
+/* ACD Control register values */
+#define ACD_LEVEL_Turbo_L2	0xa02f5ffd
+#define ACD_LEVEL_Turbo_L1	0x88285ffd
+#define ACD_LEVEL_Turbo		0xa8285ffd
+#define ACD_LEVEL_Nominal_L1	0x88295ffd
+#define ACD_LEVEL_Nominal	0xa8295ffd
+#define ACD_LEVEL_SVS_L2	0x882a5ffd
+#define ACD_LEVEL_SVS_L1	0x882a5ffd
+#define ACD_LEVEL_SVS		0x882b5ffd
+#define ACD_LEVEL_LowSVS	0xc02c5ffd
+#define ACD_LEVEL_LowSVS_D1	0xc8295ffd
+
+&msm_gpu {
+	compatible = "qcom,adreno-gpu-gen8-3-0", "qcom,kgsl-3d0";
+	status = "ok";
+	reg = <0x3d00000 0x40000>, <0x3d61000 0x3000>,
+		<0x3d50000 0x10000>, <0x3d9e000 0x2000>,
+		<0x10900000 0x80000>, <0x10048000 0x8000>,
+		<0x10b05000 0x1000>;
+	reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", "cx_misc",
+		"qdss_gfx", "qdss_etr", "qdss_tmc";
+
+	interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 80 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "kgsl_3d0_irq", "cx_host_irq";
+
+	clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+			<&gpucc GPU_CC_AHB_CLK>,
+			<&aoss_qmp QDSS_CLK>;
+	clock-names = "gcc_gpu_memnoc_gfx",
+			"gcc_gpu_snoc_dvm_gfx",
+			"gpu_cc_ahb",
+			"apb_pclk";
+
+	qcom,min-access-length = <32>;
+
+	qcom,ubwc-mode = <4>;
+
+	qcom,tzone-names = "gpuss-0", "gpuss-1";
+
+	interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
+	interconnect-names = "gpu_icc_path";
+
+	qcom,bus-table-cnoc =
+		<0>,   /* Off */
+		<100>; /* On */
+
+	qcom,bus-table-ddr7 =
+		<MHZ_TO_KBPS(0, 4)>,    /* index=0			*/
+		<MHZ_TO_KBPS(200, 4)>,  /* index=1 LOW SVS	*/
+		<MHZ_TO_KBPS(547, 4)>,	/* index=2 LOW SVS	*/
+		<MHZ_TO_KBPS(768, 4)>,	/* index=3 SVS		*/
+		<MHZ_TO_KBPS(1017, 4)>, /* index=4 SVS		*/
+		<MHZ_TO_KBPS(1353, 4)>, /* index=5 SVS L1	*/
+		<MHZ_TO_KBPS(1555, 4)>, /* index=6 NOM		*/
+		<MHZ_TO_KBPS(1708, 4)>, /* index=7 NOM		*/
+		<MHZ_TO_KBPS(2092, 4)>, /* index=8 TURBO	*/
+		<MHZ_TO_KBPS(4761, 4)>;	/* index=9*/
+
+	qcom,bus-table-ddr8 =
+		<MHZ_TO_KBPS(0, 4)>,	/* index=0			*/
+		<MHZ_TO_KBPS(200, 4)>,	/* index=1 LOW SVS	*/
+		<MHZ_TO_KBPS(547, 4)>,	/* index=2 LOW SVS	*/
+		<MHZ_TO_KBPS(768, 4)>,	/* index=3 SVS		*/
+		<MHZ_TO_KBPS(1555, 4)>,	/* index=4 SVS		*/
+		<MHZ_TO_KBPS(1708, 4)>, /* index=5 SVS L1	*/
+		<MHZ_TO_KBPS(2092, 4)>, /* index=6 NOM		*/
+		<MHZ_TO_KBPS(2736, 4)>, /* index=7 TURBO	*/
+		<MHZ_TO_KBPS(3196, 4)>, /* index=8 TURBO L1	*/
+		<MHZ_TO_KBPS(4761, 4)>;	/* index=9*/
+
+	zap-shader {
+		memory-region = <&gpu_microcode_mem>;
+	};
+
+	qcom,gpu-mempools {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,gpu-mempools";
+
+		/* 4K Page Pool configuration */
+		qcom,gpu-mempool@0 {
+			reg = <0>;
+			qcom,mempool-page-size = <4096>;
+			qcom,mempool-reserved = <2048>;
+		};
+		/* 8K Page Pool configuration */
+		qcom,gpu-mempool@1 {
+			reg = <1>;
+			qcom,mempool-page-size = <8192>;
+			qcom,mempool-reserved = <1024>;
+		};
+		/* 64K Page Pool configuration */
+		qcom,gpu-mempool@2 {
+			reg = <2>;
+			qcom,mempool-page-size = <65536>;
+			qcom,mempool-reserved = <256>;
+		};
+		/* 128K Page Pool configuration */
+		qcom,gpu-mempool@3 {
+			reg = <3>;
+			qcom,mempool-page-size = <131072>;
+			qcom,mempool-reserved = <128>;
+		};
+		/* 256K Page Pool configuration */
+		qcom,gpu-mempool@4 {
+			reg = <4>;
+			qcom,mempool-page-size = <262144>;
+			qcom,mempool-reserved = <80>;
+		};
+		/* 1M Page Pool configuration */
+		qcom,gpu-mempool@5 {
+			reg = <5>;
+			qcom,mempool-page-size = <1048576>;
+			qcom,mempool-reserved = <32>;
+		};
+	};
+};
+
+&soc {
+	kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
+		compatible = "qcom,kgsl-smmu-v2";
+		reg = <0x3da0000 0x40000>;
+
+		vddcx-supply = <&gpu_cc_cx_gdsc>;
+
+		gfx3d_user: gfx3d_user {
+			compatible = "qcom,smmu-kgsl-cb";
+			iommus = <&kgsl_smmu 0x0 0x000>;
+			qcom,iommu-dma = "disabled";
+		};
+
+		gfx3d_secure: gfx3d_secure {
+			compatible = "qcom,smmu-kgsl-cb";
+			iommus = <&kgsl_smmu 0x2 0x000>;
+			qcom,iommu-dma = "disabled";
+		};
+	};
+
+	gmu: qcom,gmu@3d37000 {
+		compatible = "qcom,gen8-gmu";
+
+		reg = <0x3d37000 0x68000>,
+			<0x3d40000 0x10000>;
+		reg-names = "gmu", "gmu_ao_blk_dec0";
+
+		interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
+			<0 305 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hfi", "gmu";
+
+		regulator-names = "vddcx", "vdd";
+
+		vddcx-supply = <&gpu_cc_cx_gdsc>;
+		vdd-supply = <&gx_clkctl_gx_gdsc>;
+
+		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+			<&gpucc GPU_CC_CXO_CLK>,
+			<&gcc GCC_DDRSS_GPU_AXI_CLK>,
+			<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			<&gpucc GPU_CC_AHB_CLK>,
+			<&gpucc GPU_CC_HUB_CX_INT_CLK>;
+
+		clock-names = "gmu_clk", "cxo_clk", "axi_clk",
+			"memnoc_clk", "ahb_clk", "hub_clk";
+
+		qcom,gmu-freq-table = <350000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
+					<650000000 RPMH_REGULATOR_LEVEL_SVS>;
+
+		qcom,gmu-perf-ddr-bw = <MHZ_TO_KBPS(768, 4)>;
+
+		iommus = <&kgsl_smmu 0x5 0x000>;
+		qcom,iommu-dma = "disabled";
+
+		qcom,qmp = <&aoss_qmp>;
+	};
+};
--- a/gpu/volcano6-gpu-pwrlevels.dtsi
+++ b/gpu/volcano6-gpu-pwrlevels.dtsi
@@ -0,0 +1,305 @@
+&msm_gpu {
+	/* Power level bins */
+	qcom,gpu-pwrlevel-bins {
+		compatible = "qcom,gpu-pwrlevels-bins";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,gpu-pwrlevels-0 {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,initial-pwrlevel = <8>;
+
+			qcom,sku-codes = <SKU_CODE(PCODE_0, FC_Y1)
+				SKU_CODE(PCODE_0, FC_Y0)>;
+
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <1150000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
+
+				qcom,bus-freq-ddr7 = <9>;
+				qcom,bus-min-ddr7 = <8>;
+				qcom,bus-max-ddr7 = <9>;
+
+				qcom,bus-freq-ddr8 = <9>;
+				qcom,bus-min-ddr8 = <8>;
+				qcom,bus-max-ddr8 = <9>;
+
+				qcom,acd-level = <ACD_LEVEL_Turbo_L2>;
+			};
+
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <1050000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+
+				qcom,bus-freq-ddr7 = <9>;
+				qcom,bus-min-ddr7 = <8>;
+				qcom,bus-max-ddr7 = <9>;
+
+				qcom,bus-freq-ddr8 = <9>;
+				qcom,bus-min-ddr8 = <8>;
+				qcom,bus-max-ddr8 = <9>;
+
+				qcom,acd-level = <ACD_LEVEL_Turbo_L1>;
+			};
+
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <960000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+
+				qcom,bus-freq-ddr7 = <8>;
+				qcom,bus-min-ddr7 = <8>;
+				qcom,bus-max-ddr7 = <8>;
+
+				qcom,bus-freq-ddr8 = <7>;
+				qcom,bus-min-ddr8 = <7>;
+				qcom,bus-max-ddr8 = <8>;
+
+				qcom,acd-level = <ACD_LEVEL_Turbo>;
+			};
+
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <895000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+
+				qcom,bus-freq-ddr7 = <8>;
+				qcom,bus-min-ddr7 = <7>;
+				qcom,bus-max-ddr7 = <8>;
+
+				qcom,bus-freq-ddr8 = <7>;
+				qcom,bus-min-ddr8 = <6>;
+				qcom,bus-max-ddr8 = <8>;
+
+				qcom,acd-level = <ACD_LEVEL_Nominal_L1>;
+			};
+
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <763000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+				qcom,bus-freq-ddr7 = <7>;
+				qcom,bus-min-ddr7 = <6>;
+				qcom,bus-max-ddr7 = <8>;
+
+				qcom,bus-freq-ddr8 = <6>;
+				qcom,bus-min-ddr8 = <5>;
+				qcom,bus-max-ddr8 = <7>;
+
+				qcom,acd-level = <ACD_LEVEL_Nominal>;
+			};
+
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <688000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+				qcom,bus-freq-ddr7 = <6>;
+				qcom,bus-min-ddr7 = <5>;
+				qcom,bus-max-ddr7 = <7>;
+
+				qcom,bus-freq-ddr8 = <6>;
+				qcom,bus-min-ddr8 = <5>;
+				qcom,bus-max-ddr8 = <7>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L2>;
+			};
+
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <644000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+				qcom,bus-freq-ddr7 = <5>;
+				qcom,bus-min-ddr7 = <4>;
+				qcom,bus-max-ddr7 = <6>;
+
+				qcom,bus-freq-ddr8 = <5>;
+				qcom,bus-min-ddr8 = <4>;
+				qcom,bus-max-ddr8 = <6>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L1>;
+			};
+
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
+				qcom,gpu-freq = <510000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+				qcom,bus-freq-ddr7 = <4>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <5>;
+
+				qcom,bus-freq-ddr8 = <4>;
+				qcom,bus-min-ddr8 = <3>;
+				qcom,bus-max-ddr8 = <5>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS>;
+			};
+
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
+				qcom,gpu-freq = <362000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+				qcom,bus-freq-ddr7 = <2>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <4>;
+
+				qcom,bus-freq-ddr8 = <2>;
+				qcom,bus-min-ddr8 = <2>;
+				qcom,bus-max-ddr8 = <4>;
+
+				qcom,acd-level = <ACD_LEVEL_LowSVS>;
+			};
+
+			qcom,gpu-pwrlevel@9 {
+				reg = <9>;
+				qcom,gpu-freq = <264000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+				qcom,bus-freq-ddr7 = <2>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <4>;
+
+				qcom,bus-freq-ddr8 = <2>;
+				qcom,bus-min-ddr8 = <2>;
+				qcom,bus-max-ddr8 = <4>;
+
+				qcom,acd-level = <ACD_LEVEL_LowSVS_D1>;
+			};
+
+		};
+
+		qcom,gpu-pwrlevels-1 {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,initial-pwrlevel = <5>;
+
+			qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AB)
+				SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
+
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <895000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+
+				qcom,bus-freq-ddr7 = <9>;
+				qcom,bus-min-ddr7 = <7>;
+				qcom,bus-max-ddr7 = <9>;
+
+				qcom,bus-freq-ddr8 = <9>;
+				qcom,bus-min-ddr8 = <7>;
+				qcom,bus-max-ddr8 = <9>;
+
+				qcom,acd-level = <ACD_LEVEL_Nominal_L1>;
+			};
+
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <763000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+				qcom,bus-freq-ddr7 = <7>;
+				qcom,bus-min-ddr7 = <6>;
+				qcom,bus-max-ddr7 = <8>;
+
+				qcom,bus-freq-ddr8 = <6>;
+				qcom,bus-min-ddr8 = <5>;
+				qcom,bus-max-ddr8 = <8>;
+
+				qcom,acd-level = <ACD_LEVEL_Nominal>;
+			};
+
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <688000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+				qcom,bus-freq-ddr7 = <6>;
+				qcom,bus-min-ddr7 = <5>;
+				qcom,bus-max-ddr7 = <7>;
+
+				qcom,bus-freq-ddr8 = <6>;
+				qcom,bus-min-ddr8 = <5>;
+				qcom,bus-max-ddr8 = <7>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L2>;
+			};
+
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <644000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+				qcom,bus-freq-ddr7 = <5>;
+				qcom,bus-min-ddr7 = <4>;
+				qcom,bus-max-ddr7 = <6>;
+
+				qcom,bus-freq-ddr8 = <5>;
+				qcom,bus-min-ddr8 = <4>;
+				qcom,bus-max-ddr8 = <6>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS_L1>;
+			};
+
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <510000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+				qcom,bus-freq-ddr7 = <4>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <5>;
+
+				qcom,bus-freq-ddr8 = <4>;
+				qcom,bus-min-ddr8 = <3>;
+				qcom,bus-max-ddr8 = <5>;
+
+				qcom,acd-level = <ACD_LEVEL_SVS>;
+			};
+
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <362000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+				qcom,bus-freq-ddr7 = <2>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <4>;
+
+				qcom,bus-freq-ddr8 = <2>;
+				qcom,bus-min-ddr8 = <2>;
+				qcom,bus-max-ddr8 = <4>;
+
+				qcom,acd-level = <ACD_LEVEL_LowSVS>;
+			};
+
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <264000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+				qcom,bus-freq-ddr7 = <2>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <4>;
+
+				qcom,bus-freq-ddr8 = <2>;
+				qcom,bus-min-ddr8 = <2>;
+				qcom,bus-max-ddr8 = <4>;
+
+				qcom,acd-level = <ACD_LEVEL_LowSVS_D1>;
+			};
+
+		};
+	};
+};
--- a/gpu/volcano6-gpu.dts
+++ b/gpu/volcano6-gpu.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,gcc-volcano.h>
+#include <dt-bindings/clock/qcom,gpucc-volcano.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,volcano.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "volcano-gpu.dtsi"
+#include "volcano6-gpu-pwrlevels.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Volcano6 SoC";
+	compatible = "qcom,volcano";
+	qcom,msm-id = <640 0x10000>;
+	qcom,board-id = <0 0>;
+};
--- a/gpu/volcano6i-gpu-pwrlevels.dtsi
+++ b/gpu/volcano6i-gpu-pwrlevels.dtsi
@@ -0,0 +1,151 @@
+&msm_gpu {
+	/* Power level bins */
+	qcom,gpu-pwrlevel-bins {
+		compatible = "qcom,gpu-pwrlevels-bins";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,gpu-pwrlevels-0 {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,initial-pwrlevel = <7>;
+
+			qcom,sku-codes = <SKU_CODE(PCODE_0, FC_Y0)
+				SKU_CODE(PCODE_0, FC_Y1)
+				SKU_CODE(PCODE_5, FC_Y0)
+				SKU_CODE(PCODE_5, FC_Y1)
+				SKU_CODE(PCODE_UNKNOWN, FC_AA)
+				SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
+
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <1050000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+
+				qcom,bus-freq-ddr7 = <9>;
+				qcom,bus-min-ddr7 = <8>;
+				qcom,bus-max-ddr7 = <9>;
+
+				qcom,bus-freq-ddr8 = <9>;
+				qcom,bus-min-ddr8 = <8>;
+				qcom,bus-max-ddr8 = <9>;
+			};
+
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <960000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+
+				qcom,bus-freq-ddr7 = <8>;
+				qcom,bus-min-ddr7 = <8>;
+				qcom,bus-max-ddr7 = <8>;
+
+				qcom,bus-freq-ddr8 = <7>;
+				qcom,bus-min-ddr8 = <7>;
+				qcom,bus-max-ddr8 = <8>;
+			};
+
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <895000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+
+				qcom,bus-freq-ddr7 = <8>;
+				qcom,bus-min-ddr7 = <7>;
+				qcom,bus-max-ddr7 = <8>;
+
+				qcom,bus-freq-ddr8 = <7>;
+				qcom,bus-min-ddr8 = <6>;
+				qcom,bus-max-ddr8 = <8>;
+			};
+
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <763000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+				qcom,bus-freq-ddr7 = <7>;
+				qcom,bus-min-ddr7 = <6>;
+				qcom,bus-max-ddr7 = <8>;
+
+				qcom,bus-freq-ddr8 = <6>;
+				qcom,bus-min-ddr8 = <5>;
+				qcom,bus-max-ddr8 = <7>;
+			};
+
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <688000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+				qcom,bus-freq-ddr7 = <6>;
+				qcom,bus-min-ddr7 = <5>;
+				qcom,bus-max-ddr7 = <7>;
+
+				qcom,bus-freq-ddr8 = <6>;
+				qcom,bus-min-ddr8 = <5>;
+				qcom,bus-max-ddr8 = <7>;
+			};
+
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <644000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+				qcom,bus-freq-ddr7 = <5>;
+				qcom,bus-min-ddr7 = <4>;
+				qcom,bus-max-ddr7 = <6>;
+
+				qcom,bus-freq-ddr8 = <5>;
+				qcom,bus-min-ddr8 = <4>;
+				qcom,bus-max-ddr8 = <6>;
+			};
+
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <510000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+				qcom,bus-freq-ddr7 = <4>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <5>;
+
+				qcom,bus-freq-ddr8 = <4>;
+				qcom,bus-min-ddr8 = <3>;
+				qcom,bus-max-ddr8 = <5>;
+			};
+
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
+				qcom,gpu-freq = <362000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+				qcom,bus-freq-ddr7 = <2>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <4>;
+
+				qcom,bus-freq-ddr8 = <2>;
+				qcom,bus-min-ddr8 = <2>;
+				qcom,bus-max-ddr8 = <4>;
+			};
+
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
+				qcom,gpu-freq = <264000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+				qcom,bus-freq-ddr7 = <2>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <4>;
+
+				qcom,bus-freq-ddr8 = <2>;
+				qcom,bus-min-ddr8 = <2>;
+				qcom,bus-max-ddr8 = <4>;
+			};
+
+		};
+	};
+};
--- a/gpu/volcano6i-gpu.dts
+++ b/gpu/volcano6i-gpu.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,gcc-volcano.h>
+#include <dt-bindings/clock/qcom,gpucc-volcano.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,volcano.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "volcano-gpu.dtsi"
+#include "volcano6i-gpu-pwrlevels.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Volcano6I SoC";
+	compatible = "qcom,volcano";
+	qcom,msm-id = <657 0x10000>;
+	qcom,board-id = <0 0>;
+};
--- a/gpu/volcano6ip-gpu.dts
+++ b/gpu/volcano6ip-gpu.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,gcc-volcano.h>
+#include <dt-bindings/clock/qcom,gpucc-volcano.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,volcano.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "volcano-gpu.dtsi"
+#include "volcano6i-gpu-pwrlevels.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Volcano6IP SoC";
+	compatible = "qcom,volcanop";
+	qcom,msm-id = <658 0x10000>;
+	qcom,board-id = <0 0>;
+};
--- a/gpu/volcano6p-gpu.dts
+++ b/gpu/volcano6p-gpu.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,gcc-volcano.h>
+#include <dt-bindings/clock/qcom,gpucc-volcano.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,volcano.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "volcano-gpu.dtsi"
+#include "volcano6-gpu-pwrlevels.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Volcano6P SoC";
+	compatible = "qcom,volcanop";
+	qcom,msm-id = <641 0x10000>;
+	qcom,board-id = <0 0>;
+};