mirror of
https://github.com/oplus-giulia-dev/android_kernel_oneplus_sm8650-devicetrees
synced 2025-11-04 06:44:04 +08:00
Commit label r2.0_00020.0 - KERNEL.PLATFORM.3.0.r1-11800-kernel.0
This commit is contained in:
android-t1
@@ -0,0 +1,769 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/input/touchscreen/azoteq,iqs7211.yaml#
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||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
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||||
title: Azoteq IQS7210A/7211A/E Trackpad/Touchscreen Controller
|
||||
|
||||
maintainers:
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- Jeff LaBundy <jeff@labundy.com>
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||||
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||||
description: |
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||||
The Azoteq IQS7210A, IQS7211A and IQS7211E trackpad and touchscreen control-
|
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lers employ projected-capacitance sensing and can track two contacts.
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Link to datasheets: https://www.azoteq.com/
|
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|
||||
properties:
|
||||
compatible:
|
||||
enum:
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- azoteq,iqs7210a
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||||
- azoteq,iqs7211a
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- azoteq,iqs7211e
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reg:
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maxItems: 1
|
||||
|
||||
irq-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
Specifies the GPIO connected to the device's active-low RDY output. The
|
||||
pin doubles as the IQS7211E's active-low MCLR input, in which case this
|
||||
GPIO must be configured as open-drain.
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
Specifies the GPIO connected to the device's active-low MCLR input. The
|
||||
device is temporarily held in hardware reset prior to initialization if
|
||||
this property is present.
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||||
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||||
azoteq,forced-comms:
|
||||
type: boolean
|
||||
description:
|
||||
Enables forced communication; to be used with host adapters that cannot
|
||||
tolerate clock stretching.
|
||||
|
||||
azoteq,forced-comms-default:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
description:
|
||||
Indicates if the device's OTP memory enables (1) or disables (0) forced
|
||||
communication by default. Specifying this property can expedite startup
|
||||
time if the default value is known.
|
||||
|
||||
If this property is not specified, communication is not initiated until
|
||||
the device asserts its RDY pin shortly after exiting hardware reset. At
|
||||
that point, forced communication is either enabled or disabled based on
|
||||
the presence or absence of the 'azoteq,forced-comms' property.
|
||||
|
||||
azoteq,rate-active-ms:
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description: Specifies the report rate (in ms) during active mode.
|
||||
|
||||
azoteq,rate-touch-ms:
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description: Specifies the report rate (in ms) during idle-touch mode.
|
||||
|
||||
azoteq,rate-idle-ms:
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description: Specifies the report rate (in ms) during idle mode.
|
||||
|
||||
azoteq,rate-lp1-ms:
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description: Specifies the report rate (in ms) during low-power mode 1.
|
||||
|
||||
azoteq,rate-lp2-ms:
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description: Specifies the report rate (in ms) during low-power mode 2.
|
||||
|
||||
azoteq,timeout-active-ms:
|
||||
multipleOf: 1000
|
||||
minimum: 0
|
||||
maximum: 65535000
|
||||
description:
|
||||
Specifies the length of time (in ms) to wait for an event before moving
|
||||
from active mode to idle or idle-touch modes.
|
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||||
azoteq,timeout-touch-ms:
|
||||
multipleOf: 1000
|
||||
minimum: 0
|
||||
maximum: 65535000
|
||||
description:
|
||||
Specifies the length of time (in ms) to wait for an event before moving
|
||||
from idle-touch mode to idle mode.
|
||||
|
||||
azoteq,timeout-idle-ms:
|
||||
multipleOf: 1000
|
||||
minimum: 0
|
||||
maximum: 65535000
|
||||
description:
|
||||
Specifies the length of time (in ms) to wait for an event before moving
|
||||
from idle mode to low-power mode 1.
|
||||
|
||||
azoteq,timeout-lp1-ms:
|
||||
multipleOf: 1000
|
||||
minimum: 0
|
||||
maximum: 65535000
|
||||
description:
|
||||
Specifies the length of time (in ms) to wait for an event before moving
|
||||
from low-power mode 1 to low-power mode 2.
|
||||
|
||||
azoteq,timeout-lp2-ms:
|
||||
multipleOf: 1000
|
||||
minimum: 0
|
||||
maximum: 60000
|
||||
description:
|
||||
Specifies the rate (in ms) at which the trackpad reference values
|
||||
are updated during low-power modes 1 and 2.
|
||||
|
||||
azoteq,timeout-ati-ms:
|
||||
multipleOf: 1000
|
||||
minimum: 0
|
||||
maximum: 60000
|
||||
description:
|
||||
Specifies the delay (in ms) before the automatic tuning implementation
|
||||
(ATI) is retried in the event it fails to complete.
|
||||
|
||||
azoteq,timeout-comms-ms:
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description:
|
||||
Specifies the delay (in ms) before a communication window is closed.
|
||||
|
||||
azoteq,timeout-press-ms:
|
||||
multipleOf: 1000
|
||||
minimum: 0
|
||||
maximum: 60000
|
||||
description:
|
||||
Specifies the length of time (in ms) to wait before automatically
|
||||
releasing a press event. Specify zero to allow the press state to
|
||||
persist indefinitely.
|
||||
|
||||
azoteq,fosc-freq:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
description: |
|
||||
Specifies the device's core clock frequency as follows:
|
||||
0: 14 MHz
|
||||
1: 18 MHz
|
||||
|
||||
azoteq,fosc-trim:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description: Specifies the device's core clock frequency trim.
|
||||
|
||||
azoteq,num-contacts:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 2
|
||||
default: 0
|
||||
description: Specifies the number of contacts reported by the device.
|
||||
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||||
azoteq,contact-split:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the contact (finger) split factor.
|
||||
|
||||
azoteq,trim-x:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the horizontal trim width.
|
||||
|
||||
azoteq,trim-y:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
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||||
maximum: 255
|
||||
description: Specifies the vertical trim height.
|
||||
|
||||
trackpad:
|
||||
type: object
|
||||
description: Represents all channels associated with the trackpad.
|
||||
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||||
properties:
|
||||
azoteq,rx-enable:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
description:
|
||||
Specifies the order of the CRx pin(s) associated with the trackpad.
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||||
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||||
azoteq,tx-enable:
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||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 12
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 11
|
||||
description:
|
||||
Specifies the order of the CTx pin(s) associated with the trackpad.
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||||
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||||
azoteq,channel-select:
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||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: |
|
||||
Specifies the channels mapped to each cycle in the following order:
|
||||
Cycle 0, slot 0
|
||||
Cycle 0, slot 1
|
||||
Cycle 1, slot 0
|
||||
Cycle 1, slot 1
|
||||
...and so on. Specify 255 to disable a given slot.
|
||||
|
||||
azoteq,ati-frac-div-fine:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
description: Specifies the trackpad's ATI fine fractional divider.
|
||||
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||||
azoteq,ati-frac-mult-coarse:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description: Specifies the trackpad's ATI coarse fractional multiplier.
|
||||
|
||||
azoteq,ati-frac-div-coarse:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
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||||
maximum: 31
|
||||
description: Specifies the trackpad's ATI coarse fractional divider.
|
||||
|
||||
azoteq,ati-comp-div:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
description: Specifies the trackpad's ATI compensation divider.
|
||||
|
||||
azoteq,ati-target:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description: Specifies the trackpad's ATI target.
|
||||
|
||||
azoteq,touch-enter:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the trackpad's touch entrance factor.
|
||||
|
||||
azoteq,touch-exit:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the trackpad's touch exit factor.
|
||||
|
||||
azoteq,thresh:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the trackpad's stationary touch threshold.
|
||||
|
||||
azoteq,conv-period:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the trackpad's conversion period.
|
||||
|
||||
azoteq,conv-frac:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the trackpad's conversion frequency fraction.
|
||||
|
||||
patternProperties:
|
||||
"^event-(tap(-double|-triple)?|hold|palm|swipe-(x|y)-(pos|neg)(-hold)?)$":
|
||||
type: object
|
||||
$ref: ../input.yaml#
|
||||
description:
|
||||
Represents a gesture event reported by the trackpad. In the case of
|
||||
axial gestures, the duration or distance specified in one direction
|
||||
applies to both directions along the same axis.
|
||||
|
||||
properties:
|
||||
linux,code: true
|
||||
|
||||
azoteq,gesture-max-ms:
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description: Specifies the maximum duration of tap/swipe gestures.
|
||||
|
||||
azoteq,gesture-mid-ms:
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description:
|
||||
Specifies the maximum duration between subsequent tap gestures
|
||||
(IQS7211E only).
|
||||
|
||||
azoteq,gesture-min-ms:
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description: Specifies the minimum duration of hold gestures.
|
||||
|
||||
azoteq,gesture-dist:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description:
|
||||
Specifies the minimum (swipe) or maximum (tap and hold) distance
|
||||
a finger may travel to be considered a gesture.
|
||||
|
||||
azoteq,gesture-dist-rep:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description:
|
||||
Specifies the minimum distance a finger must travel to elicit a
|
||||
repeated swipe gesture (IQS7211E only).
|
||||
|
||||
azoteq,gesture-angle:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 75
|
||||
description:
|
||||
Specifies the maximum angle (in degrees) a finger may travel to
|
||||
be considered a swipe gesture.
|
||||
|
||||
azoteq,thresh:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 42
|
||||
description: Specifies the palm gesture threshold (IQS7211E only).
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
dependencies:
|
||||
azoteq,rx-enable: ["azoteq,tx-enable"]
|
||||
azoteq,tx-enable: ["azoteq,rx-enable"]
|
||||
azoteq,channel-select: ["azoteq,rx-enable"]
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
alp:
|
||||
type: object
|
||||
$ref: ../input.yaml#
|
||||
description: Represents the alternate low-power channel (ALP).
|
||||
|
||||
properties:
|
||||
azoteq,rx-enable:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
description:
|
||||
Specifies the CRx pin(s) associated with the ALP in no particular
|
||||
order.
|
||||
|
||||
azoteq,tx-enable:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 12
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 11
|
||||
description:
|
||||
Specifies the CTx pin(s) associated with the ALP in no particular
|
||||
order.
|
||||
|
||||
azoteq,ati-frac-div-fine:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
description: Specifies the ALP's ATI fine fractional divider.
|
||||
|
||||
azoteq,ati-frac-mult-coarse:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description: Specifies the ALP's ATI coarse fractional multiplier.
|
||||
|
||||
azoteq,ati-frac-div-coarse:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
description: Specifies the ALP's ATI coarse fractional divider.
|
||||
|
||||
azoteq,ati-comp-div:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
description: Specifies the ALP's ATI compensation divider.
|
||||
|
||||
azoteq,ati-target:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description: Specifies the ALP's ATI target.
|
||||
|
||||
azoteq,ati-base:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
multipleOf: 8
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the ALP's ATI base.
|
||||
|
||||
azoteq,ati-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
description: |
|
||||
Specifies the ALP's ATI mode as follows:
|
||||
0: Partial
|
||||
1: Full
|
||||
|
||||
azoteq,sense-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
description: |
|
||||
Specifies the ALP's sensing mode as follows:
|
||||
0: Self capacitive
|
||||
1: Mutual capacitive
|
||||
|
||||
azoteq,debounce-enter:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the ALP's debounce entrance factor.
|
||||
|
||||
azoteq,debounce-exit:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the ALP's debounce exit factor.
|
||||
|
||||
azoteq,thresh:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description: Specifies the ALP's proximity or touch threshold.
|
||||
|
||||
azoteq,conv-period:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the ALP's conversion period.
|
||||
|
||||
azoteq,conv-frac:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the ALP's conversion frequency fraction.
|
||||
|
||||
linux,code: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
button:
|
||||
type: object
|
||||
description: Represents the inductive or capacitive button.
|
||||
|
||||
properties:
|
||||
azoteq,ati-frac-div-fine:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
description: Specifies the button's ATI fine fractional divider.
|
||||
|
||||
azoteq,ati-frac-mult-coarse:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description: Specifies the button's ATI coarse fractional multiplier.
|
||||
|
||||
azoteq,ati-frac-div-coarse:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
description: Specifies the button's ATI coarse fractional divider.
|
||||
|
||||
azoteq,ati-comp-div:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
description: Specifies the button's ATI compensation divider.
|
||||
|
||||
azoteq,ati-target:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description: Specifies the button's ATI target.
|
||||
|
||||
azoteq,ati-base:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
multipleOf: 8
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the button's ATI base.
|
||||
|
||||
azoteq,ati-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
description: |
|
||||
Specifies the button's ATI mode as follows:
|
||||
0: Partial
|
||||
1: Full
|
||||
|
||||
azoteq,sense-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2]
|
||||
description: |
|
||||
Specifies the button's sensing mode as follows:
|
||||
0: Self capacitive
|
||||
1: Mutual capacitive
|
||||
2: Inductive
|
||||
|
||||
azoteq,touch-enter:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the button's touch entrance factor.
|
||||
|
||||
azoteq,touch-exit:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the button's touch exit factor.
|
||||
|
||||
azoteq,debounce-enter:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the button's debounce entrance factor.
|
||||
|
||||
azoteq,debounce-exit:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the button's debounce exit factor.
|
||||
|
||||
azoteq,thresh:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description: Specifies the button's proximity threshold.
|
||||
|
||||
azoteq,conv-period:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the button's conversion period.
|
||||
|
||||
azoteq,conv-frac:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the button's conversion frequency fraction.
|
||||
|
||||
patternProperties:
|
||||
"^event-(prox|touch)$":
|
||||
type: object
|
||||
$ref: ../input.yaml#
|
||||
description:
|
||||
Represents a proximity or touch event reported by the button.
|
||||
|
||||
properties:
|
||||
linux,code: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
wakeup-source: true
|
||||
|
||||
touchscreen-size-x: true
|
||||
touchscreen-size-y: true
|
||||
touchscreen-inverted-x: true
|
||||
touchscreen-inverted-y: true
|
||||
touchscreen-swapped-x-y: true
|
||||
|
||||
dependencies:
|
||||
touchscreen-size-x: ["azoteq,num-contacts"]
|
||||
touchscreen-size-y: ["azoteq,num-contacts"]
|
||||
touchscreen-inverted-x: ["azoteq,num-contacts"]
|
||||
touchscreen-inverted-y: ["azoteq,num-contacts"]
|
||||
touchscreen-swapped-x-y: ["azoteq,num-contacts"]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- irq-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: touchscreen.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: azoteq,iqs7210a
|
||||
|
||||
then:
|
||||
properties:
|
||||
alp:
|
||||
properties:
|
||||
azoteq,rx-enable:
|
||||
maxItems: 4
|
||||
items:
|
||||
minimum: 4
|
||||
|
||||
else:
|
||||
properties:
|
||||
azoteq,timeout-press-ms: false
|
||||
|
||||
alp:
|
||||
properties:
|
||||
azoteq,ati-mode: false
|
||||
|
||||
button: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: azoteq,iqs7211e
|
||||
|
||||
then:
|
||||
properties:
|
||||
reset-gpios: false
|
||||
|
||||
trackpad:
|
||||
properties:
|
||||
azoteq,tx-enable:
|
||||
maxItems: 13
|
||||
items:
|
||||
maximum: 12
|
||||
|
||||
alp:
|
||||
properties:
|
||||
azoteq,tx-enable:
|
||||
maxItems: 13
|
||||
items:
|
||||
maximum: 12
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
touch@56 {
|
||||
compatible = "azoteq,iqs7210a";
|
||||
reg = <0x56>;
|
||||
irq-gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
|
||||
reset-gpios = <&gpio 17 (GPIO_ACTIVE_LOW |
|
||||
GPIO_PUSH_PULL)>;
|
||||
azoteq,num-contacts = <2>;
|
||||
|
||||
trackpad {
|
||||
azoteq,rx-enable = <6>, <5>, <4>, <3>, <2>;
|
||||
azoteq,tx-enable = <1>, <7>, <8>, <9>, <10>;
|
||||
};
|
||||
|
||||
button {
|
||||
azoteq,sense-mode = <2>;
|
||||
azoteq,touch-enter = <40>;
|
||||
azoteq,touch-exit = <36>;
|
||||
|
||||
event-touch {
|
||||
linux,code = <KEY_HOME>;
|
||||
};
|
||||
};
|
||||
|
||||
alp {
|
||||
azoteq,sense-mode = <1>;
|
||||
linux,code = <KEY_POWER>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
touch@56 {
|
||||
compatible = "azoteq,iqs7211e";
|
||||
reg = <0x56>;
|
||||
irq-gpios = <&gpio 4 (GPIO_ACTIVE_LOW |
|
||||
GPIO_OPEN_DRAIN)>;
|
||||
|
||||
trackpad {
|
||||
event-tap {
|
||||
linux,code = <KEY_PLAYPAUSE>;
|
||||
};
|
||||
|
||||
event-tap-double {
|
||||
linux,code = <KEY_SHUFFLE>;
|
||||
};
|
||||
|
||||
event-tap-triple {
|
||||
linux,code = <KEY_AGAIN>;
|
||||
};
|
||||
|
||||
event-hold {
|
||||
linux,code = <KEY_STOP>;
|
||||
};
|
||||
|
||||
event-palm {
|
||||
linux,code = <KEY_EXIT>;
|
||||
};
|
||||
|
||||
event-swipe-x-pos {
|
||||
linux,code = <KEY_REWIND>;
|
||||
};
|
||||
|
||||
event-swipe-x-pos-hold {
|
||||
linux,code = <KEY_PREVIOUS>;
|
||||
};
|
||||
|
||||
event-swipe-x-neg {
|
||||
linux,code = <KEY_FASTFORWARD>;
|
||||
};
|
||||
|
||||
event-swipe-x-neg-hold {
|
||||
linux,code = <KEY_NEXT>;
|
||||
};
|
||||
|
||||
event-swipe-y-pos {
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
|
||||
event-swipe-y-pos-hold {
|
||||
linux,code = <KEY_MUTE>;
|
||||
};
|
||||
|
||||
event-swipe-y-neg {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
|
||||
event-swipe-y-neg-hold {
|
||||
linux,code = <KEY_MUTE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -99,7 +99,7 @@ SoCs:
|
||||
compatible = "qcom,diwali"
|
||||
|
||||
- PINEAPPLE
|
||||
compatible = "qcom,pineapple", "qcom,pineapplep"
|
||||
compatible = "qcom,pineapple", "qcom,pineapplep", "qcom,pineappleq"
|
||||
|
||||
- NEO
|
||||
compatible = "qcom,neo"
|
||||
|
||||
28
bindings/firmware/qcom,mem-object.yaml
Normal file
28
bindings/firmware/qcom,mem-object.yaml
Normal file
@@ -0,0 +1,28 @@
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/firmware/qcom,mem-object.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. Trusted execution environment memory object
|
||||
|
||||
description: |
|
||||
QTEE can shared memory over smcinvoke. This interface allows client to create
|
||||
a memory object that can be shared with QTEE.
|
||||
|
||||
maintainers:
|
||||
- Amirreza Zarrabi <azarrabi@qti.qualcomm.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mem-object
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
qcom_mem_object {
|
||||
compatible = "qcom,mem-object";
|
||||
};
|
||||
127
bindings/pinctrl/qcom,seraph-vm-pinctrl.yaml
Normal file
127
bindings/pinctrl/qcom,seraph-vm-pinctrl.yaml
Normal file
@@ -0,0 +1,127 @@
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,seraph-vm-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. SERAPH VM TLMM block
|
||||
|
||||
maintainers:
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block for VM.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,seraph-vm-pinctrl
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Base address of TLMM register space
|
||||
- description: Size of TLMM register space
|
||||
|
||||
interrupts-extended:
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: reference to the interrupts that match interrupt-names
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
const: 2
|
||||
|
||||
gpios:
|
||||
description: array of gpio pin number required by VM TLMM clients
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
|
||||
# PIN CONFIGURATION NODES
|
||||
patternPropetries:
|
||||
'^.*$':
|
||||
if:
|
||||
type: object
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in
|
||||
this subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])"
|
||||
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the
|
||||
specified pins. Functions are only valid for gpio pins.
|
||||
enum: [gpio, aon_cam, atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
|
||||
atest_usb0, atest_usb00, atest_usb01, atest_usb02, atest_usb03, audio_ref, cam_mclk,
|
||||
cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
|
||||
cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, coex_uart2, cri_trng, cri_trng0,
|
||||
cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1,
|
||||
gcc_gp2, gcc_gp3, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
|
||||
mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s2_data0, mi2s2_data1,
|
||||
mi2s2_sck, mi2s2_ws, mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
|
||||
mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7, mss_grfc8, mss_grfc9,
|
||||
nav_0, nav_1, nav_2, pcie0_clkreqn, pcie1_clkreqn, phase_flag0, phase_flag1,
|
||||
phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15,
|
||||
phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20,
|
||||
phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26,
|
||||
phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31,
|
||||
phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9, pll_bist,
|
||||
pll_clk, pri_mi2s, prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio,
|
||||
qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
|
||||
qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7,
|
||||
qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss, qlink1_enable,
|
||||
qlink1_request, qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
|
||||
qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15,
|
||||
qup16, qup17, qup18, qup19, qup2, qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8,
|
||||
qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd,
|
||||
sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1,
|
||||
tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
|
||||
uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac, usb_phy, vfr_0,
|
||||
vfr_1, vsense_trigger]
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
bias-disable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
tlmm: pinctrl@03000000 {
|
||||
compatible = "qcom,seraph-vm-pinctrl";
|
||||
reg = <0x03000000 0xdc2000>;
|
||||
interrupts-extended = <0 208 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpios = /bits/ 16 <0 1>;
|
||||
};
|
||||
@@ -13,8 +13,8 @@ add-overlays = $(foreach o,$1,$(foreach b,$2,$(eval $(basename $b)-$(basename $o
|
||||
|
||||
ifneq ($(CONFIG_ARCH_QTI_VM), y)
|
||||
|
||||
PINEAPPLE_BASE_DTB += pineapple-v2.dtb
|
||||
PINEAPPLE_APQ_BASE_DTB += pineapplep-v2.dtb pineapplep-sg-v2.dtb pineappleq-v2.dtb
|
||||
PINEAPPLE_BASE_DTB += pineapple-v2.dtb pineapple-qcm.dtb
|
||||
PINEAPPLE_APQ_BASE_DTB += pineapplep-v2.dtb pineapplep-sg-v2.dtb pineappleq-v2.dtb pineapplep-qcs.dtb
|
||||
|
||||
PINEAPPLE_BOARDS += \
|
||||
pineapple-mtp-overlay.dtbo \
|
||||
@@ -124,11 +124,13 @@ NIOBE_BOARDS += \
|
||||
niobe-atp-overlay.dtbo \
|
||||
niobe-idp-overlay.dtbo \
|
||||
niobe-idp-dpu-overlay.dtbo \
|
||||
niobe-idp-edp-overlay.dtbo \
|
||||
niobe-qxr-overlay.dtbo \
|
||||
niobep-atp-overlay.dtbo \
|
||||
niobep-idp-overlay.dtbo \
|
||||
niobep-idp-dpu-overlay.dtbo \
|
||||
niobep-idp-ihv-overlay.dtbo \
|
||||
niobep-idp-edp-overlay.dtbo \
|
||||
niobep-qxr-overlay.dtbo \
|
||||
niobep-qxr-vista-overlay.dtbo \
|
||||
niobep-qxr-vista-v2-overlay.dtbo
|
||||
@@ -329,6 +331,14 @@ dtb-y += $(niobe_tuivm-dtb-y)
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_SERAPH), y)
|
||||
ifeq ($(CONFIG_ARCH_QTI_VM), y)
|
||||
seraph_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += seraph-vm-rumi.dtb
|
||||
|
||||
dtb-y += $(seraph_tuivm-dtb-y)
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_CLIFFS), y)
|
||||
ifeq ($(CONFIG_ARCH_QTI_VM), y)
|
||||
pineapple_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += cliffs-vm-atp.dtb \
|
||||
@@ -507,6 +517,15 @@ MONACO_FLEX_LA_GVM_BASE_DTB += monaco-vm-flex-la.dtb
|
||||
MONACO_FLEX_LA_GVM_BOARDS += \
|
||||
monaco-vm-flex-la-overlay.dtbo
|
||||
|
||||
MONACO_MULTI_GVM_BASE_DTB += \
|
||||
monaco-vm-lv-mt.dtb \
|
||||
monaco-vm-la-mt.dtb
|
||||
|
||||
|
||||
MONACO_MULTI_GVM_BOARDS += \
|
||||
monaco-vm-lv-mt-overlay.dtbo \
|
||||
monaco-vm-la-mt-overlay.dtbo
|
||||
|
||||
autogvm-dtb-$(CONFIG_QTI_QUIN_GVM) += \
|
||||
$(call add-overlays, $(SA8155_LA_GVM_BOARDS),$(SA8155_LA_GVM_BASE_DTB)) \
|
||||
$(call add-overlays, $(SA6155P_LA_GVM_BOARDS),$(SA6155P_LA_GVM_BASE_DTB)) \
|
||||
@@ -521,7 +540,8 @@ autogvm-dtb-$(CONFIG_QTI_QUIN_GVM) += \
|
||||
$(call add-overlays, $(MONACO_LV_GVM_BOARDS),$(MONACO_LV_GVM_BASE_DTB)) \
|
||||
$(call add-overlays, $(MONACO_LA_GVM_BOARDS),$(MONACO_LA_GVM_BASE_DTB)) \
|
||||
$(call add-overlays, $(SA8155_MULTI_GVM_BOARDS),$(SA8155_MULTI_GVM_BASE_DTB)) \
|
||||
$(call add-overlays, $(MONACO_FLEX_LA_GVM_BOARDS),$(MONACO_FLEX_LA_GVM_BASE_DTB))
|
||||
$(call add-overlays, $(MONACO_FLEX_LA_GVM_BOARDS),$(MONACO_FLEX_LA_GVM_BASE_DTB)) \
|
||||
$(call add-overlays, $(MONACO_MULTI_GVM_BOARDS),$(MONACO_MULTI_GVM_BASE_DTB))
|
||||
|
||||
autogvm-overlays-dtb-$(CONFIG_QTI_QUIN_GVM) += \
|
||||
$(SA8155_LA_GVM_BOARDS) $(SA8155_LA_GVM_BASE_DTB) \
|
||||
@@ -537,7 +557,8 @@ autogvm-overlays-dtb-$(CONFIG_QTI_QUIN_GVM) += \
|
||||
$(MONACO_LV_GVM_BOARDS) $(MONACO_LV_GVM_BASE_DTB) \
|
||||
$(MONACO_LA_GVM_BOARDS) $(MONACO_LA_GVM_BASE_DTB) \
|
||||
$(SA8155_MULTI_GVM_BOARDS) $(SA8155_MULTI_GVM_BASE_DTB) \
|
||||
$(MONACO_FLEX_LA_GVM_BOARDS) $(MONACO_FLEX_LA_GVM_BASE_DTB)
|
||||
$(MONACO_FLEX_LA_GVM_BOARDS) $(MONACO_FLEX_LA_GVM_BASE_DTB) \
|
||||
$(MONACO_MULTI_GVM_BOARDS) $(MONACO_MULTI_GVM_BASE_DTB)
|
||||
|
||||
dtb-y += $(autogvm-dtb-y)
|
||||
|
||||
|
||||
@@ -879,6 +879,22 @@
|
||||
};
|
||||
};
|
||||
|
||||
virtio-mmio@36 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
generate = "/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x2>;
|
||||
push-compatible = "virtio,mmio";
|
||||
sync-reset;
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x1D6000>;
|
||||
memory {
|
||||
qcom,label = <0x124>;
|
||||
#address-cells = <0x2>;
|
||||
allocate-base;
|
||||
};
|
||||
};
|
||||
|
||||
swiotlb-shm {
|
||||
vdevice-type = "shm";
|
||||
generate = "/swiotlb";
|
||||
|
||||
@@ -53,6 +53,20 @@
|
||||
size = <0x0 0x1000000>;
|
||||
};
|
||||
|
||||
cp_pixel_mem: cp_pixel_region {
|
||||
no-map;
|
||||
qcom,target-vmid = <0xA>;
|
||||
qcom,label = <0xC0A>;
|
||||
qcom,unmapped;
|
||||
};
|
||||
|
||||
system_secure_mem: system_secure_region {
|
||||
no-map;
|
||||
qcom,label = <0xC09>;
|
||||
qcom,target-vmid = <0x9>;
|
||||
qcom,unmapped;
|
||||
};
|
||||
|
||||
kinfo_mem: debug_kinfo_region {
|
||||
alloc-ranges = <0x0 0x0 0xffffffff 0xffffffff>;
|
||||
size = <0x0 0x1000>;
|
||||
@@ -295,6 +309,7 @@
|
||||
qcom,secdomain-ids = <52 9 10>;
|
||||
qcom,primary-vm-index = <0>;
|
||||
vm-attrs = "guest-ram-dump", "vpm-virq";
|
||||
qcom,peripheral-vmids = <0x9 0xa>;
|
||||
|
||||
/* Pass through regions */
|
||||
iomemory-ranges = <
|
||||
@@ -331,6 +346,8 @@
|
||||
0x0 0x40000000 0x0 0x40000000 0x0 0x100000 0x0
|
||||
0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000 0x0
|
||||
0x4 0x10100000 0x4 0x10100000 0x0 0x100000 0x0
|
||||
/* EMAC1 CH4 region */
|
||||
0x0 0x2300C000 0x0 0x2300C000 0x0 0x1000 0x0
|
||||
>;
|
||||
|
||||
/* Pass through IRQs */
|
||||
@@ -352,6 +369,9 @@
|
||||
346 346
|
||||
406 406
|
||||
407 407
|
||||
/* EMAC1 CH4 GIC IRQ */
|
||||
808 808
|
||||
860 860
|
||||
>;
|
||||
|
||||
memory {
|
||||
@@ -1101,22 +1121,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
virtio-mmio@44 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
generate = "/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x2>;
|
||||
push-compatible = "virtio,mmio";
|
||||
sync-reset;
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x23A000>;
|
||||
memory {
|
||||
qcom,label = <0x4C>;
|
||||
#address-cells = <0x2>;
|
||||
allocate-base;
|
||||
};
|
||||
};
|
||||
|
||||
swiotlb-shm {
|
||||
vdevice-type = "shm";
|
||||
generate = "/swiotlb";
|
||||
@@ -1244,7 +1248,7 @@
|
||||
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
|
||||
<0x100 &pcie_smmu 0x0001 0x1>;
|
||||
|
||||
status = "disabled";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
soc: soc { };
|
||||
@@ -1324,6 +1328,20 @@
|
||||
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
|
||||
memory-region = <&qseecom_ta_mem>;
|
||||
};
|
||||
|
||||
qcom,cp_pixel {
|
||||
qcom,dma-heap-name = "qcom,secure-pixel";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_SECURE_CARVEOUT>;
|
||||
qcom,token = <0x80000>;
|
||||
memory-region = <&cp_pixel_mem>;
|
||||
};
|
||||
|
||||
qcom,cp_bitstream {
|
||||
qcom,dma-heap-name = "system-secure";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_SECURE_CARVEOUT>;
|
||||
qcom,token = <0x40000>;
|
||||
memory-region = <&system_secure_mem>;
|
||||
};
|
||||
};
|
||||
|
||||
tlmm: pinctrl@f000000 {
|
||||
@@ -1532,6 +1550,50 @@
|
||||
logbuf: qcom,logbuf-vendor-hooks {
|
||||
compatible = "qcom,logbuf-vendor-hooks";
|
||||
};
|
||||
|
||||
mtl_rx_setup: rx-queue-config {
|
||||
snps,rx-queues-to-use = <1>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue {
|
||||
snps,dcb-algorithm;
|
||||
snps,priority = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup: tx-queue-config {
|
||||
snps,tx-queues-to-use = <1>;
|
||||
snps,tx-sched-sp;
|
||||
queue {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
};
|
||||
|
||||
emac1_hw: qcom,ethernet@2300C000 {
|
||||
compatible = "qcom,stmmac-ethqos-emac1";
|
||||
emac-core-version = <0x30010000>;
|
||||
qcom,arm-smmu;
|
||||
reg = <0x2300C000 0x1000>;
|
||||
reg-names = "stmmaceth";
|
||||
status = "disabled";
|
||||
interrupts-extended = <&intc 0 776 4>, <&intc 0 828 4>;
|
||||
interrupt-names = "rx_ch0_intr", "tx_ch0_intr";
|
||||
snps,tso;
|
||||
snps,pbl = <32>;
|
||||
mac-address = [00 55 7B B5 7D f7];
|
||||
rx-fifo-depth = <4096>;
|
||||
tx-fifo-depth = <4096>;
|
||||
snps,mtl-rx-config = <&mtl_rx_setup>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup>;
|
||||
queue = <0>;
|
||||
emac1_emb_smmu: emac1_emb_smmu {
|
||||
compatible = "qcom,emac-thin-smmu-embedded";
|
||||
iommus = <&apps_smmu 0x148 0x1>;
|
||||
status = "disabled";
|
||||
qcom,iommu-dma = "fastmap";
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/ {
|
||||
|
||||
@@ -239,14 +239,16 @@
|
||||
"vdj", "vdk", "vdl",
|
||||
"vdm", "vdn", "vdo",
|
||||
"vdp", "vdq", "vdr",
|
||||
"vds", "vdt", "vdu";
|
||||
"vds", "vdt", "vdu",
|
||||
"vdv";
|
||||
rename-dev = "super", "userdata", "metadata",
|
||||
"persist", "modem_a","bluetooth_a",
|
||||
"misc", "vbmeta_a", "vbmeta_b",
|
||||
"boot_a", "dtbo_a", "dsp_a",
|
||||
"modem_b", "bluetooth_b", "boot_b",
|
||||
"dtbo_b", "dsp_b", "vendor_boot_b",
|
||||
"vendor_boot_a", "init_boot_b", "init_boot_a";
|
||||
"vendor_boot_a", "init_boot_b", "init_boot_a",
|
||||
"swap";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -40,6 +40,7 @@
|
||||
qcom,host-poweroff-in-pm-suspend;
|
||||
qcom,disable-host-ssphy-powerdown;
|
||||
qcom,disable-wakeup;
|
||||
qcom,hibernate-skip-thaw;
|
||||
|
||||
/*
|
||||
* Establish dependency on smmu driver so that depopulate path of
|
||||
@@ -272,6 +273,7 @@
|
||||
qcom,default-mode-host;
|
||||
qcom,disable-host-ssphy-powerdown;
|
||||
qcom,disable-wakeup;
|
||||
qcom,hibernate-skip-thaw;
|
||||
|
||||
/*
|
||||
* Establish dependency on smmu driver so that depopulate path of
|
||||
@@ -501,6 +503,7 @@
|
||||
qcom,host-poweroff-in-pm-suspend;
|
||||
qcom,default-mode-host;
|
||||
qcom,disable-wakeup;
|
||||
qcom,hibernate-skip-thaw;
|
||||
|
||||
/*
|
||||
* Establish dependency on smmu driver so that depopulate path of
|
||||
|
||||
@@ -257,23 +257,6 @@
|
||||
qcom,primary-vm-index = <0>;
|
||||
vm-attrs = "guest-ram-dump";
|
||||
|
||||
/* Pass through regions */
|
||||
iomemory-ranges = <
|
||||
/* QUPv3 Tile 0 read-only region */
|
||||
0x0 0x9c0000 0x0 0x9c0000 0x0 0x1000 0x1
|
||||
0x0 0x9c1000 0x0 0x9c1000 0x0 0x1000 0x1
|
||||
/* QUPv3 SE3 region */
|
||||
0x0 0x98c000 0x0 0x98c000 0x0 0x1000 0x0
|
||||
0x0 0x98d000 0x0 0x98d000 0x0 0x1000 0x0
|
||||
0x0 0x99e000 0x0 0x99e000 0x0 0x1000 0x0
|
||||
0x0 0x99f000 0x0 0x99f000 0x0 0x1000 0x0
|
||||
>;
|
||||
|
||||
gic-irq-ranges = <
|
||||
/* QUPv3 SE3 GIC IRQ */
|
||||
562 562
|
||||
>;
|
||||
|
||||
memory {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x0>;
|
||||
@@ -924,14 +907,6 @@
|
||||
allocate-base;
|
||||
};
|
||||
};
|
||||
|
||||
vsmmu@15000000 {
|
||||
vdevice-type = "vsmmu-v2";
|
||||
smmu-handle = <0x15000000>;
|
||||
num-cbs = <0x1>;
|
||||
num-smrs = <0x1>;
|
||||
patch = "/soc/apps-smmu@15000000";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
9
qcom/monaco-vm-la-mt-overlay.dts
Normal file
9
qcom/monaco-vm-la-mt-overlay.dts
Normal file
@@ -0,0 +1,9 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Monaco Multi LA Virtual Machine";
|
||||
compatible = "qcom,monaco", "qcom,quinvm";
|
||||
qcom,msm-id = <606 0x10000>;
|
||||
qcom,board-id = <0x0 0x2000001>;
|
||||
};
|
||||
10
qcom/monaco-vm-la-mt.dts
Normal file
10
qcom/monaco-vm-la-mt.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "monaco-vm.dtsi"
|
||||
#include "monaco-vm-la-mt.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Monaco Multi LA Virtual Machine";
|
||||
compatible = "qcom,monaco", "qcom,quinvm";
|
||||
qcom,board-id = <0x0 0x2000001>;
|
||||
};
|
||||
66
qcom/monaco-vm-la-mt.dtsi
Normal file
66
qcom/monaco-vm-la-mt.dtsi
Normal file
@@ -0,0 +1,66 @@
|
||||
&soc {
|
||||
};
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket kpti=0 arm64.nopauth kasan=off msm_show_resume_irq.debug_mask=1";
|
||||
bootconfig = "androidboot.usbcontroller=a600000.dwc3 androidboot.fstab_suffix=gen4.qcom";
|
||||
};
|
||||
|
||||
rename_devices: rename_devices {
|
||||
compatible = "qcom,rename-devices";
|
||||
rename_blk: rename_blk {
|
||||
device-type = "block";
|
||||
actual-dev = "vda", "vdb", "vdc",
|
||||
"vdd", "vde", "vdf",
|
||||
"vdg", "vdh", "vdi",
|
||||
"vdj", "vdk", "vdl",
|
||||
"vdm", "vdn", "vdo",
|
||||
"vdp", "vdq", "vdr",
|
||||
"vds", "vdt", "vdu";
|
||||
rename-dev = "super", "userdata", "metadata",
|
||||
"persist", "modem_a","bluetooth_a",
|
||||
"misc", "vbmeta_a", "vbmeta_b",
|
||||
"boot_a", "dtbo_a", "dsp_a",
|
||||
"modem_b", "bluetooth_b", "boot_b",
|
||||
"dtbo_b", "dsp_b", "vendor_boot_b",
|
||||
"vendor_boot_a", "init_boot_b", "init_boot_a";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hab {
|
||||
vmid = <2>;
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&pcie0_msi_snps {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb_qmp_phy0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&qupv3_se2_4uart {
|
||||
status = "ok";
|
||||
};
|
||||
9
qcom/monaco-vm-lv-mt-overlay.dts
Normal file
9
qcom/monaco-vm-lv-mt-overlay.dts
Normal file
@@ -0,0 +1,9 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Monaco Multi LV Virtual Machine";
|
||||
compatible = "qcom,monaco", "qcom,quinvm";
|
||||
qcom,msm-id = <606 0x10000>;
|
||||
qcom,board-id = <0x0 0x2000002>;
|
||||
};
|
||||
10
qcom/monaco-vm-lv-mt.dts
Normal file
10
qcom/monaco-vm-lv-mt.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "monaco-vm.dtsi"
|
||||
#include "monaco-vm-lv-mt.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Monaco Multi LV Virtual Machine";
|
||||
compatible = "qcom,monaco", "qcom,quinvm";
|
||||
qcom,board-id = <0x0 0x2000002>;
|
||||
};
|
||||
37
qcom/monaco-vm-lv-mt.dtsi
Normal file
37
qcom/monaco-vm-lv-mt.dtsi
Normal file
@@ -0,0 +1,37 @@
|
||||
&hab {
|
||||
vmid = <3>;
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
/delete-property/ qcom,host-poweroff-in-pm-suspend;
|
||||
/delete-property/ qcom,default-mode-host;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&pcie_smmu {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&qupv3_0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&qupv3_1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&glink_cma_mem0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&emac_ctrl_fe {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&qcom_rng_ee3 {
|
||||
status = "ok";
|
||||
};
|
||||
@@ -150,7 +150,7 @@
|
||||
qcom,ep-latency = <10>;
|
||||
qcom,core-preset = <0x77777777>;
|
||||
|
||||
qcom,pcie-phy-ver = <109>;
|
||||
qcom,pcie-phy-ver = <119>;
|
||||
qcom,phy-status-offset = <0x1214>;
|
||||
qcom,phy-status-bit = <7>;
|
||||
qcom,phy-power-down-offset = <0x1240>;
|
||||
@@ -197,20 +197,21 @@
|
||||
0x117c 0x06 0x0
|
||||
0x11a0 0x14 0x0
|
||||
0x11a8 0x0f 0x0
|
||||
0x0e4c 0xc0 0x0
|
||||
0x0220 0x16 0x0
|
||||
0x03c0 0x38 0x0
|
||||
0x0a20 0x16 0x0
|
||||
0x0bc0 0x38 0x0
|
||||
0x0360 0x9a 0x0
|
||||
0x0360 0x9b 0x0
|
||||
0x0364 0xb0 0x0
|
||||
0x0368 0x92 0x0
|
||||
0x0368 0xd2 0x0
|
||||
0x036c 0xf0 0x0
|
||||
0x0370 0x42 0x0
|
||||
0x0374 0x99 0x0
|
||||
0x0378 0x29 0x0
|
||||
0x037c 0x9a 0x0
|
||||
0x0374 0x00 0x0
|
||||
0x0378 0x20 0x0
|
||||
0x037c 0x9b 0x0
|
||||
0x0380 0xfb 0x0
|
||||
0x0384 0x92 0x0
|
||||
0x0384 0xd2 0x0
|
||||
0x0388 0xec 0x0
|
||||
0x038c 0x43 0x0
|
||||
0x0390 0xdd 0x0
|
||||
@@ -222,16 +223,16 @@
|
||||
0x03a8 0x83 0x0
|
||||
0x03ac 0xf5 0x0
|
||||
0x03b0 0x5e 0x0
|
||||
0x0b60 0x9a 0x0
|
||||
0x0b60 0x9b 0x0
|
||||
0x0b64 0xb0 0x0
|
||||
0x0b68 0x92 0x0
|
||||
0x0b68 0xd2 0x0
|
||||
0x0b6c 0xf0 0x0
|
||||
0x0b70 0x42 0x0
|
||||
0x0b74 0x99 0x0
|
||||
0x0b78 0x29 0x0
|
||||
0x0b7c 0x9a 0x0
|
||||
0x0b74 0x00 0x0
|
||||
0x0b78 0x20 0x0
|
||||
0x0b7c 0x9b 0x0
|
||||
0x0b80 0xfb 0x0
|
||||
0x0b84 0x92 0x0
|
||||
0x0b84 0xd2 0x0
|
||||
0x0b88 0xec 0x0
|
||||
0x0b8c 0x43 0x0
|
||||
0x0b90 0xdd 0x0
|
||||
@@ -305,10 +306,16 @@
|
||||
0x0034 0x07 0x0
|
||||
0x0830 0x1f 0x0
|
||||
0x0834 0x07 0x0
|
||||
0x12c4 0x80 0x0
|
||||
0x12c8 0x00 0x0
|
||||
0x13b8 0x80 0x0
|
||||
0x13bc 0x00 0x0
|
||||
0x141c 0xc1 0x0
|
||||
0x1490 0x00 0x0
|
||||
0x13e0 0x16 0x0
|
||||
0x13e4 0x22 0x0
|
||||
0x14f0 0x27 0x0
|
||||
0x14f4 0x27 0x0
|
||||
0x1508 0x02 0x0
|
||||
0x14a0 0x16 0x0
|
||||
0x1584 0x28 0x0
|
||||
@@ -471,7 +478,7 @@
|
||||
qcom,ep-latency = <10>;
|
||||
qcom,core-preset = <0x77777777>;
|
||||
|
||||
qcom,pcie-phy-ver = <1093>;
|
||||
qcom,pcie-phy-ver = <101>;
|
||||
qcom,phy-status-offset = <0x2214>;
|
||||
qcom,phy-status-bit = <7>;
|
||||
qcom,phy-power-down-offset = <0x2240>;
|
||||
@@ -538,17 +545,17 @@
|
||||
0x3c10 0x1f 0x0
|
||||
0x3c18 0x1f 0x0
|
||||
0x3c20 0x1f 0x0
|
||||
0x3c38 0x09 0x0
|
||||
0x3b60 0x99 0x0
|
||||
0x3c38 0x01 0x0
|
||||
0x3b60 0x9b 0x0
|
||||
0x3b64 0xb0 0x0
|
||||
0x3b68 0x92 0x0
|
||||
0x3b68 0xd2 0x0
|
||||
0x3b6c 0xf0 0x0
|
||||
0x3b70 0x42 0x0
|
||||
0x3b74 0x00 0x0
|
||||
0x3b78 0x20 0x0
|
||||
0x3b7c 0x9a 0x0
|
||||
0x3b7c 0x9b 0x0
|
||||
0x3b80 0xb6 0x0
|
||||
0x3b84 0x92 0x0
|
||||
0x3b84 0xd2 0x0
|
||||
0x3b88 0xf0 0x0
|
||||
0x3b8c 0x43 0x0
|
||||
0x3b90 0xdd 0x0
|
||||
@@ -575,8 +582,14 @@
|
||||
0x3830 0x1f 0x0
|
||||
0x241c 0xc1 0x0
|
||||
0x2490 0x00 0x0
|
||||
0x22c4 0x80 0x0
|
||||
0x22c8 0x00 0x0
|
||||
0x23b8 0x80 0x0
|
||||
0x23bc 0x00 0x0
|
||||
0x23e0 0x16 0x0
|
||||
0x23e4 0x22 0x0
|
||||
0x24f0 0x27 0x0
|
||||
0x24f4 0x27 0x0
|
||||
0x2508 0x02 0x0
|
||||
0x24a0 0x16 0x0
|
||||
0x2584 0x28 0x0
|
||||
|
||||
@@ -1,6 +1,76 @@
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
&soc {
|
||||
kgsl_smmu: kgsl-smmu@3da0000 {
|
||||
compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
|
||||
reg = <0x3da0000 0x40000>;
|
||||
#iommu-cells = <2>;
|
||||
qcom,use-3-lvl-tables;
|
||||
#global-interrupts = <1>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
ranges;
|
||||
dma-coherent;
|
||||
|
||||
status = "ok";
|
||||
|
||||
qcom,regulator-names = "vdd";
|
||||
vdd-supply = <&gpu_cc_cx_gdsc>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
|
||||
<&gpucc GPU_CC_HUB_AON_CLK>;
|
||||
|
||||
clock-names =
|
||||
"gpu_cc_hlos1_vote_gpu_smmu",
|
||||
"gcc_gpu_memnoc_gfx",
|
||||
"gpu_cc_ahb",
|
||||
"gpu_cc_hub_cx_int",
|
||||
"gpu_cc_hub_aon_clk";
|
||||
|
||||
qcom,actlr =
|
||||
/* All CBs of GFX: +15 deep PF */
|
||||
<0x000 0x3ff 0x32B>;
|
||||
|
||||
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gpu_qtb: gpu_qtb@3de8000 {
|
||||
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
|
||||
reg = <0x3de8000 0x1000>;
|
||||
qcom,stream-id-range = <0x0 0x400>;
|
||||
qcom,iova-width = <49>;
|
||||
interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>;
|
||||
qcom,num-qtb-ports = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
apps_smmu: apps-smmu@15000000 {
|
||||
compatible = "qcom,qsmmu-v500";
|
||||
reg = <0x15000000 0x100000>,
|
||||
@@ -13,6 +83,7 @@
|
||||
#address-cells = <1>;
|
||||
ranges;
|
||||
dma-coherent;
|
||||
qcom,handoff-smrs = <0x1c00 0x2>;
|
||||
|
||||
/* TODO: qcom,actlr */
|
||||
|
||||
@@ -224,5 +295,16 @@
|
||||
iommus = <&apps_smmu 0x400 0x0>;
|
||||
qcom,iommu-vmid = <0xa>; /* VMID_CP_PIXEL */
|
||||
};
|
||||
|
||||
usecase5_kgsl {
|
||||
compatible = "qcom,iommu-debug-usecase";
|
||||
iommus = <&kgsl_smmu 0x0007 0x0>;
|
||||
};
|
||||
|
||||
usecase6_kgsl_dma {
|
||||
compatible = "qcom,iommu-debug-usecase";
|
||||
iommus = <&kgsl_smmu 0x0007 0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
11
qcom/niobe-idp-edp-overlay.dts
Normal file
11
qcom/niobe-idp-edp-overlay.dts
Normal file
@@ -0,0 +1,11 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "niobe-idp-edp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Niobe IDP EDP";
|
||||
compatible = "qcom,niobe-idp", "qcom,niobe", "qcom,idp";
|
||||
qcom,msm-id = <629 0x10000>;
|
||||
qcom,board-id = <0x10022 3>;
|
||||
};
|
||||
11
qcom/niobe-idp-edp.dts
Normal file
11
qcom/niobe-idp-edp.dts
Normal file
@@ -0,0 +1,11 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "niobe.dtsi"
|
||||
#include "niobe-idp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Niobe IDP EDP";
|
||||
compatible = "qcom,niobe-idp", "qcom,niobe", "qcom,idp";
|
||||
qcom,board-id = <0x10022 3>;
|
||||
};
|
||||
1
qcom/niobe-idp-edp.dtsi
Normal file
1
qcom/niobe-idp-edp.dtsi
Normal file
@@ -0,0 +1 @@
|
||||
#include "niobe-idp.dtsi"
|
||||
@@ -2858,16 +2858,6 @@
|
||||
peer-name = <2>;
|
||||
};
|
||||
|
||||
hall_gpio {
|
||||
compatible = "qcom,hall-gpio";
|
||||
label = "hall_gpio";
|
||||
pinctrl-names = "sleep", "active";
|
||||
pinctrl-0 = <&hall_gpio_sleep>;
|
||||
pinctrl-1 = <&hall_gpio_active>;
|
||||
vdd-supply = <&L14B>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
pdm_pwm: pdm_pwm@8600000 {
|
||||
compatible = "qcom,pdm-pwm-v2";
|
||||
reg = <0x8600000 0x16000>;
|
||||
|
||||
11
qcom/niobep-idp-edp-overlay.dts
Normal file
11
qcom/niobep-idp-edp-overlay.dts
Normal file
@@ -0,0 +1,11 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "niobep-idp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. NiobeP IDP EDP";
|
||||
compatible = "qcom,niobep-idp", "qcom,niobep", "qcom,idp";
|
||||
qcom,msm-id = <652 0x10000>;
|
||||
qcom,board-id = <0x10022 3>;
|
||||
};
|
||||
11
qcom/niobep-idp-edp.dts
Normal file
11
qcom/niobep-idp-edp.dts
Normal file
@@ -0,0 +1,11 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "niobep.dtsi"
|
||||
#include "niobep-idp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. NiobeP IDP EDP";
|
||||
compatible = "qcom,niobep-idp", "qcom,niobep", "qcom,idp";
|
||||
qcom,board-id = <0x10022 3>;
|
||||
};
|
||||
1
qcom/niobep-idp-edp.dtsi
Normal file
1
qcom/niobep-idp-edp.dtsi
Normal file
@@ -0,0 +1 @@
|
||||
#include "niobe-idp.dtsi"
|
||||
@@ -1 +1,54 @@
|
||||
#include "niobep-qxr-vista.dtsi"
|
||||
|
||||
&tlmm {
|
||||
|
||||
/delete-node/ qupv3_se8_spi_pins;
|
||||
|
||||
qupv3_se8_spi_pins: qupv3_se8_spi_pins {
|
||||
qupv3_se8_spi_miso_active: qupv3_se8_spi_miso_active {
|
||||
mux {
|
||||
pins = "gpio16";
|
||||
function = "qup2_se4_l0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio16";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se8_spi_clk_active: qupv3_se8_spi_clk_active {
|
||||
mux {
|
||||
pins = "gpio18";
|
||||
function = "qup2_se4_l2";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio18";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
|
||||
mux {
|
||||
pins = "gpio16","gpio18";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio16","gpio18";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_se8_spi {
|
||||
/delete-property/ pinctrl-1;
|
||||
/delete-property/ pinctrl-0;
|
||||
pinctrl-0 = <&qupv3_se8_spi_miso_active>, <&qupv3_se8_spi_clk_active>;
|
||||
pinctrl-1 = <&qupv3_se8_spi_sleep>;
|
||||
};
|
||||
|
||||
@@ -47,12 +47,51 @@
|
||||
|
||||
&soc {
|
||||
gpio_keys {
|
||||
pinctrl-0 = <&key_vol_up_default
|
||||
&ipd_vol_up_default
|
||||
&ipd_vol_down_default>;
|
||||
pinctrl-0 = <&key_vol_up_default>;
|
||||
|
||||
/delete-node/ back_key;
|
||||
/delete-node/ confirm_key;
|
||||
/delete-node/ ipd_vol_up_default;
|
||||
/delete-node/ ipd_vol_down_default;
|
||||
/delete-node/ ipd_down;
|
||||
/delete-node/ ipd_up;
|
||||
|
||||
ipd_up {
|
||||
label = "ipd_wide";
|
||||
gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
|
||||
linux,input-type = <1>;
|
||||
linux,code = <KEY_KPPLUS>;
|
||||
gpio-key,wakeup;
|
||||
debounce-interval = <15>;
|
||||
linux,can-disable;
|
||||
};
|
||||
};
|
||||
|
||||
ipd-step-motor {
|
||||
status = "ok";
|
||||
compatible = "qcom,ipd_step_motor";
|
||||
label = "ipd-step-motor-dual";
|
||||
|
||||
pinctrl-names = "sleep", "default";
|
||||
pinctrl-0 = <&hall_gpio_sleep &hall2_gpio_sleep>;
|
||||
pinctrl-1 = <&hall_gpio_default &hall2_gpio_default>;
|
||||
vdd-supply = <&L14B>;
|
||||
|
||||
pwr-gpio = <&tlmm 11 0>;
|
||||
nsleep-gpio = <&tlmm 18 0>;
|
||||
|
||||
step-gpio-left = <&tlmm 5 0>;
|
||||
nen-gpio-left = <&tlmm 62 0>;
|
||||
dir-gpio-left = <&tlmm 26 0>;
|
||||
|
||||
step-gpio-right = <&tlmm 15 0>;
|
||||
nen-gpio-right = <&tlmm 29 0>;
|
||||
dir-gpio-right = <&tlmm 16 0>;
|
||||
|
||||
io-channels = <&pmk8550_vadc PMXR2230_ADC5_GEN3_AMUX_THM5>,
|
||||
<&pmk8550_vadc PMXR2230_ADC5_GEN3_AMUX_THM4>;
|
||||
io-channel-names = "ipd_step_motor_left",
|
||||
"ipd_step_motor_right";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -143,6 +182,102 @@
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_se9_i2c {
|
||||
status = "ok";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
touch: iqs7211e@56 {
|
||||
compatible = "azoteq,iqs7211e";
|
||||
reg = <0x56>;
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <141 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
|
||||
irq-gpios = <&tlmm 141 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
|
||||
touchscreen-size-x = <3840>;
|
||||
touchscreen-size-y = <3550>;
|
||||
azoteq,num-contacts = <1>;
|
||||
azoteq,forced-comms = <1>;
|
||||
|
||||
trackpad {
|
||||
azoteq,rx-enable = <4>, <1>, <0>;
|
||||
azoteq,tx-enable = <12>, <11>,<10>,<9>,<8>,<7>,<6>,<5>,<3>, <2>;
|
||||
azoteq,channel-select = <1>, <0>, <2>, <255>, <4>, <3>, <5>, <255>,
|
||||
<7>, <6>, <8>, <255>, <10>, <9>,<11>, <255>, <13>, <12>, <14>,
|
||||
<255>, <16>, <15>, <17>, <255>, <19>, <18>, <20>, <255>, <22>,
|
||||
<21>, <23>, <255>, <25>, <24>, <26>, <255>, <28>, <27>, <29>, <255>;
|
||||
azoteq,ati-frac-div-fine = <5>;
|
||||
azoteq,ati-frac-mult-coarse = <4>;
|
||||
azoteq,ati-frac-div-coarse = <1>;
|
||||
azoteq,ati-comp-div = <5>;
|
||||
azoteq,ati-target = <300>;
|
||||
azoteq,touch-enter = <20>;
|
||||
azoteq,touch-exit = <14>;
|
||||
|
||||
event-tap {
|
||||
linux,code = <KEY_PLAYPAUSE>;
|
||||
};
|
||||
|
||||
event-tap-double {
|
||||
linux,code = <KEY_SHUFFLE>;
|
||||
};
|
||||
|
||||
event-tap-triple {
|
||||
linux,code = <KEY_AGAIN>;
|
||||
};
|
||||
|
||||
event-hold {
|
||||
linux,code = <KEY_STOP>;
|
||||
};
|
||||
|
||||
event-palm {
|
||||
linux,code = <KEY_EXIT>;
|
||||
};
|
||||
|
||||
event-swipe-x-pos {
|
||||
linux,code = <KEY_REWIND>;
|
||||
};
|
||||
|
||||
event-swipe-x-pos-hold {
|
||||
linux,code = <KEY_PREVIOUS>;
|
||||
};
|
||||
|
||||
event-swipe-x-neg {
|
||||
linux,code = <KEY_FASTFORWARD>;
|
||||
};
|
||||
|
||||
event-swipe-x-neg-hold {
|
||||
linux,code = <KEY_NEXT>;
|
||||
};
|
||||
|
||||
event-swipe-y-pos {
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
|
||||
event-swipe-y-pos-hold {
|
||||
linux,code = <KEY_MUTE>;
|
||||
};
|
||||
|
||||
event-swipe-y-neg {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
|
||||
event-swipe-y-neg-hold {
|
||||
linux,code = <KEY_MUTE>;
|
||||
};
|
||||
};
|
||||
|
||||
alp {
|
||||
azoteq,rx-enable = <0>, <4>;
|
||||
azoteq,tx-enable = <12>, <11>, <10>, <9>, <8>, <7>, <6>, <5>, <3>, <2>;
|
||||
azoteq,ati-frac-div-fine = <1>;
|
||||
azoteq,ati-frac-mult-coarse = <1>;
|
||||
azoteq,ati-frac-div-coarse = <3>;
|
||||
azoteq,ati-comp-div = <2>;
|
||||
azoteq,ati-target = <200>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&thermal_zones {
|
||||
/delete-node/ sys-therm-5;
|
||||
|
||||
@@ -237,6 +372,62 @@
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
hall_gpio_default: hall_gpio_default {
|
||||
mux {
|
||||
pins = "gpio12";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio12";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
hall_gpio_sleep: hall_gpio_sleep {
|
||||
mux {
|
||||
pins = "gpio12";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio12";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
hall2_gpio_default: hall2_gpio_default {
|
||||
mux {
|
||||
pins = "gpio17";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio17";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
hall2_gpio_sleep: hall2_gpio_sleep {
|
||||
mux {
|
||||
pins = "gpio17";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio17";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_se1_spi {
|
||||
|
||||
@@ -6,6 +6,7 @@
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple CDP ST54L NFC";
|
||||
compatible = "qcom,pineapple-cdp", "qcom,pineapple", "qcom,pineapplep-cdp", "qcom,pineapplep", "qcom,cdp";
|
||||
qcom,msm-id = <557 0x20000>, <577 0x20000>, <682 0x20000>, <696 0x20000>;
|
||||
qcom,msm-id = <557 0x20000>, <577 0x20000>, <682 0x20000>, <696 0x20000>,
|
||||
<702 0x20000>;
|
||||
qcom,board-id = <0x50001 0>;
|
||||
};
|
||||
|
||||
@@ -6,6 +6,8 @@
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple CDP";
|
||||
compatible = "qcom,pineapple-cdp", "qcom,pineapple", "qcom,pineapplep-cdp", "qcom,pineapplep", "qcom,cdp";
|
||||
qcom,msm-id = <557 0x20000>, <577 0x20000>, <682 0x20000>, <696 0x20000>;
|
||||
qcom,msm-id = <557 0x20000>, <577 0x20000>, <682 0x20000>, <696 0x20000>,
|
||||
<645 0x10000>, <645 0x20000>, <646 0x10000>, <646 0x20000>,
|
||||
<702 0x10000>, <702 0x20000>;
|
||||
qcom,board-id = <1 0>, <0x01000001 0>;
|
||||
};
|
||||
|
||||
@@ -4395,9 +4395,9 @@
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
apss_pe0: cti@12010000 {
|
||||
apss_pe0: cti@120f0000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x12010000 0x1000>;
|
||||
reg = <0x120f0000 0x1000>;
|
||||
|
||||
arm,primecell-periphid = <0x000bb922>;
|
||||
coresight-name = "coresight-cti-apss_pe0";
|
||||
@@ -4406,9 +4406,9 @@
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
apss_pe1: cti@12020000 {
|
||||
apss_pe1: cti@12170000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x12020000 0x1000>;
|
||||
reg = <0x12170000 0x1000>;
|
||||
|
||||
arm,primecell-periphid = <0x000bb922>;
|
||||
coresight-name = "coresight-cti-apss_pe1";
|
||||
@@ -4417,9 +4417,9 @@
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
apss_pe2: cti@12030000 {
|
||||
apss_pe2: cti@121f0000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x12030000 0x1000>;
|
||||
reg = <0x121f0000 0x1000>;
|
||||
|
||||
arm,primecell-periphid = <0x000bb922>;
|
||||
coresight-name = "coresight-cti-apss_pe2";
|
||||
@@ -4428,9 +4428,9 @@
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
apss_pe3: cti@12040000 {
|
||||
apss_pe3: cti@12270000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x12040000 0x1000>;
|
||||
reg = <0x12270000 0x1000>;
|
||||
|
||||
arm,primecell-periphid = <0x000bb922>;
|
||||
coresight-name = "coresight-cti-apss_pe3";
|
||||
@@ -4439,9 +4439,9 @@
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
apss_pe4: cti@12050000 {
|
||||
apss_pe4: cti@122f0000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x12050000 0x1000>;
|
||||
reg = <0x122f0000 0x1000>;
|
||||
|
||||
arm,primecell-periphid = <0x000bb922>;
|
||||
coresight-name = "coresight-cti-apss_pe4";
|
||||
@@ -4450,9 +4450,9 @@
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
apss_pe5: cti@12060000 {
|
||||
apss_pe5: cti@12370000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x12060000 0x1000>;
|
||||
reg = <0x12370000 0x1000>;
|
||||
|
||||
arm,primecell-periphid = <0x000bb922>;
|
||||
coresight-name = "coresight-cti-apss_pe5";
|
||||
@@ -4461,9 +4461,9 @@
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
apss_pe6: cti@12070000 {
|
||||
apss_pe6: cti@123f0000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x12070000 0x1000>;
|
||||
reg = <0x123f0000 0x1000>;
|
||||
|
||||
arm,primecell-periphid = <0x000bb922>;
|
||||
coresight-name = "coresight-cti-apss_pe6";
|
||||
@@ -4472,9 +4472,9 @@
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
apss_pe7: cti@12080000 {
|
||||
apss_pe7: cti@12470000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x12080000 0x1000>;
|
||||
reg = <0x12470000 0x1000>;
|
||||
|
||||
arm,primecell-periphid = <0x000bb922>;
|
||||
coresight-name = "coresight-cti-apss_pe7";
|
||||
@@ -4483,9 +4483,9 @@
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
apss_cluster: cti@12230000 {
|
||||
apss_cluster: cti@12040000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x12230000 0x1000>;
|
||||
reg = <0x12040000 0x1000>;
|
||||
|
||||
arm,primecell-periphid = <0x000bb922>;
|
||||
coresight-name = "coresight-cti-apss_cluster";
|
||||
|
||||
@@ -6,6 +6,7 @@
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple MTP ST54L NFC";
|
||||
compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp";
|
||||
qcom,msm-id = <557 0x20000>, <577 0x20000>, <682 0x20000>, <696 0x20000>;
|
||||
qcom,msm-id = <557 0x20000>, <577 0x20000>, <682 0x20000>,
|
||||
<702 0x20000>, <696 0x20000>;
|
||||
qcom,board-id = <0x50008 0>;
|
||||
};
|
||||
|
||||
@@ -6,6 +6,8 @@
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple MTP";
|
||||
compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp";
|
||||
qcom,msm-id = <557 0x20000>, <577 0x20000>, <682 0x20000>, <696 0x20000>;
|
||||
qcom,msm-id = <557 0x20000>, <577 0x20000>, <682 0x20000>,
|
||||
<645 0x20000>, <646 0x20000>, <702 0x20000>,
|
||||
<696 0x20000>;
|
||||
qcom,board-id = <8 0>;
|
||||
};
|
||||
|
||||
9
qcom/pineapple-qcm.dts
Normal file
9
qcom/pineapple-qcm.dts
Normal file
@@ -0,0 +1,9 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "pineapple-qcm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple QCM SoC";
|
||||
compatible = "qcom,pineapple";
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
7
qcom/pineapple-qcm.dtsi
Normal file
7
qcom/pineapple-qcm.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
#include "pineapple-v2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple QCM";
|
||||
compatible = "qcom,pineapple";
|
||||
qcom,msm-id = <645 0x20000>;
|
||||
};
|
||||
@@ -6,6 +6,7 @@
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Pineapple RCM";
|
||||
compatible = "qcom,pineapple-rcm", "qcom,pineapple", "qcom,pineapplep-rcm", "qcom,pineapplep", "qcom,rcm";
|
||||
qcom,msm-id = <557 0x20000>, <577 0x20000>, <682 0x20000>, <696 0x20000>;
|
||||
qcom,msm-id = <557 0x20000>, <577 0x20000>, <682 0x20000>,
|
||||
<702 0x20000>, <696 0x20000>;
|
||||
qcom,board-id = <0x15 0>;
|
||||
};
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. PineappleP HDK";
|
||||
compatible = "qcom,pineapplep-hdk", "qcom,pineapplep", "qcom,hdk";
|
||||
qcom,msm-id = <577 0x20000>;
|
||||
qcom,msm-id = <577 0x20000>, <702 0x20000>;
|
||||
qcom,board-id = <0x1f 0>;
|
||||
};
|
||||
|
||||
|
||||
9
qcom/pineapplep-qcs.dts
Normal file
9
qcom/pineapplep-qcs.dts
Normal file
@@ -0,0 +1,9 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "pineapplep-qcs.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. PineappleP QCS SoC";
|
||||
compatible = "qcom,pineapplep";
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
7
qcom/pineapplep-qcs.dtsi
Normal file
7
qcom/pineapplep-qcs.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
#include "pineapplep-v2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. PineappleP QCS";
|
||||
compatible = "qcom,pineapplep";
|
||||
qcom,msm-id = <646 0x20000>, <702 0x20000>;
|
||||
};
|
||||
@@ -15,6 +15,8 @@ _platform_map = {
|
||||
{"name": "sa8195-vm-la.dtb"},
|
||||
{"name": "monaco-vm-la.dtb"},
|
||||
{"name": "monaco-vm-lv.dtb"},
|
||||
{"name": "monaco-vm-lv-mt.dtb"},
|
||||
{"name": "monaco-vm-la-mt.dtb"},
|
||||
{"name": "sa6155p-vm-la.dtb"},
|
||||
{"name": "monaco-vm-flex-la.dtb"},
|
||||
],
|
||||
@@ -33,6 +35,8 @@ _platform_map = {
|
||||
{"name": "sa8195-vm-la-overlay.dtbo"},
|
||||
{"name": "monaco-vm-la-overlay.dtbo"},
|
||||
{"name": "monaco-vm-lv-overlay.dtbo"},
|
||||
{"name": "monaco-vm-lv-mt-overlay.dtbo"},
|
||||
{"name": "monaco-vm-la-mt-overlay.dtbo"},
|
||||
{"name": "sa6155p-vm-la-overlay.dtbo"},
|
||||
{"name": "monaco-vm-flex-la-overlay.dtbo"},
|
||||
],
|
||||
@@ -178,6 +182,11 @@ _platform_map = {
|
||||
"name": "pineapplep-sg-v2.dtb",
|
||||
"apq": True,
|
||||
},
|
||||
{"name": "pineapple-qcm.dtb"},
|
||||
{
|
||||
"name": "pineapplep-qcs.dtb",
|
||||
"apq": True,
|
||||
},
|
||||
{
|
||||
"name": "pineappleq-v2.dtb",
|
||||
"apq": True,
|
||||
@@ -278,11 +287,13 @@ _platform_map = {
|
||||
{"name": "niobe-atp-overlay.dtbo"},
|
||||
{"name": "niobe-idp-overlay.dtbo"},
|
||||
{"name": "niobe-idp-dpu-overlay.dtbo"},
|
||||
{"name": "niobe-idp-edp-overlay.dtbo"},
|
||||
{"name": "niobe-qxr-overlay.dtbo"},
|
||||
{"name": "niobep-atp-overlay.dtbo"},
|
||||
{"name": "niobep-idp-overlay.dtbo"},
|
||||
{"name": "niobep-idp-dpu-overlay.dtbo"},
|
||||
{"name": "niobep-idp-ihv-overlay.dtbo"},
|
||||
{"name": "niobep-idp-edp-overlay.dtbo"},
|
||||
{"name": "niobep-qxr-overlay.dtbo"},
|
||||
{"name": "niobep-qxr-vista-overlay.dtbo"},
|
||||
{"name": "niobep-qxr-vista-v2-overlay.dtbo"},
|
||||
@@ -369,6 +380,11 @@ _platform_map = {
|
||||
{"name": "niobep-vm-idp.dtb"},
|
||||
],
|
||||
},
|
||||
"seraph-tuivm": {
|
||||
"dtb_list": [
|
||||
{"name": "seraph-vm-rumi.dtb"},
|
||||
],
|
||||
},
|
||||
"cliffs-tuivm": {
|
||||
"dtb_list": [
|
||||
{"name": "cliffs-vm-atp.dtb"},
|
||||
|
||||
@@ -73,7 +73,7 @@
|
||||
firmware: firmware {
|
||||
android {
|
||||
compatible = "android,firmware";
|
||||
boot_devices = "vdevs/1c140000.virtio_blk,vdevs/1c0b0000.virtio_blk,vdevs/1c0f0000.virtio_blk,vdevs/1c410000.virtio_blk,vdevs/1c130000.virtio_blk,vdevs/1c0e0000.virtio_blk,vdevs/1c100000.virtio_blk,vdevs/1c170000.virtio_blk,vdevs/1c180000.virtio_blk,vdevs/1c110000.virtio_blk,vdevs/1c120000.virtio_blk,vdevs/1c210000.virtio_blk,vdevs/1c220000.virtio_blk,vdevs/1c230000.virtio_blk,vdevs/1c240000.virtio_blk,vdevs/1c250000.virtio_blk,vdevs/1c260000.virtio_blk,vdevs/1c280000.virtio_blk,vdevs/1c290000.virtio_blk,vdevs/1c310000.virtio_blk,vdevs/1c320000.virtio_blk";
|
||||
boot_devices = "vdevs/1c140000.virtio_blk,vdevs/1c0b0000.virtio_blk,vdevs/1c0f0000.virtio_blk,vdevs/1c410000.virtio_blk,vdevs/1c130000.virtio_blk,vdevs/1c0e0000.virtio_blk,vdevs/1c100000.virtio_blk,vdevs/1c170000.virtio_blk,vdevs/1c180000.virtio_blk,vdevs/1c110000.virtio_blk,vdevs/1c120000.virtio_blk,vdevs/1c210000.virtio_blk,vdevs/1c220000.virtio_blk,vdevs/1c230000.virtio_blk,vdevs/1c240000.virtio_blk,vdevs/1c250000.virtio_blk,vdevs/1c260000.virtio_blk,vdevs/1c280000.virtio_blk,vdevs/1c290000.virtio_blk,vdevs/1c310000.virtio_blk,vdevs/1c320000.virtio_blk,vdevs/1c330000.virtio_blk";
|
||||
|
||||
vbmeta {
|
||||
compatible = "android,vbmeta";
|
||||
|
||||
@@ -39,6 +39,16 @@
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0x1000000>;
|
||||
};
|
||||
|
||||
glink_cma_mem1: glink-cma-region@1 {
|
||||
no-map;
|
||||
qcom,label = <0x60>;
|
||||
};
|
||||
|
||||
glink_cma_mem2: glink-cma-region@2 {
|
||||
no-map;
|
||||
qcom,label = <0x61>;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
@@ -1164,6 +1174,28 @@
|
||||
default_iocoherency;
|
||||
db-off;
|
||||
};
|
||||
|
||||
scmi {
|
||||
compatible = "arm,scmi-virtio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "ok";
|
||||
|
||||
scmi_power: protocol@11 {
|
||||
reg = <0x11>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
scmi_perf: protocol@13 {
|
||||
reg = <0x13>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
scmi_reset: protocol@16 {
|
||||
reg = <0x16>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/ {
|
||||
|
||||
@@ -4,5 +4,17 @@
|
||||
qcom,dma-heaps {
|
||||
compatible = "qcom,dma-heaps";
|
||||
};
|
||||
|
||||
qcom,qseecom {
|
||||
qcom,dma-heap-name = "qcom,qseecom";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
|
||||
memory-region = <&qseecom_mem>;
|
||||
};
|
||||
|
||||
qcom,qseecom_ta {
|
||||
qcom,dma-heap-name = "qcom,qseecom-ta";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
|
||||
memory-region = <&qseecom_ta_mem>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,4 +1,458 @@
|
||||
&soc {
|
||||
/* QUPv3 SE Instances
|
||||
* QUP0 0: SE 0
|
||||
* QUP0 1: SE 1
|
||||
* QUP0 2: SE 2
|
||||
* QUP0 3: SE 3
|
||||
* QUP0 4: SE 4
|
||||
* QUP0 5: SE 5
|
||||
* Qup1 0: SE 6
|
||||
* Qup1 1: SE 7
|
||||
* Qup1 2: SE 8
|
||||
* Qup1 3: SE 9
|
||||
* Qup1 4: SE 10
|
||||
* Qup1 5: SE 11
|
||||
*/
|
||||
|
||||
/* GPI Instance */
|
||||
gpi_dma0: qcom,gpi-dma@800000 {
|
||||
compatible = "qcom,gpi-dma";
|
||||
#dma-cells = <5>;
|
||||
reg = <0x800000 0x60000>;
|
||||
reg-names = "gpi-top";
|
||||
iommus = <&apps_smmu 0x1b6 0x0>;
|
||||
qcom,max-num-gpii = <16>;
|
||||
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,gpii-mask = <0x3f>;
|
||||
qcom,ev-factor = <1>;
|
||||
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
|
||||
qcom,gpi-ee-offset = <0x10000>;
|
||||
dma-coherent;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
/* QUPv3_0 wrapper instance */
|
||||
qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x8c0000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0x1a3 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
||||
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
||||
qcom,iommu-dma = "fastmap";
|
||||
dma-coherent;
|
||||
ranges;
|
||||
status = "ok";
|
||||
|
||||
qupv3_se0_i2c: i2c@880000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x880000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 0 3 64 0>,
|
||||
<&gpi_dma0 1 0 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se0_spi: spi@880000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x880000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
|
||||
<&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se0_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 0 1 64 0>,
|
||||
<&gpi_dma0 1 0 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* I3C Instance */
|
||||
i3c0: i3c-master@880000 {
|
||||
compatible = "qcom,geni-i3c";
|
||||
reg = <0x880000 0x4000>,
|
||||
<0xec90000 0x10000>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep", "disable";
|
||||
pinctrl-0 = <&qupv3_se0_i3c_sda_active>, <&qupv3_se0_i3c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se0_i3c_sda_sleep>, <&qupv3_se0_i3c_scl_sleep>;
|
||||
pinctrl-2 = <&qupv3_se0_i3c_disable>;
|
||||
interrupts-extended = <&intc GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 61 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
qcom,ibi-ctrl-id = <1>;
|
||||
dmas = <&gpi_dma0 0 0 4 64 0>,
|
||||
<&gpi_dma0 1 0 4 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se1_i2c: i2c@884000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x884000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 1 3 64 0>,
|
||||
<&gpi_dma0 1 1 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se1_spi: spi@884000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x884000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
|
||||
<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se1_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 1 1 64 0>,
|
||||
<&gpi_dma0 1 1 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se2_i2c: i2c@888000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x888000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se2_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 2 3 64 0>,
|
||||
<&gpi_dma0 1 2 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se2_spi: spi@888000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x888000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>,
|
||||
<&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se2_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 2 1 64 0>,
|
||||
<&gpi_dma0 1 2 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se3_i2c: i2c@88c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x88c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se3_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 3 3 64 0>,
|
||||
<&gpi_dma0 1 3 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se3_spi: spi@88c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x88c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>,
|
||||
<&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se3_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 3 1 64 0>,
|
||||
<&gpi_dma0 1 3 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*UART 2 wire Instance */
|
||||
qupv3_se3_2uart: qcom,qup_uart@88c000 {
|
||||
compatible = "qcom,msm-geni-serial-hs";
|
||||
reg = <0x88c000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se3_2uart_tx_active>, <&qupv3_se3_2uart_rx_active>;
|
||||
pinctrl-1 = <&qupv3_se3_2uart_sleep>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se4_i2c: i2c@890000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x890000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 4 3 64 0>,
|
||||
<&gpi_dma0 1 4 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se4_spi: spi@890000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x890000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
|
||||
<&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se4_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 4 1 64 0>,
|
||||
<&gpi_dma0 1 4 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* I3C Instance */
|
||||
i3c1: i3c-master@890000 {
|
||||
compatible = "qcom,geni-i3c";
|
||||
reg = <0x890000 0x4000>,
|
||||
<0xeca0000 0x10000>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep", "disable";
|
||||
pinctrl-0 = <&qupv3_se4_i3c_sda_active>, <&qupv3_se4_i3c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se4_i3c_sda_sleep>, <&qupv3_se4_i3c_scl_sleep>;
|
||||
pinctrl-2 = <&qupv3_se4_i3c_disable>;
|
||||
interrupts-extended = <&intc GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 62 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
qcom,ibi-ctrl-id = <2>;
|
||||
dmas = <&gpi_dma0 0 4 4 64 0>,
|
||||
<&gpi_dma0 1 4 4 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se5_i2c: i2c@894000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x894000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 5 3 64 0>,
|
||||
<&gpi_dma0 1 5 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se5_spi: spi@894000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x894000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>,
|
||||
<&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se5_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 5 1 64 0>,
|
||||
<&gpi_dma0 1 5 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
/* GPI Instance */
|
||||
gpi_dma1: qcom,gpi-dma@a00000 {
|
||||
compatible = "qcom,gpi-dma";
|
||||
#dma-cells = <5>;
|
||||
reg = <0xa00000 0x60000>;
|
||||
reg-names = "gpi-top";
|
||||
iommus = <&apps_smmu 0x36 0x0>;
|
||||
qcom,max-num-gpii = <16>;
|
||||
interrupts = <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,gpii-mask = <0x3f>;
|
||||
qcom,ev-factor = <1>;
|
||||
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
|
||||
qcom,gpi-ee-offset = <0x10000>;
|
||||
dma-coherent;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
/* QUPv3_1 wrapper instance */
|
||||
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
@@ -8,9 +462,310 @@
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0x23 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
||||
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
||||
qcom,iommu-dma = "fastmap";
|
||||
dma-coherent;
|
||||
ranges;
|
||||
status = "ok";
|
||||
|
||||
qupv3_se6_i2c: i2c@a80000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa80000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_1>,
|
||||
<&system_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 0 3 64 0>,
|
||||
<&gpi_dma1 1 0 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se6_spi: spi@a80000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa80000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_1>,
|
||||
<&system_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
|
||||
<&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se6_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 0 1 64 0>,
|
||||
<&gpi_dma1 1 0 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* I3C Instance */
|
||||
i3c2: i3c-master@a80000 {
|
||||
compatible = "qcom,geni-i3c";
|
||||
reg = <0xa80000 0x4000>,
|
||||
<0xecb0000 0x10000>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_1>,
|
||||
<&system_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep", "disable";
|
||||
pinctrl-0 = <&qupv3_se6_i3c_sda_active>, <&qupv3_se6_i3c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se6_i3c_sda_sleep>, <&qupv3_se6_i3c_scl_sleep>;
|
||||
pinctrl-2 = <&qupv3_se6_i3c_disable>;
|
||||
interrupts-extended = <&intc GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 63 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
qcom,ibi-ctrl-id = <3>;
|
||||
dmas = <&gpi_dma1 0 0 4 1024 0>,
|
||||
<&gpi_dma1 1 0 4 1024 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se7_spi: spi@a84000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa84000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_1>,
|
||||
<&system_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se7_spi_mosi_active>, <&qupv3_se7_spi_miso_active>,
|
||||
<&qupv3_se7_spi_clk_active>, <&qupv3_se7_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se7_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 1 1 64 0>,
|
||||
<&gpi_dma1 1 1 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* HS UART Instance */
|
||||
qupv3_se7_4uart: qcom,qup_uart@a84000 {
|
||||
compatible = "qcom,msm-geni-serial-hs";
|
||||
reg = <0xa84000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts-extended = <&intc GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&tlmm 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_1>,
|
||||
<&system_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "active", "sleep", "shutdown";
|
||||
pinctrl-0 = <&qupv3_se7_default_cts>, <&qupv3_se7_default_rts>,
|
||||
<&qupv3_se7_default_tx>, <&qupv3_se7_default_rx>;
|
||||
pinctrl-1 = <&qupv3_se7_cts>, <&qupv3_se7_rts>,
|
||||
<&qupv3_se7_tx>, <&qupv3_se7_rx>;
|
||||
pinctrl-2 = <&qupv3_se7_cts>, <&qupv3_se7_rts>,
|
||||
<&qupv3_se7_tx>, <&qupv3_se7_default_rx>;
|
||||
pinctrl-3 = <&qupv3_se7_default_cts>, <&qupv3_se7_default_rts>,
|
||||
<&qupv3_se7_default_tx>, <&qupv3_se7_default_rx>;
|
||||
qcom,wakeup-byte = <0xFD>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se8_i2c: i2c@a88000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa88000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_1>,
|
||||
<&system_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 2 3 64 0>,
|
||||
<&gpi_dma1 1 2 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se8_spi: spi@a88000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa88000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_1>,
|
||||
<&system_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>,
|
||||
<&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se8_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 2 1 64 0>,
|
||||
<&gpi_dma1 1 2 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se9_i2c: i2c@a8c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa8c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_1>,
|
||||
<&system_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 3 3 64 0>,
|
||||
<&gpi_dma1 1 3 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se9_spi: spi@a8c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa8c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_1>,
|
||||
<&system_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>,
|
||||
<&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se9_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 3 1 64 0>,
|
||||
<&gpi_dma1 1 3 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se10_i2c: i2c@a90000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa90000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_1>,
|
||||
<&system_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se10_i2c_sda_active>, <&qupv3_se10_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se10_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 4 3 64 0>,
|
||||
<&gpi_dma1 1 4 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se10_spi: spi@a90000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa90000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_1>,
|
||||
<&system_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se10_spi_mosi_active>, <&qupv3_se10_spi_miso_active>,
|
||||
<&qupv3_se10_spi_clk_active>, <&qupv3_se10_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se10_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 4 1 64 0>,
|
||||
<&gpi_dma1 1 4 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* I3C Instance */
|
||||
i3c3: i3c-master@a90000 {
|
||||
compatible = "qcom,geni-i3c";
|
||||
reg = <0xa90000 0x4000>,
|
||||
<0xecc0000 0x10000>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_1>,
|
||||
<&system_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep", "disable";
|
||||
pinctrl-0 = <&qupv3_se10_i3c_sda_active>, <&qupv3_se10_i3c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se10_i3c_sda_sleep>, <&qupv3_se10_i3c_scl_sleep>;
|
||||
pinctrl-2 = <&qupv3_se10_i3c_disable>;
|
||||
interrupts-extended = <&intc GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 64 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
qcom,ibi-ctrl-id = <4>;
|
||||
dmas = <&gpi_dma1 0 4 4 64 0>,
|
||||
<&gpi_dma1 1 4 4 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Debug UART Instance */
|
||||
qupv3_se11_2uart: qcom,qup_uart@a94000 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
@@ -19,6 +774,11 @@
|
||||
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_QUP_1>,
|
||||
<&system_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se11_2uart_tx_active>, <&qupv3_se11_2uart_rx_active>;
|
||||
pinctrl-1 = <&qupv3_se11_2uart_sleep>;
|
||||
|
||||
@@ -224,10 +224,19 @@
|
||||
reg = <0x0 0xf7c00000 0x0 0x4c00000>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
llcc_lpi_mem: llcc_lpi_region@fc000000 {
|
||||
no-map;
|
||||
reg = <0x0 0xfc000000 0x0 0xc00000>;
|
||||
};
|
||||
|
||||
vm_comm_mem: vm_comm_mem_region {
|
||||
compatible = "shared-dma-pool";
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0x400000>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -29,6 +29,26 @@
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
status = "ok";
|
||||
|
||||
qcom,iommu-dma = "bypass";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_on>;
|
||||
pinctrl-1 = <&sdc1_off>;
|
||||
|
||||
vdd-supply = <&L11A>;
|
||||
qcom,vdd-voltage-level = <2952000 2952000>;
|
||||
qcom,vdd-current-level = <0 570000>;
|
||||
|
||||
vdd-io-supply = <&L4A>;
|
||||
qcom,vdd-io-always-on;
|
||||
qcom,vdd-io-lpm-sup;
|
||||
qcom,vdd-io-voltage-level = <1800000 1800000>;
|
||||
qcom,vdd-io-current-level = <0 325000>;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
dwc3@a600000 {
|
||||
usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
|
||||
|
||||
31
qcom/seraph-vm-dma-heaps.dtsi
Normal file
31
qcom/seraph-vm-dma-heaps.dtsi
Normal file
@@ -0,0 +1,31 @@
|
||||
#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
|
||||
|
||||
&soc {
|
||||
qcom,dma-heaps {
|
||||
compatible = "qcom,dma-heaps";
|
||||
|
||||
qcom,tui {
|
||||
qcom,dma-heap-name = "qcom,tui";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_TUI_CARVEOUT>;
|
||||
qcom,dynamic-heap;
|
||||
};
|
||||
|
||||
qcom,ms1 {
|
||||
qcom,dma-heap-name = "qcom,ms1";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_TUI_CARVEOUT>;
|
||||
qcom,dynamic-heap;
|
||||
};
|
||||
|
||||
qcom,ms2 {
|
||||
qcom,dma-heap-name = "qcom,ms2";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_TUI_CARVEOUT>;
|
||||
qcom,dynamic-heap;
|
||||
};
|
||||
|
||||
qcom,ms3 {
|
||||
qcom,dma-heap-name = "qcom,ms3";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_TUI_CARVEOUT>;
|
||||
qcom,dynamic-heap;
|
||||
};
|
||||
};
|
||||
};
|
||||
10
qcom/seraph-vm-rumi.dts
Normal file
10
qcom/seraph-vm-rumi.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "seraph-vm.dtsi"
|
||||
#include "seraph-vm-rumi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Seraph SVM RUMI";
|
||||
compatible = "qcom,seraph-rumi", "qcom,seraph", "qcom,seraph";
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
3
qcom/seraph-vm-rumi.dtsi
Normal file
3
qcom/seraph-vm-rumi.dtsi
Normal file
@@ -0,0 +1,3 @@
|
||||
&arch_timer {
|
||||
clock-frequency = <500000>;
|
||||
};
|
||||
432
qcom/seraph-vm.dtsi
Normal file
432
qcom/seraph-vm.dtsi
Normal file
@@ -0,0 +1,432 @@
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-seraph.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
qcom,msm-id = <672 0x10000>;
|
||||
interrupt-parent = <&vgic>;
|
||||
chosen {
|
||||
bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x0>;
|
||||
CPU0: cpu@0 {
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_PWR_DWN
|
||||
&CLUSTER_PWR_DWN>;
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_PWR_DWN
|
||||
&CLUSTER_PWR_DWN>;
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */
|
||||
compatible = "arm,idle-state";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */
|
||||
compatible = "arm,idle-state";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dmesg-dump {
|
||||
compatible = "qcom,dmesg-dump";
|
||||
gunyah-label = <7>;
|
||||
ddump-pubkey-size = <270>;
|
||||
ddump-pubkey = /bits/ 8 <0x30 0x82 0x01 0x0a 0x02 0x82 0x01 0x01 0x00 0xe6 0x4b 0x31 0x82 0x61 0x14 0xf2
|
||||
0xbe 0xd1 0xe4 0xde 0xe7 0xed 0xba 0x8f 0x3b 0x23 0x5f 0x7a 0xb8 0x16 0x40 0x96
|
||||
0xae 0x77 0x5e 0x1b 0xf0 0x3f 0x39 0xab 0x69 0x90 0xb1 0xd4 0x70 0xcb 0x66 0xbc
|
||||
0x41 0x08 0x1d 0x37 0xdb 0x49 0xc8 0x49 0x5b 0x99 0x5c 0x32 0xbe 0x62 0xd5 0xa7
|
||||
0x3c 0x0f 0xa4 0x4b 0x43 0x49 0xdb 0x54 0x69 0x06 0x0c 0xe5 0x99 0xe5 0xf9 0x1e
|
||||
0x25 0x84 0x17 0x47 0x62 0x2b 0x5d 0x0d 0xec 0x5e 0xc6 0xb5 0x86 0xb9 0x75 0x6d
|
||||
0xfe 0x7d 0x35 0x4f 0x35 0xc1 0x48 0x10 0x75 0x4c 0x57 0x6b 0x46 0x4b 0xff 0x5b
|
||||
0x52 0x22 0x40 0x2c 0xb0 0x47 0xe1 0x47 0xc4 0xe5 0x47 0x0c 0x56 0xe8 0x17 0xd0
|
||||
0x7e 0xc3 0x4d 0x9f 0xea 0xd0 0xea 0x87 0xe5 0x51 0x39 0xe8 0x45 0x4c 0x54 0x27
|
||||
0x9c 0x50 0x38 0xb7 0x72 0x93 0x12 0x0b 0xa1 0x2f 0x9e 0x04 0x92 0x20 0x6e 0x31
|
||||
0x42 0x87 0xe1 0xfe 0x88 0x3f 0xe5 0x09 0xe1 0xf9 0xbe 0x44 0xc6 0xbf 0x10 0x79
|
||||
0x36 0x47 0x7b 0xa0 0x8e 0x27 0x31 0xa3 0x70 0x69 0x01 0x54 0x92 0xf4 0x42 0xbd
|
||||
0xcd 0x7e 0x79 0x2b 0x2c 0xe1 0xd4 0xba 0x6e 0x34 0xc6 0xe6 0xc6 0x5c 0x63 0xd0
|
||||
0x7f 0x39 0x1f 0xe8 0x8d 0x67 0xe6 0x27 0x67 0x0d 0x16 0x57 0x94 0xd1 0xfb 0xdf
|
||||
0xce 0xaf 0xfd 0x43 0xb3 0xbe 0x5d 0x83 0x4b 0x93 0x05 0xe8 0xdf 0x04 0xad 0xac
|
||||
0xeb 0xa6 0x81 0xa7 0xd5 0x04 0x63 0xbf 0x83 0xb8 0x0c 0xbc 0x20 0x18 0xb5 0x50
|
||||
0xd7 0x61 0x84 0x11 0xca 0x2d 0x22 0xb3 0x29 0x02 0x03 0x01 0x00 0x01>;
|
||||
};
|
||||
|
||||
qcom,vm-config {
|
||||
compatible = "qcom,vm-1.0";
|
||||
vm-type = "aarch64-guest";
|
||||
boot-config = "fdt,unified";
|
||||
os-type = "linux";
|
||||
kernel-entry-segment = "kernel";
|
||||
kernel-entry-offset = <0x0 0x0>;
|
||||
vendor = "QTI";
|
||||
image-name = "qcom,trustedvm";
|
||||
qcom,pasid = <0x0 0x1c>;
|
||||
qcom,qtee-config-info = "p=3,9,C,39,77,78,7C,8F,96,97,C8,FE,10C,11B,159,199,47E,7F1,CDF;";
|
||||
qcom,secdomain-ids = <45>;
|
||||
qcom,primary-vm-index = <0>;
|
||||
vm-uri = "vmuid/trusted-ui";
|
||||
vm-guid = "598085da-c516-5b25-a9c1-927a02819770";
|
||||
qcom,sensitive;
|
||||
vm-attrs = "context-dump", "crash-restart";
|
||||
/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
|
||||
* QUP1_SE4: GPII5 : IRQ_316
|
||||
* QUP2_SE7: GPII5 : IRQ_625
|
||||
*
|
||||
if you need this, add IRQ here
|
||||
gic-irq-ranges = <316 316
|
||||
625 625
|
||||
279 279>;
|
||||
*/
|
||||
gic-irq-ranges = <>;
|
||||
memory {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x0>;
|
||||
/*
|
||||
* IPA address linux image is loaded at. Must be within
|
||||
* first 1GB due to memory hotplug requirement.
|
||||
*/
|
||||
base-address = <0x0 0x88800000 >;
|
||||
};
|
||||
|
||||
segments {
|
||||
config_cpio = <2>;
|
||||
};
|
||||
|
||||
vcpus {
|
||||
config = "/cpus";
|
||||
affinity = "proxy";
|
||||
affinity-map = <0x0 0x0>;
|
||||
sched-priority = <0>; /* relative to PVM */
|
||||
sched-timeslice = <2000>; /* in ms */
|
||||
};
|
||||
|
||||
interrupts {
|
||||
config = &vgic;
|
||||
};
|
||||
|
||||
vdevices {
|
||||
generate = "/hypervisor";
|
||||
minidump {
|
||||
vdevice-type = "minidump";
|
||||
push-compatible = "qcom,minidump_rm";
|
||||
minidump_allowed;
|
||||
};
|
||||
|
||||
rm-rpc {
|
||||
vdevice-type = "rm-rpc";
|
||||
generate = "/hypervisor/qcom,resource-mgr";
|
||||
console-dev;
|
||||
message-size = <0x000000f0>;
|
||||
queue-depth = <0x00000008>;
|
||||
qcom,label = <0x1>;
|
||||
};
|
||||
|
||||
virtio-mmio@0 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
generate = "/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x1>;
|
||||
push-compatible = "virtio,mmio";
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x0>;
|
||||
memory {
|
||||
qcom,label = <0x11>; //for persist.img
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xDA6F8000>;
|
||||
};
|
||||
};
|
||||
|
||||
virtio-mmio@1 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
generate = "/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x2>;
|
||||
push-compatible = "virtio,mmio";
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x4000>;
|
||||
memory {
|
||||
qcom,label = <0x10>; //for system.img
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xDA6FC000>;
|
||||
};
|
||||
};
|
||||
|
||||
virtio-mmio@2 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
patch = "/soc/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x3>;
|
||||
push-compatible = "virtio,mmio";
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x8000>;
|
||||
memory {
|
||||
qcom,label = <0x15>; //for virtio-vsock
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xDA700000>;
|
||||
};
|
||||
};
|
||||
|
||||
swiotlb-shm {
|
||||
vdevice-type = "shm";
|
||||
generate = "/swiotlb";
|
||||
push-compatible = "swiotlb";
|
||||
peer-default;
|
||||
dma_base = <0x0 0x14000>;
|
||||
memory {
|
||||
qcom,label = <0x12>;
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xDA70c000>;
|
||||
};
|
||||
};
|
||||
|
||||
gpiomem0 {
|
||||
vdevice-type = "iomem";
|
||||
patch = "/soc/tlmm-vm-mem-access";
|
||||
push-compatible = "qcom,tlmm-vm-mem-access";
|
||||
peer-default;
|
||||
memory {
|
||||
qcom,label = <0x8>;
|
||||
qcom,mem-info-tag = <0x3>;
|
||||
allocate-base;
|
||||
};
|
||||
};
|
||||
|
||||
ddump-shm {
|
||||
vdevice-type = "shm-doorbell";
|
||||
generate = "/hypervisor/ddump-shm";
|
||||
push-compatible = "qcom,ddump-gunyah-gen";
|
||||
peer-default;
|
||||
memory {
|
||||
qcom,label = <0x7>;
|
||||
allocate-base;
|
||||
};
|
||||
};
|
||||
|
||||
gunyah-panic-notifier-shm {
|
||||
vdevice-type = "shm-doorbell";
|
||||
generate = "/hypervisor/gpn-shm";
|
||||
push-compatible = "qcom,gunyah-panic-gen";
|
||||
peer-default;
|
||||
memory {
|
||||
qcom,label = <0x9>;
|
||||
allocate-base;
|
||||
};
|
||||
};
|
||||
|
||||
vrtc {
|
||||
vdevice-type = "vrtc-pl031";
|
||||
peer-default;
|
||||
allocate-base;
|
||||
};
|
||||
|
||||
mem-buf-message-queue-pair {
|
||||
vdevice-type = "message-queue-pair";
|
||||
generate = "/hypervisor/membuf-msgq-pair";
|
||||
message-size = <0x000000f0>;
|
||||
queue-depth = <0x00000008>;
|
||||
peer-default;
|
||||
qcom,label = <0x0000001>;
|
||||
};
|
||||
|
||||
eva-message-queue-pair {
|
||||
vdevice-type = "message-queue-pair";
|
||||
generate = "/hypervisor/eva-msgq-pair";
|
||||
message-size = <0x000000f0>;
|
||||
queue-depth = <0x00000008>;
|
||||
peer-default;
|
||||
qcom,label =<0x7>;
|
||||
};
|
||||
|
||||
test-dbl-tuivm {
|
||||
vdevice-type = "doorbell";
|
||||
generate = "/hypervisor/test-dbl-tuivm";
|
||||
qcom,label = <0x4>;
|
||||
peer-default;
|
||||
};
|
||||
|
||||
test-dbl-tuivm-source {
|
||||
vdevice-type = "doorbell-source";
|
||||
generate = "/hypervisor/test-dbl-tuivm-source";
|
||||
qcom,label = <0x4>;
|
||||
peer-default;
|
||||
};
|
||||
|
||||
test-msgq-tuivm {
|
||||
vdevice-type = "message-queue-pair";
|
||||
generate = "/hypervisor/test-msgq-tuivm-pair";
|
||||
message-size = <0xf0>;
|
||||
queue-depth = <0x8>;
|
||||
qcom,label = <0x4>;
|
||||
peer-default;
|
||||
};
|
||||
|
||||
vcpu-sched-test-msgq {
|
||||
vdevice-type = "message-queue-pair";
|
||||
generate = "/hypervisor/sched-test-msgq-pair";
|
||||
message-size = <0xf0>;
|
||||
queue-depth = <0x8>;
|
||||
qcom,label = <0x8>;
|
||||
peer-default;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
firmware: firmware {
|
||||
qcom_scm: qcom_scm {
|
||||
compatible = "qcom,scm";
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc { };
|
||||
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
virtio-mmio {
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
vgic: interrupt-controller@17200000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x20000>;
|
||||
reg = <0x17200000 0x10000>, /* GICD */
|
||||
<0x17260000 0xA0000>; /* GICR * 5 */
|
||||
};
|
||||
|
||||
arch_timer: timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
always-on;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
vm_tlmm_irq: vm-tlmm-irq@0 {
|
||||
compatible = "qcom,tlmm-vm-irq";
|
||||
reg = <0x0 0x0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
tlmm: pinctrl@f000000 {
|
||||
compatible = "qcom,seraph-vm-pinctrl";
|
||||
reg = <0x0F000000 0x1000000>;
|
||||
interrupts-extended = <&vm_tlmm_irq 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
/* Valid pins */
|
||||
gpios = /bits/ 16 <12>;
|
||||
};
|
||||
|
||||
tlmm-vm-mem-access {
|
||||
compatible = "qcom,tlmm-vm-mem-access";
|
||||
tlmm-vm-gpio-list = <&tlmm 12 0>;
|
||||
};
|
||||
|
||||
tlmm-vm-test {
|
||||
compatible = "qcom,tlmm-vm-test";
|
||||
pinctrl-names = "active", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_7i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se1_7i2c_sleep>;
|
||||
tlmm-vm-gpio-list = <&tlmm 12 0>;
|
||||
};
|
||||
|
||||
pinctrl@f000000 {
|
||||
qupv3_se1_7i2c_pins: qupv3_se1_7i2c_pins {
|
||||
qupv3_se1_7i2c_active: qupv3_se1_7i2c_active {
|
||||
mux {
|
||||
pins = "gpio12";
|
||||
function = "qup2_se3_l0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio12";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se1_7i2c_sleep: qupv3_se1_7i2c_sleep {
|
||||
mux {
|
||||
pins = "gpio12";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio12";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qcom,test-dbl-tuivm {
|
||||
compatible = "qcom,gh-dbl";
|
||||
qcom,label = <0x4>;
|
||||
};
|
||||
|
||||
qcom,test-msgq-tuivm {
|
||||
compatible = "qcom,gh-msgq-test";
|
||||
gunyah-label = <4>;
|
||||
affinity = <0>;
|
||||
};
|
||||
|
||||
qcom,gh-qtimer@1742b000 {
|
||||
compatible = "qcom,gh-qtmr";
|
||||
reg = <0x1742b000 0x1000>;
|
||||
reg-names = "qtmr-base";
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "qcom,qtmr-intr";
|
||||
qcom,secondary;
|
||||
};
|
||||
|
||||
qcom_smcinvoke {
|
||||
compatible = "qcom,smcinvoke";
|
||||
};
|
||||
|
||||
qtee_shmbridge {
|
||||
compatible = "qcom,tee-shared-memory-bridge";
|
||||
qcom,custom-bridge-size = <64>;
|
||||
qcom,support-hypervisor;
|
||||
};
|
||||
|
||||
qcom,gunyah-panic-notifier {
|
||||
compatible = "qcom,gh-panic-notifier";
|
||||
gunyah-label = <9>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "seraph-vm-dma-heaps.dtsi"
|
||||
476
qcom/seraph.dtsi
476
qcom/seraph.dtsi
@@ -31,6 +31,30 @@
|
||||
|
||||
aliases {
|
||||
serial0 = &qupv3_se11_2uart;
|
||||
hsuart0 = &qupv3_se7_4uart;
|
||||
hsuart1 = &qupv3_se3_2uart;
|
||||
i2c0 = &qupv3_se0_i2c;
|
||||
i2c1 = &qupv3_se1_i2c;
|
||||
i2c2 = &qupv3_se2_i2c;
|
||||
i2c3 = &qupv3_se3_i2c;
|
||||
i2c4 = &qupv3_se4_i2c;
|
||||
i2c5 = &qupv3_se5_i2c;
|
||||
i2c6 = &qupv3_se6_i2c;
|
||||
i2c8 = &qupv3_se8_i2c;
|
||||
i2c9 = &qupv3_se9_i2c;
|
||||
i2c10 = &qupv3_se10_i2c;
|
||||
spi0 = &qupv3_se0_spi;
|
||||
spi1 = &qupv3_se1_spi;
|
||||
spi2 = &qupv3_se2_spi;
|
||||
spi3 = &qupv3_se3_spi;
|
||||
spi4 = &qupv3_se4_spi;
|
||||
spi5 = &qupv3_se5_spi;
|
||||
spi6 = &qupv3_se6_spi;
|
||||
spi7 = &qupv3_se7_spi;
|
||||
spi8 = &qupv3_se8_spi;
|
||||
spi9 = &qupv3_se9_spi;
|
||||
spi10 = &qupv3_se10_spi;
|
||||
mmc0 = &sdhc_1; /* SDC1 eMMC slot */
|
||||
};
|
||||
|
||||
firmware: firmware {};
|
||||
@@ -274,6 +298,38 @@
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
qcom,tmecom-qmp-client {
|
||||
compatible = "qcom,tmecom-qmp-client";
|
||||
mboxes = <&qmp_tme 0>;
|
||||
mbox-names = "tmecom";
|
||||
label = "tmecom";
|
||||
depends-on-supply = <&qmp_tme>;
|
||||
};
|
||||
|
||||
slimbam: bamdma@7004000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x07004000 0x20000>, <0x708B000 0x1000>;
|
||||
reg-names = "bam", "bam_remote_mem";
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
qcom,controlled-remotely;
|
||||
num-channels = <31>;
|
||||
qcom,ee = <1>;
|
||||
qcom,num-ees = <2>;
|
||||
};
|
||||
|
||||
slim_msm: slim@7040000 {
|
||||
compatible = "qcom,slim-ngd-v1.5.0";
|
||||
reg = <0x7040000 0x2C000>, <0x708A000 0x1000>;
|
||||
reg-names = "ctrl", "slimbus_remote_mem";
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&slimbam 3>, <&slimbam 4>;
|
||||
dma-names = "rx", "tx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qcom,smp2p-adsp {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <443>, <429>;
|
||||
@@ -418,6 +474,118 @@
|
||||
compatible = "qcom,glink";
|
||||
};
|
||||
|
||||
qcom,glinkpkt {
|
||||
compatible = "qcom,glinkpkt";
|
||||
|
||||
qcom,glinkpkt-at-mdm0 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DS";
|
||||
qcom,glinkpkt-dev-name = "at_mdm0";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-ctrl-cdsp {
|
||||
qcom,glinkpkt-edge = "cdsp";
|
||||
qcom,glinkpkt-ch-name = "LOOPBACK_CTL_CDSP";
|
||||
qcom,glinkpkt-dev-name = "glink_pkt_ctrl_cdsp";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data-cdsp {
|
||||
qcom,glinkpkt-edge = "cdsp";
|
||||
qcom,glinkpkt-ch-name = "LOOPBACK_DATA_CDSP";
|
||||
qcom,glinkpkt-dev-name = "glink_pkt_data_cdsp";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-ctrl-lpass {
|
||||
qcom,glinkpkt-edge = "lpass";
|
||||
qcom,glinkpkt-ch-name = "LOOPBACK_CTL_LPASS";
|
||||
qcom,glinkpkt-dev-name = "glink_pkt_ctrl_lpass";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data-lpass {
|
||||
qcom,glinkpkt-edge = "lpass";
|
||||
qcom,glinkpkt-ch-name = "LOOPBACK_DATA_LPASS";
|
||||
qcom,glinkpkt-dev-name = "glink_pkt_data_lpass";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-ctrl-mpss {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "LOOPBACK_CTL_MPSS";
|
||||
qcom,glinkpkt-dev-name = "glink_pkt_ctrl_mpss";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data-mpss {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "LOOPBACK_DATA_MPSS";
|
||||
qcom,glinkpkt-dev-name = "glink_pkt_data_mpss";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-apr-apps2 {
|
||||
qcom,glinkpkt-edge = "adsp";
|
||||
qcom,glinkpkt-ch-name = "apr_apps2";
|
||||
qcom,glinkpkt-dev-name = "apr_apps2";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data40-cntl {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
||||
qcom,glinkpkt-dev-name = "smdcntl8";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data1 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA1";
|
||||
qcom,glinkpkt-dev-name = "smd7";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data4 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA4";
|
||||
qcom,glinkpkt-dev-name = "smd8";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data11 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA11";
|
||||
qcom,glinkpkt-dev-name = "smd11";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-qmc-dma {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "QMC_DMA_LINE";
|
||||
qcom,glinkpkt-dev-name = "qmc_dma";
|
||||
qcom,glinkpkt-enable-ch-close;
|
||||
};
|
||||
|
||||
qcom,glinkpkt-qmc-cma {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "QMC_CMA_LINE";
|
||||
qcom,glinkpkt-dev-name = "qmc_cma";
|
||||
qcom,glinkpkt-enable-ch-close;
|
||||
};
|
||||
|
||||
qcom,glinkpkt-ims-sub-1 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "Ims_dc_sub1";
|
||||
qcom,glinkpkt-dev-name = "ims_dc_sub1";
|
||||
qcom,glinkpkt-enable-ch-close;
|
||||
};
|
||||
|
||||
qcom,glinkpkt-ims-sub-2 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "Ims_dc_sub2";
|
||||
qcom,glinkpkt-dev-name = "ims_dc_sub2";
|
||||
qcom,glinkpkt-enable-ch-close;
|
||||
};
|
||||
|
||||
qcom,glinkpkt-xpan_control {
|
||||
qcom,glinkpkt-edge = "adsp";
|
||||
qcom,glinkpkt-ch-name = "bt_cp_ctrl";
|
||||
qcom,glinkpkt-dev-name = "bt_cp_ctrl";
|
||||
};
|
||||
};
|
||||
|
||||
msm_gpu: qcom,kgsl-3d0@3d00000 { };
|
||||
|
||||
intc: interrupt-controller@17200000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
@@ -765,6 +933,113 @@
|
||||
wakeup-parent = <&pdc>;
|
||||
};
|
||||
|
||||
qcom_tzlog: tz-log@14680720 {
|
||||
compatible = "qcom,tz-log";
|
||||
reg = <0x14680720 0x3000>;
|
||||
qcom,hyplog-enabled;
|
||||
hyplog-address-offset = <0x410>;
|
||||
hyplog-size-offset = <0x414>;
|
||||
tmecrashdump-address-offset = <0x81CA0000>;
|
||||
};
|
||||
|
||||
qcom_qseecom: qseecom@c1700000 {
|
||||
compatible = "qcom,qseecom";
|
||||
memory-region = <&qseecom_mem>;
|
||||
qseecom_mem = <&qseecom_mem>;
|
||||
qseecom_ta_mem = <&qseecom_ta_mem>;
|
||||
qcom,no-user-contig-mem-support;
|
||||
qcom,hlos-num-ce-hw-instances = <1>;
|
||||
qcom,hlos-ce-hw-instance = <0>;
|
||||
qcom,qsee-ce-hw-instance = <0>;
|
||||
qcom,disk-encrypt-pipe-pair = <2>;
|
||||
qcom,no-clock-support;
|
||||
qcom,appsbl-qseecom-support;
|
||||
qcom,commonlib64-loaded-by-uefi;
|
||||
qcom,qsee-reentrancy-support = <2>;
|
||||
};
|
||||
|
||||
qcom_cedev: qcedev@1de0000 {
|
||||
compatible = "qcom,qcedev";
|
||||
reg = <0x1de0000 0x20000>,
|
||||
<0x1dc4000 0x28000>;
|
||||
reg-names = "crypto-base","crypto-bam-base";
|
||||
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,bam-pipe-pair = <2>;
|
||||
qcom,offload-ops-support;
|
||||
qcom,bam-pipe-offload-cpb-hlos = <1>;
|
||||
qcom,bam-pipe-offload-hlos-cpb = <3>;
|
||||
qcom,bam-pipe-offload-hlos-cpb-1 = <8>;
|
||||
qcom,bam-pipe-offload-hlos-hlos = <4>;
|
||||
qcom,bam-pipe-offload-hlos-hlos-1 = <9>;
|
||||
qcom,ce-hw-instance = <0>;
|
||||
qcom,ce-device = <0>;
|
||||
qcom,ce-hw-shared;
|
||||
qcom,bam-ee = <0>;
|
||||
qcom,smmu-s1-enable;
|
||||
qcom,no-clock-support;
|
||||
interconnect-names = "data_path";
|
||||
interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
|
||||
iommus = <&apps_smmu 0x080 0x0>,
|
||||
<&apps_smmu 0x081 0x0>;
|
||||
qcom,iommu-dma = "atomic";
|
||||
dma-coherent;
|
||||
|
||||
qcom_cedev_ns_cb {
|
||||
compatible = "qcom,qcedev,context-bank";
|
||||
label = "ns_context";
|
||||
iommus = <&apps_smmu 0x081 0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
qcom_cedev_s_cb {
|
||||
compatible = "qcom,qcedev,context-bank";
|
||||
label = "secure_context";
|
||||
iommus = <&apps_smmu 0x083 0x0>;
|
||||
qcom,iommu-vmid = <0x9>;
|
||||
qcom,secure-context-bank;
|
||||
dma-coherent;
|
||||
};
|
||||
};
|
||||
|
||||
qcom_rng: qrng@10c3000 {
|
||||
compatible = "qcom,msm-rng";
|
||||
reg = <0x10c3000 0x1000>;
|
||||
qcom,no-qrng-config;
|
||||
qcom,no-clock-support;
|
||||
};
|
||||
|
||||
tlmm-vm-mem-access {
|
||||
compatible = "qcom,tlmm-vm-mem-access";
|
||||
qcom,master;
|
||||
tlmm-vm-gpio-list = <&tlmm 12 0>;
|
||||
};
|
||||
|
||||
tlmm-vm-test {
|
||||
compatible = "qcom,tlmm-vm-test";
|
||||
qcom,master;
|
||||
tlmm-vm-gpio-list = <&tlmm 12 0>;
|
||||
};
|
||||
|
||||
qcom,test-dbl-tuivm {
|
||||
compatible = "qcom,gh-dbl";
|
||||
qcom,label = <0x4>;
|
||||
};
|
||||
|
||||
qcom,test-msgq-tuivm {
|
||||
compatible = "qcom,gh-msgq-test";
|
||||
gunyah-label = <4>;
|
||||
qcom,primary;
|
||||
};
|
||||
|
||||
qcom,gh-qtimer@1742b000 {
|
||||
compatible = "qcom,gh-qtmr";
|
||||
reg = <0x1742b000 0x1000>;
|
||||
reg-names = "qtmr-base";
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "qcom,qtmr-intr";
|
||||
qcom,primary;
|
||||
};
|
||||
|
||||
adsp_pas: remoteproc-adsp@06C00000 {
|
||||
compatible = "qcom,seraph-adsp-pas";
|
||||
reg = <0x06C00000 0x10000>;
|
||||
@@ -1095,8 +1370,148 @@
|
||||
qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;
|
||||
};
|
||||
|
||||
sdhc1_opp_table: sdhc1-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-peak-kBps = <250000 133320>;
|
||||
opp-avg-kBps = <104000 0>;
|
||||
};
|
||||
|
||||
opp-384000000 {
|
||||
opp-hz = /bits/ 64 <384000000>;
|
||||
opp-peak-kBps = <800000 300000>;
|
||||
opp-avg-kBps = <400000 0>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhc_1: sdhci@B24000 {
|
||||
status = "disabled";
|
||||
|
||||
compatible = "qcom,sdhci-msm-v5";
|
||||
|
||||
reg = <0x00B24000 0x1000>, <0x00B25000 0x1000>, <0xB28000 0x8000>, <0xB30000 0x9000>;
|
||||
reg-names = "hc", "cqhci", "cqhci_ice", "cqhci_ice_hwkm";
|
||||
|
||||
iommus = <&apps_smmu 0x120 0x0>;
|
||||
qcom,iommu-dma = "fastmap";
|
||||
|
||||
/*
|
||||
* iommu-dma-addr-pool- Indicate the range of data addresses which will be
|
||||
* used in dma allocation.
|
||||
*
|
||||
* iommu-geometry - This is specific for fastmap which Allow clients
|
||||
* to save SMMU page table memory.
|
||||
*
|
||||
* The 2nd parameter indicates size of the smmu page table memory.
|
||||
* If its exceeds beyond this size, last unused entry from page table
|
||||
* memory will be invalidated.
|
||||
*
|
||||
* It's better to provide range of dma address, hence provide
|
||||
* iommu-dma-addr-pool property along with iommu-geometry property.
|
||||
*/
|
||||
|
||||
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
|
||||
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
||||
|
||||
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
|
||||
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
|
||||
<&gcc GCC_SDCC1_AHB_CLK>,
|
||||
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
|
||||
clock-names = "core", "iface", "ice_core";
|
||||
|
||||
qcom,ice-clk-rates = <300000000 100000000>;
|
||||
|
||||
interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC &cnoc_cfg SLAVE_SDCC_1>;
|
||||
interconnect-names = "sdhc-ddr","cpu-sdhc";
|
||||
operating-points-v2 = <&sdhc1_opp_table>;
|
||||
|
||||
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
||||
qcom,dll-hsr-list = <0x000F44EC 0x0 0x01 0x290106C0 0x80040868>;
|
||||
|
||||
cap-mmc-hw-reset;
|
||||
|
||||
non-removable;
|
||||
supports-cqe;
|
||||
|
||||
no-sd;
|
||||
no-sdio;
|
||||
|
||||
bus-width = <8>;
|
||||
|
||||
/* Add dt entry for gcc hw reset */
|
||||
resets = <&gcc GCC_SDCC1_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qos0 {
|
||||
mask = <0x10>;
|
||||
vote = <44>;
|
||||
};
|
||||
|
||||
qos1 {
|
||||
mask = <0x0f>;
|
||||
vote = <44>;
|
||||
};
|
||||
};
|
||||
|
||||
thermal_zones: thermal-zones {};
|
||||
|
||||
trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring {
|
||||
size = <0x4000>;
|
||||
gunyah-label = <0x11>;
|
||||
};
|
||||
|
||||
trust_ui_vm_vblk1_ring: trust_ui_vm_vblk1_ring {
|
||||
size = <0x4000>;
|
||||
gunyah-label = <0x10>;
|
||||
};
|
||||
|
||||
trust_ui_vm_swiotlb: trust_ui_vm_swiotlb {
|
||||
size = <0x100000>;
|
||||
gunyah-label = <0x12>;
|
||||
};
|
||||
|
||||
trust_ui_vm: qcom,trust_ui_vm {
|
||||
vm_name = "trustedvm";
|
||||
shared-buffers-size = <0x108000>;
|
||||
shared-buffers = <&trust_ui_vm_vblk0_ring &trust_ui_vm_vblk1_ring &trust_ui_vm_swiotlb>;
|
||||
};
|
||||
|
||||
trust_ui_vm_virt_be0: trust_ui_vm_virt_be0@11 {
|
||||
qcom,vm = <&trust_ui_vm>;
|
||||
qcom,label = <0x11>;
|
||||
};
|
||||
|
||||
trust_ui_vm_virt_be1: trust_ui_vm_virt_be1@10 {
|
||||
qcom,vm = <&trust_ui_vm>;
|
||||
qcom,label = <0x10>;
|
||||
};
|
||||
|
||||
gh_secure_vm_loader0: gh-secure-vm-loader@0 {
|
||||
compatible = "qcom,gh-secure-vm-loader";
|
||||
qcom,pas-id = <28>;
|
||||
qcom,vmid = <45>;
|
||||
qcom,firmware-name = "trustedvm";
|
||||
qcom,keep-running;
|
||||
memory-region = <&trust_ui_vm_region &vm_comm_mem>;
|
||||
virtio-backends = <&trust_ui_vm_virt_be0 &trust_ui_vm_virt_be1>;
|
||||
};
|
||||
|
||||
gh-secure-vm-loader@2 {
|
||||
compatible = "qcom,gh-secure-vm-loader";
|
||||
qcom,pas-id = <35>;
|
||||
qcom,vmid = <50>;
|
||||
qcom,firmware-name = "cpusys_vm";
|
||||
memory-region = <&cpusys_vm_mem>;
|
||||
ext-region = <&chipinfo_mem>;
|
||||
ext-label = <0x7>;
|
||||
};
|
||||
|
||||
spmi_bus: spmi0_bus: qcom,spmi@c42d000 {
|
||||
compatible = "qcom,spmi-pmic-arb";
|
||||
reg = <0xc42d000 0x4000>,
|
||||
@@ -1121,6 +1536,7 @@
|
||||
compatible = "qcom,spmi-pmic-arb-debug";
|
||||
reg = <0x11314000 0x60>, <0x221c8784 0x4>;
|
||||
reg-names = "core", "fuse";
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "core_clk";
|
||||
qcom,fuse-enable-bit = <18>;
|
||||
#address-cells = <2>;
|
||||
@@ -1159,6 +1575,24 @@
|
||||
qcom,can-sleep;
|
||||
};
|
||||
};
|
||||
|
||||
dmesg-dump {
|
||||
compatible = "qcom,dmesg-dump";
|
||||
qcom,primary-vm;
|
||||
gunyah-label = <7>;
|
||||
peer-name = <2>;
|
||||
memory-region = <&vm_comm_mem>;
|
||||
shared-buffer-size = <0x1000>;
|
||||
};
|
||||
|
||||
qcom,gunyah-panic-notifier {
|
||||
compatible = "qcom,gh-panic-notifier";
|
||||
qcom,primary-vm;
|
||||
gunyah-label = <9>;
|
||||
peer-name = <2>;
|
||||
memory-region = <&vm_comm_mem>;
|
||||
shared-buffer-size = <0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "pineapple-gdsc.dtsi"
|
||||
@@ -1382,12 +1816,53 @@
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0x400000>;
|
||||
};
|
||||
|
||||
qseecom_mem: qseecom_region {
|
||||
compatible = "shared-dma-pool";
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0x1400000>;
|
||||
};
|
||||
|
||||
non_secure_display_memory: non_secure_display_region {
|
||||
compatible = "shared-dma-pool";
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0xa400000>;
|
||||
};
|
||||
|
||||
qseecom_ta_mem: qseecom_ta_region {
|
||||
compatible = "shared-dma-pool";
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0x1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&firmware {
|
||||
qcom_scm {
|
||||
compatible = "qcom,scm";
|
||||
};
|
||||
|
||||
qcom_smcinvoke {
|
||||
compatible = "qcom,smcinvoke";
|
||||
};
|
||||
|
||||
qcom_mem_object {
|
||||
compatible = "qcom,mem-object";
|
||||
};
|
||||
|
||||
qtee_shmbridge {
|
||||
compatible = "qcom,tee-shared-memory-bridge";
|
||||
};
|
||||
|
||||
qcom,hdcp {
|
||||
compatible = "qcom,hdcp";
|
||||
qcom,use-smcinvoke = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -1397,3 +1872,4 @@
|
||||
#include "seraph-debug.dtsi"
|
||||
#include "msm-arm-smmu-seraph.dtsi"
|
||||
#include "seraph-usb.dtsi"
|
||||
#include "msm-rdbg.dtsi"
|
||||
|
||||
@@ -100,4 +100,41 @@
|
||||
};
|
||||
};
|
||||
|
||||
qcom,smp2p-modem@1799000c {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <435>, <428>;
|
||||
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
|
||||
qcom,ipc = <&apcs 0 14>;
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <1>;
|
||||
|
||||
modem_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
modem_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
|
||||
qcom,entry-name = "ipa";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
/* ipa - inbound entry from mss */
|
||||
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
|
||||
qcom,entry-name = "ipa";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
|
||||
qcom,entry-name = "wlan";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -416,7 +416,7 @@
|
||||
reg = <0x0 0x8be00000 0x0 0x1a00000>;
|
||||
};
|
||||
|
||||
pil_modem_mem: modem_region {
|
||||
rproc_modem_mem: rproc_modem_region {
|
||||
no-map;
|
||||
reg = <0x0 0x8d800000 0x0 0x4c1c000>;
|
||||
};
|
||||
@@ -1650,6 +1650,80 @@
|
||||
};
|
||||
};
|
||||
|
||||
modem_pas: remoteproc-modem@4080000 {
|
||||
compatible = "qcom,sm8150-mpss-pas";
|
||||
reg = <0x4080000 0x00100>;
|
||||
status = "ok";
|
||||
|
||||
cx-supply = <&VDD_CX_LEVEL>;
|
||||
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
||||
mx-supply = <&VDD_MX_LEVEL>;
|
||||
mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
||||
reg-names = "cx", "mx";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "xo";
|
||||
|
||||
qcom,qmp = <&aoss_qmp>;
|
||||
|
||||
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "crypto_ddr";
|
||||
|
||||
memory-region = <&rproc_modem_mem>;
|
||||
|
||||
/* Inputs from mss */
|
||||
interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&modem_smp2p_in 0 0>,
|
||||
<&modem_smp2p_in 2 0>,
|
||||
<&modem_smp2p_in 1 0>,
|
||||
<&modem_smp2p_in 3 0>,
|
||||
<&modem_smp2p_in 7 0>;
|
||||
|
||||
interrupt-names = "wdog",
|
||||
"fatal",
|
||||
"handover",
|
||||
"ready",
|
||||
"stop-ack",
|
||||
"shutdown-ack";
|
||||
|
||||
/* Outputs to mss */
|
||||
qcom,smem-states = <&modem_smp2p_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
|
||||
glink-edge {
|
||||
qcom,remote-pid = <1>;
|
||||
transport = "smem";
|
||||
mboxes = <&apss_shared 12>;
|
||||
mbox-names = "mpss_smem";
|
||||
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
label = "modem";
|
||||
qcom,glink-label = "mpss";
|
||||
|
||||
qcom,modem_qrtr {
|
||||
qcom,glink-channels = "IPCRTR";
|
||||
qcom,intents = <0x800 5
|
||||
0x2000 3
|
||||
0x4400 2>;
|
||||
};
|
||||
|
||||
qcom,msm_fastrpc_rpmsg {
|
||||
compatible = "qcom,msm-fastrpc-rpmsg";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
qcom,intents = <0x64 64>;
|
||||
};
|
||||
|
||||
qcom,modem_glink_ssr {
|
||||
qcom,glink-channels = "glink_ssr";
|
||||
};
|
||||
|
||||
qcom,modem_ds {
|
||||
qcom,glink-channels = "DS";
|
||||
qcom,intents = <0x4000 0x2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qcom,pmu {
|
||||
compatible = "qcom,pmu";
|
||||
qcom,pmu-events-tbl =
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
|
||||
/ {
|
||||
qcom,pmic-id-size = <8>;
|
||||
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x59>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
|
||||
13
qcom/volcano6i-idp-wcd9395-brahma-nopmi-overlay.dts
Normal file
13
qcom/volcano6i-idp-wcd9395-brahma-nopmi-overlay.dts
Normal file
@@ -0,0 +1,13 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "volcano6i-idp-wcd9395-brahma.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6I IDP + WCD9395 HSJ + Brahma + nopmi";
|
||||
compatible = "qcom,volcano-idp", "qcom,volcano", "qcom,volcanop-idp", "qcom,volcanop", "qcom,idp";
|
||||
qcom,msm-id = <0X4000291 0x10000>, <0x4000292 0x10000>, <0x8000291 0x10000>, <0x8000292 0x10000>, <0xc000291 0x10000>, <0xc000292 0x10000>, <0x10000291 0x10000>, <0x10000292 0x10000>;
|
||||
qcom,board-id = <34 3>;
|
||||
qcom,pmic-id-size = <8>;
|
||||
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
};
|
||||
13
qcom/volcano6i-idp-wcd9395-ganges-nopmi-overlay.dts
Normal file
13
qcom/volcano6i-idp-wcd9395-ganges-nopmi-overlay.dts
Normal file
@@ -0,0 +1,13 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "volcano6i-idp-wcd9395-ganges.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6I IDP + WCD9395 HSJ + Ganges + nopmi";
|
||||
compatible = "qcom,volcano-idp", "qcom,volcano", "qcom,volcanop-idp", "qcom,volcanop", "qcom,idp";
|
||||
qcom,board-id = <34 2>;
|
||||
qcom,msm-id = <0X4000291 0x10000>, <0x4000292 0x10000>, <0x8000291 0x10000>, <0x8000292 0x10000>, <0xc000291 0x10000>, <0xc000292 0x10000>, <0x10000291 0x10000>, <0x10000292 0x10000>;
|
||||
qcom,pmic-id-size = <8>;
|
||||
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
};
|
||||
13
qcom/volcano6i-mtp-STSafe320-brahma-nopmi-overlay.dts
Normal file
13
qcom/volcano6i-mtp-STSafe320-brahma-nopmi-overlay.dts
Normal file
@@ -0,0 +1,13 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "volcano6i-mtp-STSafe320-brahma.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6I MTP + STSafe320 eSE + Brahma + nopmi";
|
||||
compatible = "qcom,volcano-mtp", "qcom,volcano", "qcom,volcanop-mtp", "qcom,volcanop", "qcom,mtp";
|
||||
qcom,board-id = <8 11>;
|
||||
qcom,msm-id = <0X4000291 0x10000>, <0x8000291 0x10000>, <0xc000291 0x10000>, <0x10000291 0x10000>;
|
||||
qcom,pmic-id-size = <8>;
|
||||
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
};
|
||||
13
qcom/volcano6i-mtp-brahma-nopmi-overlay.dts
Normal file
13
qcom/volcano6i-mtp-brahma-nopmi-overlay.dts
Normal file
@@ -0,0 +1,13 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "volcano6i-mtp-brahma.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6I MTP + WCD9378 AATC + Brahma + nopmi";
|
||||
compatible = "qcom,volcano-mtp", "qcom,volcano", "qcom,volcanop-mtp", "qcom,volcanop", "qcom,mtp";
|
||||
qcom,board-id = <8 6>;
|
||||
qcom,msm-id = <0X4000291 0x10000>, <0x4000292 0x10000>, <0x8000291 0x10000>, <0x8000292 0x10000>, <0xc000291 0x10000>, <0xc000292 0x10000>, <0x10000291 0x10000>, <0x10000292 0x10000>;
|
||||
qcom,pmic-id-size = <8>;
|
||||
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
};
|
||||
13
qcom/volcano6i-mtp-ganges-nopmi-overlay.dts
Normal file
13
qcom/volcano6i-mtp-ganges-nopmi-overlay.dts
Normal file
@@ -0,0 +1,13 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "volcano6i-mtp-ganges.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6I MTP + WCD9378 AATC + Ganges + nopmi";
|
||||
compatible = "qcom,volcano-mtp", "qcom,volcano", "qcom,volcanop-mtp", "qcom,volcanop", "qcom,mtp";
|
||||
qcom,board-id = <8 3>;
|
||||
qcom,msm-id = <0X4000291 0x10000>, <0x4000292 0x10000>, <0x8000291 0x10000>, <0x8000292 0x10000>, <0xc000291 0x10000>, <0xc000292 0x10000>, <0x10000291 0x10000>, <0x10000292 0x10000>;
|
||||
qcom,pmic-id-size = <8>;
|
||||
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
};
|
||||
13
qcom/volcano6i-mtp-wcd9395-brahma-nopmi-overlay.dts
Normal file
13
qcom/volcano6i-mtp-wcd9395-brahma-nopmi-overlay.dts
Normal file
@@ -0,0 +1,13 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "volcano6i-mtp-wcd9395-brahma.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6I MTP + WCD9395 HSJ + Brahma + nopmi";
|
||||
compatible = "qcom,volcano-mtp", "qcom,volcano", "qcom,volcanop-mtp", "qcom,volcanop", "qcom,mtp";
|
||||
qcom,board-id = <8 5>;
|
||||
qcom,msm-id = <0X4000291 0x10000>, <0x4000292 0x10000>, <0x8000291 0x10000>, <0x8000292 0x10000>, <0xc000291 0x10000>, <0xc000292 0x10000>, <0x10000291 0x10000>, <0x10000292 0x10000>;
|
||||
qcom,pmic-id-size = <8>;
|
||||
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
};
|
||||
13
qcom/volcano6i-mtp-wcd9395-ganges-hac2019-nopmi-overlay.dts
Normal file
13
qcom/volcano6i-mtp-wcd9395-ganges-hac2019-nopmi-overlay.dts
Normal file
@@ -0,0 +1,13 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "volcano6i-mtp-wcd9395-ganges-hac2019.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6I MTP + WCD9395 HSJ + HAC2019/RFID + Ganges + nopmi";
|
||||
compatible = "qcom,volcano-mtp", "qcom,volcano", "qcom,volcanop-mtp", "qcom,volcanop", "qcom,mtp";
|
||||
qcom,board-id = <8 4>;
|
||||
qcom,msm-id = <0X4000291 0x10000>, <0x4000292 0x10000>, <0x8000291 0x10000>, <0x8000292 0x10000>, <0xc000291 0x10000>, <0xc000292 0x10000>, <0x10000291 0x10000>, <0x10000292 0x10000>;
|
||||
qcom,pmic-id-size = <8>;
|
||||
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
};
|
||||
13
qcom/volcano6i-mtp-wcd9395-ganges-nopmi-overlay.dts
Normal file
13
qcom/volcano6i-mtp-wcd9395-ganges-nopmi-overlay.dts
Normal file
@@ -0,0 +1,13 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "volcano6i-mtp-wcd9395-ganges.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6I MTP + WCD9395 HSJ + Ganges + nopmi";
|
||||
compatible = "qcom,volcano-mtp", "qcom,volcano", "qcom,volcanop-mtp", "qcom,volcanop", "qcom,mtp";
|
||||
qcom,board-id = <8 2>;
|
||||
qcom,msm-id = <0X4000291 0x10000>, <0x4000292 0x10000>, <0x8000291 0x10000>, <0x8000292 0x10000>, <0xc000291 0x10000>, <0xc000292 0x10000>, <0x10000291 0x10000>, <0x10000292 0x10000>;
|
||||
qcom,pmic-id-size = <8>;
|
||||
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
};
|
||||
13
qcom/volcano6i-mtp-wcd9395-moselle-nopmi-overlay.dts
Normal file
13
qcom/volcano6i-mtp-wcd9395-moselle-nopmi-overlay.dts
Normal file
@@ -0,0 +1,13 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "volcano6i-mtp-wcd9395-moselle.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Volcano6I MTP + WCD9395 AATC + SN220T + Moselle + nopmi";
|
||||
compatible = "qcom,volcano-mtp", "qcom,volcano", "qcom,volcanop-mtp", "qcom,volcanop", "qcom,mtp";
|
||||
qcom,board-id = <8 7>;
|
||||
qcom,msm-id = <0X4000291 0x10000>, <0x4000292 0x10000>, <0x8000291 0x10000>, <0x8000292 0x10000>, <0xc000291 0x10000>, <0xc000292 0x10000>, <0x10000291 0x10000>, <0x10000292 0x10000>;
|
||||
qcom,pmic-id-size = <8>;
|
||||
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
};
|
||||
Reference in New Issue
Block a user