ARM: dts: msm: Add initial device tree for Anorak

- Enabled SRAM node and added initial memory map for Anorak.
- Added arch_timer and mem_timer for Anorak.
- Added qcom_tzlog (this will be needed for ABL to load dtbo).
- Added device tree files for anorak IDP, ATP and QXR based vairous boards.

Change-Id: I3cca8e4de31d3885b63eec8da86fab105533d242

bindings/arm/msm/msm.txt

@@ -102,7 +102,7 @@ SoCs:
   compatible = "qcom,pineapple", "qcom,pineapplep"
 
 - ANORAK
-  compatible = "qcom,anorak"
+  compatible = "qcom,anorak", "qcom,anorakp"
 
 - NIOBE
   compatible = "qcom,niobe", "qcom,niobep"
@@ -377,6 +377,9 @@ compatible = "qcom,monaco_auto-ivi-adp-star"
 compatible = "qcom,anorak-idp"
 compatible = "qcom,anorak-qxr"
 compatible = "qcom,anorak-atp"
+compatible = "qcom,anorakp-idp"
+compatible = "qcom,anorakp-qxr"
+compatible = "qcom,anorakp-atp"
 compatible = "qcom,pitti-rumi"
 compatible = "qcom,pitti-idp"
 compatible = "qcom,pitti-atp"

qcom/Makefile

@@ -132,17 +132,30 @@ niobe-dtb-$(CONFIG_ARCH_NIOBE) += \
 niobe-overlays-dtb-$(CONFIG_ARCH_NIOBE) += $(NIOBE_BOARDS) $(NOAPQ_NIOBE_BOARDS) $(NIOBE_BASE_DTB) $(NIOBE_APQ_BASE_DTB)
 dtb-y += $(niobe-dtb-y)
 
+### Added for Anorak ###
 ANORAK_BASE_DTB += anorak.dtb
+ANORAK_APQ_BASE_DTB += anorakp.dtb
 
 ANORAK_BOARDS += \
 		anorak-idp-overlay.dtbo \
 		anorak-qxr-overlay.dtbo \
-		anorak-atp-overlay.dtbo
+		anorak-atp-overlay.dtbo \
+		anorak-idp-hmt-overlay.dtbo \
+		anorak-qxr-hmt-ufs-ref-overlay.dtbo \
+		anorak-qxr-4kdisp-hmt-ufs-ref-overlay.dtbo \
+		anorak-qxr-hmt-overlay.dtbo \
+		anorak-idp-sd-overlay.dtbo \
+		anorak-idp-top-hmt-overlay.dtbo \
+		anorak-idp-top-hsp-overlay.dtbo \
+		anorak-idp-4kdisp-hsp-overlay.dtbo \
+		anorak-idp-4kdisp-hmt-overlay.dtbo \
+		anorak-idp-hsp-nodisplay-overlay.dtbo
 
 anorak-dtb-$(CONFIG_ARCH_ANORAK) += \
-	$(call add-overlays, $(ANORAK_BOARDS) ,$(ANORAK_BASE_DTB))
+	$(call add-overlays, $(ANORAK_BOARDS) ,$(ANORAK_BASE_DTB))\
+	$(call add-overlays, $(ANORAK_BOARDS) ,$(ANORAK_APQ_BASE_DTB))
 
-anorak-overlays-dtb-$(CONFIG_ARCH_ANORAK) += $(ANORAK_BOARDS) ${ANORAK_BASE_DTB)
+anorak-overlays-dtb-$(CONFIG_ARCH_ANORAK) += $(ANORAK_BOARDS) $(ANORAK_BASE_DTB) $(ANORAK_APQ_BASE_DTB)
 dtb-y += $(anorak-dtb-y)
 
 BLAIR_BASE_DTB += blair.dtb

qcom/anorak-idp-4kdisp-hmt-overlay.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "anorak-idp-4kdisp-hmt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP 4K display + HMT";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,msm-id = <549 0x10000>,<649 0x10000>;
+	qcom,board-id = <0x10022 0x6>;
+};

qcom/anorak-idp-4kdisp-hmt.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorak.dtsi"
+#include "anorak-idp-4kdisp-hmt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP 4K display + HMT";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,board-id = <0x10022 0x6>;
+};

qcom/anorak-idp-4kdisp-hmt.dtsi

@@ -0,0 +1,4 @@
+#include "anorak-idp.dtsi"
+
+&soc {
+};

qcom/anorak-idp-4kdisp-hsp-overlay.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "anorak-idp-4kdisp-hsp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP 4K display + HSP";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,msm-id = <549 0x10000>,<649 0x10000>;
+	qcom,board-id = <0x10022 0x5>;
+};

qcom/anorak-idp-4kdisp-hsp.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorak.dtsi"
+#include "anorak-idp-4kdisp-hsp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP 4K display + HSP";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,board-id = <0x10022 0x5>;
+};

qcom/anorak-idp-4kdisp-hsp.dtsi

@@ -0,0 +1,4 @@
+#include "anorak-idp.dtsi"
+
+&soc {
+};

qcom/anorak-idp-hmt-overlay.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "anorak-idp-hmt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP HMT";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,msm-id = <549 0x10000>,<649 0x10000>;
+	qcom,board-id = <0x10022 0x1>;
+};

qcom/anorak-idp-hmt.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorak.dtsi"
+#include "anorak-idp-hmt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP HMT";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,board-id = <0x10022 0x1>;
+};

qcom/anorak-idp-hmt.dtsi

@@ -0,0 +1,3 @@
+&soc {
+
+};

qcom/anorak-idp-hsp-nodisplay-overlay.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "anorak-idp-hsp-nodisplay.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP HSP with no display";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,msm-id = <549 0x10000>,<649 0x10000>;
+	qcom,board-id = <0x10022 0x7>;
+};

qcom/anorak-idp-hsp-nodisplay.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorak.dtsi"
+#include "anorak-idp-hsp-nodisplay.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP HSP with no display";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,board-id = <0x10022 0x7>;
+};

qcom/anorak-idp-hsp-nodisplay.dtsi

@@ -0,0 +1,4 @@
+#include "anorak-idp.dtsi"
+
+&soc {
+};

qcom/anorak-idp-sd-overlay.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "anorak-idp-sd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP Single Display";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,msm-id = <549 0x10000>,<649 0x10000>;
+	qcom,board-id = <0x10022 0x2>;
+};

qcom/anorak-idp-sd.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorak.dtsi"
+#include "anorak-idp-sd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP Single Display";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,board-id = <0x10022 0x2>;
+};

qcom/anorak-idp-sd.dtsi

@@ -0,0 +1 @@
+#include "anorak-idp.dtsi"

qcom/anorak-idp-top-hmt-overlay.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "anorak-idp-top-hmt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP Topanga Hamilton";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,msm-id = <549 0x10000>,<649 0x10000>;
+	qcom,board-id = <0x10022 0x3>;
+};

qcom/anorak-idp-top-hmt.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorak.dtsi"
+#include "anorak-idp-top-hmt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP Topanga Hamilton";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,board-id = <0x10022 0x3>;
+};

qcom/anorak-idp-top-hmt.dtsi

@@ -0,0 +1 @@
+#include "anorak-idp-hmt.dtsi"

qcom/anorak-idp-top-hsp-overlay.dts

@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "anorak-idp-top-hsp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP Topanga with EDP display + HSP";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,msm-id = <549 0x10000>,<649 0x10000>;
+	qcom,board-id = <0x10022 0x4>;
+};
+

qcom/anorak-idp-top-hsp.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorak.dtsi"
+#include "anorak-idp-top-hsp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak IDP Topanga with EDP display + HSP";
+	compatible = "qcom,anorak-idp", "qcom,anorak", "qcom,idp";
+	qcom,board-id = <0x10022 0x4>;
+};

qcom/anorak-idp-top-hsp.dtsi

@@ -0,0 +1,4 @@
+#include "anorak-idp.dtsi"
+
+&soc {
+};

qcom/anorak-qxr-4kdisp-hmt-ufs-ref-overlay.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "anorak-qxr-4kdisp-hmt-ufs-ref.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak QXR HMT UFS REF + 4K Display";
+	compatible = "qcom,anorak-qxr", "qcom,anorak";
+	qcom,msm-id = <549 0x10000>,<649 0x10000>;
+	qcom,board-id = <0x10126 0x3>;
+};

qcom/anorak-qxr-4kdisp-hmt-ufs-ref.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorak.dtsi"
+#include "anorak-qxr-4kdisp-hmt-ufs-ref.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak QXR HMT UFS REF + 4K Display";
+	compatible = "qcom,anorak-qxr", "qcom,anorak";
+	qcom,board-id = <0x10126 0x3>;
+};

qcom/anorak-qxr-4kdisp-hmt-ufs-ref.dtsi

@@ -0,0 +1 @@
+#include "anorak-qxr-hmt-ufs-ref.dtsi"

qcom/anorak-qxr-hmt-overlay.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "anorak-qxr-hmt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak QXR HMT";
+	compatible = "qcom,anorak-qxr", "qcom,anorak";
+	qcom,msm-id = <549 0x10000>,<649 0x10000>;
+	qcom,board-id = <0x10026 0x1>;
+};

qcom/anorak-qxr-hmt-ufs-ref-overlay.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "anorak-qxr-hmt-ufs-ref.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak QXR HMT UFS REF";
+	compatible = "qcom,anorak-qxr", "qcom,anorak";
+	qcom,msm-id = <549 0x10000>,<649 0x10000>;
+	qcom,board-id = <0x10126 0x2>;
+};

qcom/anorak-qxr-hmt-ufs-ref.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorak.dtsi"
+#include "anorak-qxr-hmt-ufs-ref.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak QXR HMT UFS REF";
+	compatible = "qcom,anorak-qxr", "qcom,anorak";
+	qcom,board-id = <0x10126 0x2>;
+};

qcom/anorak-qxr-hmt-ufs-ref.dtsi

@@ -0,0 +1 @@
+#include "anorak-qxr-hmt.dtsi"

qcom/anorak-qxr-hmt.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorak.dtsi"
+#include "anorak-qxr-hmt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak QXR HMT";
+	compatible = "qcom,anorak-qxr", "qcom,anorak";
+	qcom,board-id = <0x10026 0x1>;
+};

qcom/anorak-qxr-hmt.dtsi

@@ -0,0 +1,3 @@
+&soc {
+
+};

qcom/anorak-reserved-memory.dtsi

@@ -0,0 +1,177 @@
+&reserved_memory {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+
+	hyp_qheebsp_mem: hyp_qheebsp_region@80000000 {
+		no-map;
+		reg = <0x0 0x80000000 0x0 0x200000>;
+	};
+
+	hyp_data_mem: hyp_data_region@80200000 {
+		no-map;
+		reg = <0x0 0x80200000 0x0 0x400000>;
+	};
+
+	hyp_rm_hypx_mem: hyp_rm_hypx_region@80600000 {
+		no-map;
+		reg = <0x0 0x80600000 0x0 0x200000>;
+	};
+
+	cpusys_vm_mem: cpusys_vm_region@80800000 {
+		no-map;
+		reg = <0x0 0x80800000 0x0 0x400000>;
+	};
+
+	hyp_heap_mem: hyp_heap_region@80c00000 {
+		no-map;
+		reg = <0x0 0x80c00000 0x0 0x200000>;
+	};
+
+	tags_hyp_mem: tags_hyp_region@80e00000 {
+		no-map;
+		reg = <0x0 0x80e00000 0x0 0x3d0000>;
+	};
+
+	xbl_dtlog_mem: xbl_dtlog_region@81a00000 {
+		no-map;
+		reg = <0x0 0x81a00000 0x0 0x40000>;
+	};
+
+	xbl_ramdump_mem: xbl_ramdump_region@81a40000 {
+		no-map;
+		reg = <0x0 0x81a40000 0x0 0x1c0000>;
+	};
+
+	aop_image_mem: aop_image_region@81c00000 {
+		no-map;
+		reg = <0x0 0x81c00000 0x0 0x60000>;
+	};
+
+	aop_cmd_db_mem: aop_cmd_db_region@81c60000 {
+		compatible = "qcom,cmd-db";
+		no-map;
+		reg = <0x0 0x81c60000 0x0 0x20000>;
+	};
+
+	aop_config_mem: aop_config_region@81c80000 {
+		no-map;
+		reg = <0x0 0x81c80000 0x0 0x20000>;
+	};
+
+	tme_crash_dump_mem: tme_crash_dump_region@81ca0000 {
+		no-map;
+		reg = <0x0 0x81ca0000 0x0 0x40000>;
+	};
+
+	tme_log_mem: tme_log_region@81ce0000 {
+		no-map;
+		reg = <0x0 0x81ce0000 0x0 0x4000>;
+	};
+
+	uefi_log_mem: uefi_log_region@81ce4000 {
+		no-map;
+		reg = <0x0 0x81ce4000 0x0 0x10000>;
+	};
+
+	secdata_apss_mem: secdata_apss_region@81cff000 {
+		no-map;
+		reg = <0x0 0x81cff000 0x0 0x1000>;
+	};
+
+	smem_mem: smem_region@81d00000 {
+		no-map;
+		reg = <0x0 0x81d00000 0x0 0x200000>;
+	};
+
+	global_sync_mem: global_sync_region@82600000 {
+		no-map;
+		reg = <0x0 0x82600000 0x0 0x100000>;
+	};
+
+	tz_stat_mem: tz_stat_region@82700000 {
+		no-map;
+		reg = <0x0 0x82700000 0x0 0x100000>;
+	};
+
+	video_mem: video_region@88d00000 {
+		no-map;
+		reg = <0x0 0x88d00000 0x0 0x700000>;
+	};
+
+	adsp_mem: adsp_region@89400000 {
+		no-map;
+		reg = <0x0 0x89400000 0x0 0x2100000>;
+	};
+
+	cdsp_mem: cdsp_region@8b500000 {
+		no-map;
+		reg = <0x0 0x8b500000 0x0 0xf00000>;
+	};
+
+	ipa_fw_mem: ipa_fw_region@8d500000 {
+		no-map;
+		reg = <0x0 0x8d500000 0x0 0x10000>;
+	};
+
+	ipa_gsi_mem: ipa_gsi_region@8d510000 {
+		no-map;
+		reg = <0x0 0x8d510000 0x0 0xa000>;
+	};
+
+	gpu_microcode_mem: gpu_microcode_region@8d51a000 {
+		no-map;
+		reg = <0x0 0x8d51a000 0x0 0x2000>;
+	};
+
+	spss_region_mem: spss_region_region@8d600000 {
+		no-map;
+		reg = <0x0 0x8d600000 0x0 0x180000>;
+	};
+
+	spu_tz_shared_mem: spu_tz_shared_mem@8d780000 {
+		no-map;
+		reg = <0x0 0x8d780000 0x0 0x80000>;
+	};
+
+	cvp_mem: cvp_region@8d800000 {
+		no-map;
+		reg = <0x0 0x8d800000 0x0 0x700000>;
+	};
+
+	camera_mem: camera_region@8df00000 {
+		no-map;
+		reg = <0x0 0x8df00000 0x0 0x800000>;
+	};
+
+	cpucp_fw_mem: cpucp_fw_region@d8000000 {
+		no-map;
+		reg = <0x0 0xd8000000 0x0 0x100000>;
+	};
+
+	xbl_sc_mem: xbl_sc_region@d8100000 {
+		no-map;
+		reg = <0x0 0xd8100000 0x0 0x40000>;
+	};
+
+	reserved_mem: reserved_region@d8140000 {
+		no-map;
+		reg = <0x0 0xd8140000 0x0 0x1c0000>;
+	};
+
+	qtee_mem: qtee_region@d8300000 {
+		no-map;
+		reg = <0x0 0xd8300000 0x0 0x500000>;
+	};
+
+	ta_mem: ta_region@d8800000 {
+		no-map;
+		reg = <0x0 0xd8800000 0x0 0x3000000>;
+	};
+
+	tags_tz_mem: tags_tz_region@db800000 {
+		no-map;
+		reg = <0x0 0xdb800000 0x0 0xf00000>;
+	};
+
+};

qcom/anorak.dtsi

@@ -10,8 +10,9 @@
 	#size-cells = <2>;
 	memory { device_type = "memory"; reg = <0 0 0 0>; };
 
+	chosen: chosen { bootargs = "console=ttyMSM0,115200n8 loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat service_locator.enable=1 msm_rtb.filter=0x237 allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 ftrace_dump_on_oops kpti=off rcu_nocbs=0-5 swiotlb=noforce cgroup.memory=nokmem,nosocket can.stats_timer=0 disable_dma32=on cpufreq.default_governor=performance"; };
 
-	chosen: chosen { };
+	reserved_memory: reserved-memory { };
 
 	aliases: aliases { };
 
@@ -237,9 +238,135 @@
 		};
 	};
 
+	sram: sram@17D09100 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "mmio-sram";
+		reg = <0x0 0x17D09100 0x0 0x200>;
+		ranges = <0x0 0x0 0x0 0x17D09100 0x0 0x200>;
+
+		cpu_scp_lpri: scp-shmem@0 {
+			compatible = "arm,scp-shmem";
+			reg = <0x0 0x0 0x0 0x200>;
+		};
+	};
+
 	soc: soc { };
 };
 
+#include "anorak-reserved-memory.dtsi"
+
+&reserved_memory {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+
+	/* global autoconfigured region for contiguous allocations */
+	system_cma: linux,cma {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x2000000>;
+		linux,cma-default;
+	};
+
+	user_contig_mem: user_contig_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1000000>;
+	};
+
+	qseecom_mem: qseecom_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1400000>;
+	};
+
+	qseecom_ta_mem: qseecom_ta_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1000000>;
+	};
+
+	cdsp_eva_mem: cdsp_eva_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x400000>;
+	};
+
+	adsp_mem_heap: adsp_heap_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0xC00000>;
+	};
+
+	cdsp_secure_heap: secure_cdsp_region { /* Secure DSP */
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x2800000>;
+	};
+
+	sp_mem: sp_region {  /* SPSS-HLOS ION shared mem */
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1000000>;
+	};
+
+	ramoops_mem: ramoops_region {
+		compatible = "ramoops";
+		alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
+		size = <0x0 0x200000>;
+		pmsg-size = <0x200000>;
+		mem-type = <2>;
+	};
+
+	va_md_mem: va_md_mem_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
+		reusable;
+		size = <0 0x1000000>;
+	};
+
+	audio_cma_mem: audio_cma_region {
+	compatible = "shared-dma-pool";
+	alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+	reusable;
+	alignment = <0x0 0x400000>;
+	size = <0x0 0x1000000>;
+	};
+
+	non_secure_display_memory: non_secure_display_region {
+		compatible = "shared-dma-pool";
+		reusable;
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		size = <0x0 0xa400000>;
+		alignment = <0x0 0x400000>;
+	};
+
+	cnss_wlan_mem: cnss_wlan_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x2000000>;
+	};
+};
+
 &soc {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -296,4 +423,94 @@
 		      <0x17260000 0x100000>;	/* GICR * 8 */
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 	};
+
+	cpu_pmu: cpu-pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <19200000>;
+	};
+
+	kryo-erp {
+		compatible = "arm,arm64-kryo-cpu-erp";
+		interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "l1-l2-faultirq", "l3-scu-faultirq";
+	};
+
+	memtimer: timer@17420000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "arm,armv7-timer-mem";
+		reg = <0x17420000 0x1000>;
+		clock-frequency = <19200000>;
+
+		frame@17421000 {
+			frame-number = <0>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17421000 0x1000>,
+			      <0x17422000 0x1000>;
+		};
+
+		frame@17423000 {
+			frame-number = <1>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17423000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17425000 {
+			frame-number = <2>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17425000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17427000 {
+			frame-number = <3>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17427000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17429000 {
+			frame-number = <4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17429000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@1742b000 {
+			frame-number = <5>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x1742b000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@1742d000 {
+			frame-number = <6>;
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x1742d000 0x1000>;
+			status = "disabled";
+		};
+	};
+
+	qcom_tzlog: tz-log@146AA720 {
+		compatible = "qcom,tz-log";
+		reg = <0x146AA720 0x3000>;
+		qcom,hyplog-enabled;
+		hyplog-address-offset = <0x410>;
+		hyplog-size-offset = <0x414>;
+		tmecrashdump-address-offset = <0x81CA0000>;
+	};
 };

qcom/anorakp-atp.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorakp.dtsi"
+#include "anorakp-atp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP ATP";
+	compatible = "qcom,anorakp-atp", "qcom,anorakp", "qcom,atp";
+	qcom,board-id = <0x10021 0x0>;
+};

qcom/anorakp-atp.dtsi

@@ -0,0 +1 @@
+#include "anorak-atp.dtsi"

qcom/anorakp-idp-4kdisp-hmt.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorakp.dtsi"
+#include "anorakp-idp-4kdisp-hmt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP IDP 4K display + HMT";
+	compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
+	qcom,board-id = <0x10022 0x6>;
+};

qcom/anorakp-idp-4kdisp-hmt.dtsi

@@ -0,0 +1 @@
+#include "anorak-idp-4kdisp-hmt.dtsi"

qcom/anorakp-idp-4kdisp-hsp.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorakp.dtsi"
+#include "anorakp-idp-4kdisp-hsp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP IDP 4K display + HSP";
+	compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
+	qcom,board-id = <0x10022 0x5>;
+};

qcom/anorakp-idp-4kdisp-hsp.dtsi

@@ -0,0 +1 @@
+#include "anorak-idp-4kdisp-hsp.dtsi"

qcom/anorakp-idp-hmt.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorakp.dtsi"
+#include "anorakp-idp-hmt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP IDP HMT";
+	compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
+	qcom,board-id = <0x10022 0x1>;
+};

qcom/anorakp-idp-hmt.dtsi

@@ -0,0 +1 @@
+#include "anorak-idp-hmt.dtsi"

qcom/anorakp-idp-hsp-nodisplay.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorakp.dtsi"
+#include "anorakp-idp-hsp-nodisplay.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP IDP HSP with no display";
+	compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
+	qcom,board-id = <0x10022 0x7>;
+};

qcom/anorakp-idp-hsp-nodisplay.dtsi

@@ -0,0 +1 @@
+#include "anorak-idp-hsp-nodisplay.dtsi"

qcom/anorakp-idp-sd.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorakp.dtsi"
+#include "anorakp-idp-sd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP IDP Single Display";
+	compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
+	qcom,board-id = <0x10022 0x2>;
+};

qcom/anorakp-idp-sd.dtsi

@@ -0,0 +1 @@
+#include "anorak-idp-sd.dtsi"

qcom/anorakp-idp-top-hmt.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorakp.dtsi"
+#include "anorakp-idp-top-hmt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP IDP Topanga Hamilton";
+	compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
+	qcom,board-id = <0x10022 0x3>;
+};

qcom/anorakp-idp-top-hmt.dtsi

@@ -0,0 +1 @@
+#include "anorak-idp-top-hmt.dtsi"

qcom/anorakp-idp-top-hsp.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorakp.dtsi"
+#include "anorakp-idp-top-hsp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP IDP Topanga with EDP display + HSP";
+	compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
+	qcom,board-id = <0x10022 0x4>;
+};

qcom/anorakp-idp-top-hsp.dtsi

@@ -0,0 +1 @@
+#include "anorak-idp-top-hsp.dtsi"

qcom/anorakp-idp.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorakp.dtsi"
+#include "anorakp-idp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP IDP";
+	compatible = "qcom,anorakp-idp", "qcom,anorakp", "qcom,idp";
+	qcom,board-id = <0x10022 0x0>;
+};

qcom/anorakp-idp.dtsi

@@ -0,0 +1 @@
+#include "anorak-idp.dtsi"

qcom/anorakp-qxr-4kdisp-hmt-ufs-ref.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorakp.dtsi"
+#include "anorakp-qxr-4kdisp-hmt-ufs-ref.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP QXR HMT UFS REF + 4K Display";
+	compatible = "qcom,anorakp-qxr", "qcom,anorakp";
+	qcom,board-id = <0x10126 0x3>;
+};

qcom/anorakp-qxr-4kdisp-hmt-ufs-ref.dtsi

@@ -0,0 +1 @@
+#include "anorak-qxr-4kdisp-hmt-ufs-ref.dtsi"

qcom/anorakp-qxr-hmt-ufs-ref.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorakp.dtsi"
+#include "anorakp-qxr-hmt-ufs-ref.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP QXR HMT UFS REF";
+	compatible = "qcom,anorakp-qxr", "qcom,anorakp";
+	qcom,board-id = <0x10126 0x2>;
+};

qcom/anorakp-qxr-hmt-ufs-ref.dtsi

@@ -0,0 +1 @@
+#include "anorak-qxr-hmt-ufs-ref.dtsi"

qcom/anorakp-qxr-hmt.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorakp.dtsi"
+#include "anorakp-qxr-hmt.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP QXR HMT";
+	compatible = "qcom,anorakp-qxr", "qcom,anorakp";
+	qcom,board-id = <0x10026 0x1>;
+};

qcom/anorakp-qxr-hmt.dtsi

@@ -0,0 +1 @@
+#include "anorak-qxr-hmt.dtsi"

qcom/anorakp-qxr.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "anorakp.dtsi"
+#include "anorakp-qxr.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP QXR";
+	compatible = "qcom,anorakp-qxr", "qcom,anorakp";
+	qcom,board-id = <0x10026 0x0>;
+};

qcom/anorakp-qxr.dtsi

@@ -0,0 +1 @@
+#include "anorak-qxr.dtsi"

qcom/anorakp.dts

@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "anorakp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP SoC";
+	compatible = "qcom,anorakp";
+	qcom,board-id = <0 0>;
+};

qcom/anorakp.dtsi

@@ -0,0 +1,7 @@
+#include "anorak.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. AnorakP";
+	compatible = "qcom,anorakp";
+	qcom,msm-id = <649 0x10000>;
+};

qcom/platform_map.bzl

@@ -184,6 +184,26 @@ _platform_map = {
     "anorak": {
         "dtb_list": [
             {"name": "anorak.dtb"},
+            #TODO: Need to add anorakp
+            #{
+            #    "name": "anorakp.dtb",
+            #    "apq": True,
+            #},
+        ],
+        "dtbo_list": [
+            {"name": "anorak-idp-overlay.dtbo"},
+            {"name": "anorak-atp-overlay.dtbo"},
+            {"name": "anorak-qxr-overlay.dtbo"},
+            {"name": "anorak-idp-4kdisp-hmt-overlay.dtbo"},
+            {"name": "anorak-idp-4kdisp-hsp-overlay.dtbo"},
+            {"name": "anorak-idp-hmt-overlay.dtbo"},
+            {"name": "anorak-idp-hsp-nodisplay-overlay.dtbo"},
+            {"name": "anorak-idp-sd-overlay.dtbo"},
+            {"name": "anorak-idp-top-hmt-overlay.dtbo"},
+            {"name": "anorak-idp-top-hsp-overlay.dtbo"},
+            {"name": "anorak-qxr-4kdisp-hmt-ufs-ref-overlay.dtbo"},
+            {"name": "anorak-qxr-hmt-overlay.dtbo"},
+            {"name": "anorak-qxr-hmt-ufs-ref-overlay.dtbo"},
         ],
     },
     "niobe": {