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ARM: dts: msm: Merge kernel.lnx.5.4-200915 into msm-5.10

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Merge kernel.lnx.5.4-200915 into msm-5.10.

Change-Id: If85db2d0b92b484f2e439d72bee8c5e1056baa3f
This commit is contained in:
Elliot Berman
2020-12-17 06:33:10 -08:00
parent 2c3b609c38 e4c629d337
commit 7adfb2b429
279 changed files with 45626 additions and 864 deletions
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11
bindings/arm/coresight.txt
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@@ -161,9 +161,10 @@ its hardware characteristcs.
* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
use the SG mode on this system.
* Optional property for CATU :
* Optional property for CATU and APSS :
* interrupts : Exactly one SPI may be listed for reporting the address
error
error for CATU and four interrupts for TGU to get trigger from four
type of events.
<<<<<<< HEAD
* Required property for TPDAs:
@@ -196,6 +197,8 @@ its hardware characteristcs.
* qcom,msr-fix-req: boolean, indicating if MSRs need to be programmed
after enabling the subunit.
* qcom,cmb-msr-skip: boolean, indicating cmb MSR don't need to be programmed.
* qcom,hw-enable-check: Check if the tpdm need to be probed as some tpdms
are not enabled in secure device.
@@ -510,6 +513,10 @@ Example:
tgu-conditions = <4>;
tgu-regs = <4>;
tgu-timer-counters = <8>;
interrupts = <GIC_SPI 23 IRQ_TYPE_TRIGGER_HIGH>,
<GIC_SPI 24 IRQ_TYPE_TRIGGER_HIGH>,
<GIC_SPI 25 IRQ_TYPE_TRIGGER_HIGH>,
<GIC_SPI 26 IRQ_TYPE_TRIGGER_HIGH>;
coresight-name = "coresight-tgu-ipcb";

39
bindings/arm/msm/hh_watchdog.yaml Normal file
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@@ -0,0 +1,39 @@
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/arm/msm/hh_watchdog.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: QTI HH Watchdog
maintainers:
description: |+
Watchdog timer is configured with a bark and a bite time.
If the watchdog is not "pet" at regular intervals, the system
is assumed to have become non responsive and needs to be reset.
A warning in the form of a bark timeout leads to a bark interrupt
and a kernel panic. If the watchdog timer is still not reset,
a bite timeout occurs, which leads to a reset of the VM via
the hypervisor. The driver needs the petting time, and the bark
timeout to be programmed into the watchdog, as well as the bark irq.
The device tree parameters for the watchdog are:
properties:
compatible:
Usage: required
Value type: <string>
Definition: Must be "qcom,hh-watchdog"
interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should contain the bark irq number
example:
- |
wdog_hh: qcom,wdt_hh {
compatible = "qcom,hh-watchdog";
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
};
...

3
bindings/arm/msm/imem.yaml
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@@ -69,6 +69,9 @@ patternProperties:
- const: qcom,msm-imem-diag-dload
description: USB Diag download mode region
- const: qcom,msm-imem-pil-disable-timeout
description: Offset to set PIL debug cookie
reg:
description: Start address and the size of the region

21
bindings/arm/msm/msm.txt
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@@ -77,6 +77,9 @@ SoCs:
- SDXPRAIRIE
compatible = "qcom,sdxprairie"
- SDXLEMUR
compatible = "qcom,sdxlemur"
- SDMMAGPIE
compatible = "qcom,sdmmagpie"
@@ -127,6 +130,9 @@ Generic board variants:
- IOT device:
compatible = "qcom,iot"
- HDK device:
compatible = "qcom,hdk"
Boards (SoC type + board variant):
@@ -186,14 +192,20 @@ compatible = "qcom,kona-mtp"
compatible = "qcom,kona-cdp"
compatible = "qcom,kona-qrd"
compatible = "qcom,lahaina-rumi"
compatible = "qcom,lahaina-atp"
compatible = "qcom,lahaina-mtp"
compatible = "qcom,lahaina-cdp"
compatible = "qcom,lahaina-qrd"
compatible = "qcom,lahaina-qrd-module"
compatible = "qcom,shima-rumi"
compatible = "qcom,lahaina-hdk"
compatible = "qcom,lahainap-mtp"
compatible = "qcom,lahainap-cdp"
compatible = "qcom,lahainap-atp"
compatible = "qcom,lahainap-qrd"
compatible = "qcom,shima-rumi"
compatible = "qcom,shima-idp"
compatible = "qcom,shima-atp"
compatible = "qcom,shima-qrd"
compatible = "qcom,lito-rumi"
compatible = "qcom,lito-mtp"
compatible = "qcom,lito-cdp"
@@ -216,7 +228,14 @@ compatible = "qcom,adp-star"
compatible = "qcom,sdxprairie-rumi"
compatible = "qcom,sdxprairie-mtp"
compatible = "qcom,sdxprairie-cdp"
compatible = "qcom,sdxlemur-rumi"
compatible = "qcom,sdxlemur-mtp"
compatible = "qcom,sdxlemur-cdp"
compatible = "qcom,sdmmagpie-rumi"
compatible = "qcom,sdmmagpie-idp"
compatible = "qcom,sdmmagpie-qrd"
compatible = "qcom,holi-rumi"
compatible = "qcom,holi-mtp"
compatible = "qcom,holi-cdp"
compatible = "qcom,holi-qrd"
compatible = "qcom,holi-atp"

33
bindings/arm/msm/msm_watchdog.yaml
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@@ -44,35 +44,6 @@ properties:
Value type: <prop-encoded-array>
Definition: should contain bark and bite irq numbers
qcom,pet-time:
Usage: required
Value type: <u32>
Definition: Non zero time interval at which watchdog should be pet in ms.
qcom,bark-time:
Usage: required
Value type: <u32>
Definition: Non zero timeout value for a watchdog bark in ms.
qcom,userspace-watchdog:
Usage: optional
Value type: <boolean>
Definition: Allow enabling the userspace-watchdog feature. This feature
requires userspace to pet the watchdog every qcom,pet-time interval
in addition to the existing kernel-level checks.
This feature is supported through device sysfs files.
qcom,ipi-ping:
Usage: optional
Value type: <boolean>
Definition: send keep alive ping to other cpus if present
qcom,wakeup-enable:
Usage: optional
Value type: <boolean>
Definition: enable non secure watchdog to freeze / unfreeze
automatically across suspend / resume path.
example:
- |
wdog: qcom,wdt@17c10000{
@@ -81,9 +52,5 @@ example:
reg-names = "wdt-base";
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
<0 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,bark-time = <11000>;
qcom,pet-time = <9360>;
qcom,ipi-ping;
qcom,wakeup-enable;
};
...

17
bindings/arm/msm/qcom,llcc.txt
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@@ -12,7 +12,8 @@ Properties:
Usage: required
Value type: <string>
Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc"
or "qcom,shima-llcc" or "qcom,waipio-llcc".
or "qcom,shima-llcc" or "qcom,waipio-llcc"
or "qcom,sdxlemur-llcc".
"qcom,llcc-v2" must be appended for V2 hardware or
"qcom,llcc-v21" for V2.1.
@@ -34,6 +35,18 @@ Properties:
It's used for llcc cache single and double bit error detection
and reporting.
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: List of phandles and clock specifier pairs for the llcc perfmon
trace feature support.
- clock-names:
Usage: required
Value type: <stringlist>
Definition: List of clock input name strings sorted in the same
order as the clocks property. Definition must have
"qdss_clk"
Example:
cache-controller@1100000 {
@@ -41,4 +54,6 @@ Example:
reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_aop QDSS_CLK>;
clock-names = "qdss_clk";
};

15
bindings/arm/msm/rdbg-smp2p.txt Normal file
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@@ -0,0 +1,15 @@
Qualcomm Technologies, Inc. Remote Debugger (RDBG) driver
Required properties:
-compatible : Should be one of
To communicate with adsp
qcom,smp2p-interrupt-rdbg-2-in (inbound)
qcom,smp2p-interrupt-rdbg-2-out (outbound)
To communicate with cdsp
qcom,smp2p-interrupt-rdbg-5-in (inbound)
qcom,smp2p-interrupt-rdbg-5-out (outbound)
Example:
qcom,smp2p_interrupt_rdbg_2_in {
compatible = "qcom,smp2p-interrupt-rdbg-2-in";
};

40
bindings/arm/msm/rpm-smd.txt Normal file
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@@ -0,0 +1,40 @@
Resource Power Manager(RPM)
RPM is a dedicated hardware engine for managing shared SoC resources,
which includes buses, clocks, power rails, etc. The goal of RPM is
to achieve the maximum power savings while satisfying the SoC's
operational and performance requirements. RPM accepts resource
requests from multiple RPM masters. It arbitrates and aggregates
the requests, and configures the shared resources. The RPM masters
are the application processor, the modem processor, as well as hardware
accelerators. The RPM driver communicates with the hardware engine using
SMD.
The devicetree representation of the RPM block should be:
Required properties
- compatible: "qcom,rpm-smd"
- rpm-channel-name: The string corresponding to the channel name of the
peripheral subsystem. Required for both smd and
glink transports.
- rpm-channel-type: The interal SMD edge for this subsystem found in
<soc/qcom/smd.h>
- interrupts: The IRQ used by remote processor to inform APSS about
reception of response message packet.
Optional properties
- rpm-standalone: Allow RPM driver to run in standalone mode irrespective of RPM
channel presence.
- reg: Contains the memory address at which rpm messaging format version is
stored. If this field is not present, the target only supports v0 format.
Example:
qcom,rpm-smd {
compatible = "qcom,rpm-smd";
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-channel-name = "rpm_requests";
qcom,rpm-channel-type = 15; /* APPS_RPM_SMD */
}
}

47
bindings/arm/msm/rpm_master_stats.txt Normal file
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@@ -0,0 +1,47 @@
* RPM Stats
RPM maintains a counter of the masters i.e APPS, MPPS etc
number of times the SoC entered a deeper sleep mode involving
lowering or powering down the backbone rails - Cx and Mx and
the oscillator clock, XO.
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: Should be "qcom,rpm-master-stats".
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: The address on the RPM RAM from where the stats are read
should be provided as "phys_addr_base". The offset
from which the stats are available should be provided as
"offset_addr".
- reg-names:
Usage: required
Value type: <prop-encoded-array>
Definition: Provides labels for the reg property.
- qcom,masters:
Usage: required
Value tye: <string list>
Defination: Provides the masters list.
qcom,master-offset:
Usage: required
Value tye: <prop-encoded-array>
Defination: Provides the masters list
EXAMPLE:
qcom,rpm-master-stats@60150 {
compatible = "qcom,rpm-master-stats";
reg = <0x45f0150 0x5000>;
qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ";
qcom,master-stats-version = <2>;
qcom,master-offset = <4096>;
};

19
bindings/arm/msm/system_pm_rpm.txt Normal file
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@@ -0,0 +1,19 @@
SYSTEM PM
System PM device is a virtual device that handles all CPU subsystem low power
mode activties. When entering core shutdown, resource state that were requested
from the processor may be relinquished and set to idle and restored when the
cores are brought out of sleep.
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,system-pm-rpm".
EXAMPLE
system_pm_rpm {
compatible = "qcom,system-pm-rpm";
};

2
bindings/bluetooth/btpower.txt
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@@ -21,6 +21,8 @@ Optional properties:
- qcom,bt-vdd-xtal-supply: Bluetooth VDD XTAL regulator handle
- qcom,bt-vdd-core-supply: Bluetooth VDD CORE regulator handle
- qcom,bt-vdd-asd-supply: Bluetooth VDD regulator handle for antenna switch
- reg: Memory regions defined as starting address and size
- reg-names: Names of the memory regions defined in reg entry
diversity.
- qcom,bt-chip-pwd-supply: Chip power down gpio is required when bluetooth
module and other modules like wifi co-exist in a singe chip and

2
bindings/clock/qcom,aop-qmp.txt
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@@ -7,6 +7,8 @@ Required properties :
- mboxes : list of QMP mailbox phandle and channel identifier tuples.
- mbox-names: List of identifier strings for each mailbox channel.
Must contain "qdss_clk".
- qcom,clk-stop-bimc-log: Presence indicates a BIMC logging request will
be sent to AOP during kernel panic.
Example :
clock_qdss: qcom,aopclk {

7
bindings/clock/qcom,camcc.txt
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@@ -2,9 +2,12 @@ Qualcomm Camera Clock & Reset Controller Binding
------------------------------------------------
Required properties :
- compatible : shall contain "qcom,sdm845-camcc" or "qcom,lahaina-camcc",
- compatible : shall contain
"qcom,sdm845-camcc"
"qcom,lahaina-camcc"
"qcom,lahaina-camcc-v2"
"qcom,shima-camcc"
"qcom,waipio-camcc".
"qcom,waipio-camcc"
- reg : shall contain base register location and length.
- #clock-cells : from common clock binding, shall contain 1.
- #reset-cells : from common reset binding, shall contain 1.

4
bindings/clock/qcom,debugcc.txt
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@@ -6,7 +6,9 @@ Required properties :
"qcom,lahaina-debugcc"
"qcom,shima-debugcc"
"qcom,waipio-debugcc".
"qcom,holi-debugcc"
"qcom,sdxlemur-debugcc"
"qcom,waipio-debugcc"
- qcom,gcc: phandle to the GCC device node.
- qcom,videocc: phandle to the Video CC device node.

1
bindings/clock/qcom,gcc.txt
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@@ -30,6 +30,7 @@ Required properties :
"qcom,gcc-sa8155-v2"
"qcom,shima-gcc"
"qcom,holi-gcc"
"qcom,sdxlemur-gcc"
"qcom,waipio-gcc"
- reg : shall contain base register location and length

7
bindings/clock/qcom,rpmcc.txt
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@@ -24,6 +24,7 @@ Required properties :
"qcom,rpmcc-msm8998", "qcom,rpmcc"
"qcom,rpmcc-qcs404", "qcom,rpmcc"
"qcom,rpmcc-sdm660", "qcom,rpmcc"
"qcom,rpmcc-holi", "qcom,rpmcc"
- #clock-cells : shall contain 1
@@ -35,6 +36,12 @@ suspended or in deep idle. If it is important that the clock keeps running
during system suspend, you need to specify the non-active clock, the one
not containing *_A_* in the enumerator name.
Optional properties:
- qcom,hw-clk-handoff : Add this property to support initial high votes on the
to be sent to RPM as proxy votes.
- qcom,bimc-log-stop : Add this property to request RPM to stop the bimc
logging.
Example:
smd {
compatible = "qcom,smd";

1
bindings/clock/qcom,rpmh-clk.txt
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@@ -13,6 +13,7 @@ Required properties :
"qcom,kona-rpmh-clk",
"qcom,sdm845-rpmh-clk"
"qcom,sm8150-rpmh-clk"
"qcom,sdxlemur-rpmh-clk"
- #clock-cells : must contain 1

48
bindings/clock/qcom,sdxlemur-apsscc.txt Normal file
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@@ -0,0 +1,48 @@
Qualcomm Technologies, Inc. SDXLEMUR CPU clock driver
-----------------------------------------------------
It is the clock controller driver which provides higher frequency
clocks and allows CPU frequency scaling on qcs405 based platforms.
Required properties:
- compatible: Shall contain following:
"qcom,sdxlemur-apsscc"
- clocks: Phandle to the clock device.
- clock-names: Names of the used clocks. Shall contain following:
"xo_ao", "gpll0_ao"
- reg: Shall contain base register offset and size.
- reg-names: Names of the bases for the above registers. Shall contain following:
"apcs_cmd", "apcs_pll"
- vdd_dig_ao-supply: The regulator(active only) powering the digital logic of APSS PLL.
- vdd_hf_pll-supply: The regulator(active only) powering the Analog logic of APSS PLL.
- cpu-vdd-supply: The regulator powering the APSS RCG.
- qcom,speedX-bin-vZ: A table of CPU frequency (Hz) to regulator voltage (uV) mapping.
Format: <freq uV>
This represents the max frequency possible for each possible
power configuration for a CPU that's binned as speed bin X,
speed bin revision Z. Version can be between [0-3].
- #clock-cells: Shall contain 1.
Optional properties:
- reg-names: "efuse"
- qcom,cpucc-init-rate: Initial rate which needs to be set from cpu driver.
Example:
clock_cpu: qcom,clock-cpu@17808100 {
compatible = "qcom,sdxlemur-apsscc";
clocks = <&rpmhcc RPMH_CXO_CLK>>;
<&gcc GPLL0_AO_OUT_MAIN>;;
clock-names = "xo_ao", "gpll0_ao" ;
reg = <0x17810008 0x8>,
<0x17808100 0x44>;
reg-names = "apcs_cmd" , "apcs_pll";
vdd-lucid-pll-supply = <&VDD_CX_LEVEL_AO>;
cpu-vdd-supply = <&VDD_CX_LEVEL_AO>;
qcom,speed0-bin-v0 =
< 0 RPMH_REGULATOR_LEVEL_OFF>,
< 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
< 576000000 RPMH_REGULATOR_LEVEL_SVS>,
< 1094400000 RPMH_REGULATOR_LEVEL_NOM>,
< 1555200000 RPMH_REGULATOR_LEVEL_TURBO>;
#clock-cells = <1>;
};

16
bindings/cnss/cnss-wlan.txt
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@@ -69,6 +69,22 @@ Optional properties:
- qcom,mhi: phandle to indicate the device which needs MHI support.
- qcom,cap-tsf-gpio: WLAN_TSF_CAPTURED GPIO signal specified by the chip
specifications, should be drived depending on products
- cnss-daemon-support: Boolean property to decide whether cnss_daemon
userspace QMI client is supported.
- use-nv-mac: Boolean property to indicate whether NV MAC is used or not.
- qcom,set-wlaon-pwr-ctrl: Boolean property to indicate if set
WLAON_QFPROM_PWR_CTRL_REG register during power on
and off sequences.
- use-pm-domain: Boolean property to indicate if driver needs to use PM
domain or not.
- qcom,wlan-cbc-enabled: boolean property to control cold boot calibration
- interconnects: Interconnect framework setup for bus configuration
- interconnect-names: Interconnect path names as strings
- qcom,icc-path-count: Number of Interconnect paths for this platform
- qcom,bus-bw-cfg-count: Number of bus bandwidth voting cases
- qcom,bus-bw-cfg: Bus bandwidth voting data
- qcom,tcs_offset_int_pow_amp_vreg: TCS CMD register offset for Voltage
regulator used in internal power amplifier for QCA6490
Example:

78
bindings/cnss/icnss.txt Normal file
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@@ -0,0 +1,78 @@
* Qualcomm Technologies Inc Q6 Integrated connectivity Platform Driver
This platform driver adds support for the Integrated WLAN that runs
on Q6 based platforms. WLAN FW on these architecture runs on Q6. This
platform driver communicates with WLAN FW over QMI, WLAN on/off messages
to FW are communicated thru this interface. This driver also listens to
WLAN PD restart notifications.
Required properties:
- compatible: "qcom,icnss" for ADRASTEA architecture
"qcom,wcn6750" for iWCN architecture
- reg: Memory regions defined as starting address and size
- reg-names: Names of the memory regions defined in reg entry
- interrupts: Copy engine interrupt table
- qcom,wlan-msa-memory: MSA memory size
- clocks: List of clock phandles
- clock-names: List of clock names corresponding to the "clocks" property
- iommus: SMMUs and corresponding Stream IDs needed by WLAN
- qcom,wlan-smmu-iova-address: I/O virtual address range as <start length>
format to be used for allocations associated between WLAN and SMMU
Optional properties:
- <supply-name>-supply: phandle to the regulator device tree node
optional "supply-name" is "vdd-0.8-cx-mx".
- qcom,<supply>-config: Specifies voltage levels for supply. Should be
specified in pairs (min, max), units uV. There can
be optional load in uA and Regulator settle delay in
uS.
- qcom,icnss-vadc: VADC handle for vph_pwr read APIs.
- qcom,icnss-adc_tm: VADC handle for vph_pwr notification APIs.
- io-channels: IIO channel to monitor for vph_pwr power.
- io-channel-names: IIO channel name as per the client name.
- qcom,smmu-s1-bypass: Boolean context flag to set SMMU to S1 bypass
- qcom,wlan-msa-fixed-region: phandle, specifier pairs to children of /reserved-memory
- qcom,hyp_disabled: Boolean context flag to disable hyperviser
WLAN SMP2P sub nodes
- qcom,smp2p_map_wlan_1_in - represents the in smp2p to
wlan driver from modem.
Example:
qcom,icnss@0a000000 {
compatible = "qcom,icnss";
reg = <0x0a000000 0x1000000>;
reg-names = "membase";
clocks = <&clock_gcc clk_aggre2_noc_clk>;
clock-names = "smmu_aggre2_noc_clk";
iommus = <&anoc2_smmu 0x1900>,
<&anoc2_smmu 0x1901>;
qcom,wlan-smmu-iova-address = <0 0x10000000>;
interrupts =
<0 130 0 /* CE0 */ >,
<0 131 0 /* CE1 */ >,
<0 132 0 /* CE2 */ >,
<0 133 0 /* CE3 */ >,
<0 134 0 /* CE4 */ >,
<0 135 0 /* CE5 */ >,
<0 136 0 /* CE6 */ >,
<0 137 0 /* CE7 */ >,
<0 138 0 /* CE8 */ >,
<0 139 0 /* CE9 */ >,
<0 140 0 /* CE10 */ >,
<0 141 0 /* CE11 */ >;
qcom,wlan-msa-memory = <0x200000>;
qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
qcom,smmu-s1-bypass;
vdd-0.8-cx-mx-supply = <&pm8998_l5>;
qcom,vdd-0.8-cx-mx-config = <800000 800000 2400 1000>;
qcom,hyp_disabled;
qcom,smp2p_map_wlan_1_in {
interrupts-extended = <&smp2p_wlan_1_in 0 0>,
<&smp2p_wlan_1_in 1 0>;
interrupt-names = "qcom,smp2p-force-fatal-error",
"qcom,smp2p-early-crash-ind";
};
};

8
bindings/cpufreq/cpufreq-qcom-hw.txt
View File

@@ -42,6 +42,14 @@ Properties:
Definition: Indicate to check for Enable of FW before registering
with cpufreq.
- qcom,perf-lock-support
Usage: Optional
Value type: bool
Definition: Indicate to check for performance lock support in FW.
In case this property is present, the reg & reg-names
should have the "pdmem-domainX" to indicate the
corresponding bases.
* Property qcom,freq-domain
Devices supporting freq-domain must set their "qcom,freq-domain" property with
phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.

12
bindings/devfreq/devfreq_icc.txt
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@@ -8,6 +8,7 @@ CPU, GPU) master port(s) to the slave (Eg: DDR) port(s).
Required properties:
- compatible: Must be "qcom,devfreq-icc" or "qcom,devfreq-icc-ddr"
or "qcom,devfreq-icc-llcc" or "qcom,devfreq-icc-l3"
or "qcom,devfreq-icc-l3bw"
- interconnects: Pairs of phandles and interconnect provider specificers
to denote the edge source and destination ports of the
desired interconnect path.
@@ -16,12 +17,17 @@ Required properties:
requested from the device master port to the slave port.
The list of values depend on the supported bus/slave
frequencies and the bus width. Required for all devices
except those compatible with "qcom,devfreq-icc-l3".
except those compatible with "qcom,devfreq-icc-l3" or
"qcom,devfreq-icc-l3bw".
- reg: Physical base address and region size of the memory
mapped registers containing the device's frequency
table. Required for "qcom,devfreq-icc-l3" devices.
table. Required for "qcom,devfreq-icc-l3" and
"qcom,devfreq-icc-l3bw" devices.
- reg-names: Name used for the above registers. Expected name is
"ftbl-base". Required for "qcom,devfreq-icc-l3" devices.
"ftbl-base". Required for "qcom,devfreq-icc-l3"
and "qcom,devfreq-icc-l3bw" devices.
- qcom,bus-width: Bus width of the interconnect path. Only required for
"qcom,devfreq-icc-l3bw" devices.
Optional properties:
- qcom,active-only: Indicates that the bandwidth votes need to be
enforced only when the CPU subsystem is active.

125
bindings/display/bridge/lt9611uxc.txt Normal file
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@@ -0,0 +1,125 @@
LT9611uxc DSI to HDMI bridge
Required properties:
- compatible: Must be "lt,lt9611uxc"
- reg: Main I2C slave ID (for I2C host driver)
- lt,irq-gpio: Main IRQ gpio mapping
- lt,reset-gpio Main reset gpio mapping
Optional properties:
- lt,hdmi-ps-gpio: gpio mapping for HDMI PS
- lt,hdmi-en-gpio: gpio mapping for HDMI EN
- lt,supply-entries: A node that lists the elements of the supply used to
power the bridge. There can be more than one instance
of this binding, in which case the entry would be
appended with the supply entry index.
e.g. lt,supply-entry@0
-- lt,supply-name: name of the supply (vdd/vcc)
-- lt,supply-min-voltage: minimum voltage level (uV)
-- lt,supply-max-voltage: maximum voltage level (uV)
-- lt,supply-enable-load: load drawn (uA) from enabled supply
-- lt,supply-disable-load: load drawn (uA) from disabled supply
-- lt,supply-ulp-load: load drawn (uA) from supply in ultra-low power mode
-- lt,supply-pre-on-sleep: time to sleep (ms) before turning on
-- lt,supply-post-on-sleep: time to sleep (ms) after turning on
-- lt,supply-pre-off-sleep: time to sleep (ms) before turning off
-- lt,supply-post-off-sleep: time to sleep (ms) after turning off
- lt,non-pluggable: Boolean to indicate if display is non pluggable.
- lt,customize-modes: Customized modes when it's non-pluggable display.
e.g. lt,customize-mode-id@0
-- lt,mode-h-active: Horizontal active pixels for this mode.
-- lt,mode-h-front-porch: Horizontal front porch in pixels for this mode.
-- lt,mode-h-pulse-width: Horizontal sync width in pixels for this mode.
-- lt,mode-h-back-porch: Horizontal back porch in pixels for this mode.
-- lt,mode-h-active-high: Boolean to indicate if mode horizontal polarity is active high.
-- lt,mode-v-active: Vertical active lines for this mode.
-- lt,mode-v-front-porch: Vertical front porch in lines for this mode.
-- lt,mode-v-pulse-width: Vertical sync width in lines for this mode.
-- lt,mode-v-back-porch: Vertical back porch in lines for this mode.
-- lt,mode-v-active-high: Boolean to indicate if mode vertical polarity is active high.
-- lt,mode-refersh-rate: Mode refresh rate in hertz.
-- lt,mode-clock-in-khz: Mode pclk in KHz.
Required nodes:
The LT9611 has one video port. Its connection is modelled using the OF
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
Video port 0 is for the DSI input. The remote endpoint phandle should
be a reference to a valid mipi_dsi_host device node.
Example:
&qupv3_se9_i2c {
status = "okay";
lt9611@3b {
compatible = "lt,lt9611uxc";
reg = <0x3b>;
interrupt-parent = <&tlmm>;
interrupts = <125 0>;
interrupt-names = "lt_irq";
lt,irq-gpio = <&tlmm 125 0x0>;
lt,reset-gpio = <&tlmm 134 0x0>;
lt,hdmi-ps-gpio = <&tlmm 136 0x0>;
lt,hdmi-en-gpio = <&tlmm 137 0x0>;
vcc-supply = <&pm660l_l6>;
vdd-supply = <&pm660_l11>;
lt,supply-entries {
#address-cells = <1>;
#size-cells = <0>;
lt,supply-entry@0 {
reg = <0>;
lt,supply-name = "vcc";
lt,supply-min-voltage = <3300000>;
lt,supply-max-voltage = <3300000>;
lt,supply-enable-load = <200000>;
lt,supply-post-on-sleep = <50>;
};
lt,supply-entry@1 {
reg = <1>;
lt,supply-name = "vdd";
lt,supply-min-voltage = <1800000>;
lt,supply-max-voltage = <1800000>;
lt,supply-enable-load = <200000>;
lt,supply-post-on-sleep = <50>;
};
};
lt,customize-modes {
lt,customize-mode-id@0 {
lt,mode-h-active = <1920>;
lt,mode-h-front-porch = <88>;
lt,mode-h-pulse-width = <44>;
lt,mode-h-back-porch = <148>;
lt,mode-h-active-high;
lt,mode-v-active = <1080>;
lt,mode-v-front-porch = <4>;
lt,mode-v-pulse-width = <5>;
lt,mode-v-back-porch = <36>;
lt,mode-v-active-high;
lt,mode-refresh-rate = <60>;
lt,mode-clock-in-khz = <148500>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lt9611_in: endpoint {
remote-endpoint = <&ext_dsi_out>;
};
};
};
};
};

10
bindings/dma/qcom_gpi.txt
View File

@@ -74,6 +74,16 @@ Optional property:
Value type: tuple of <address size>.
Definition: Indicates the range of addresses that the dma layer will use.
- qcom,le-vm
Usage: optional
Value type: boolean
Definition: flag to support I2C functionality in trusted VM.
- qcom,static-gpii-mask
Usage: optional
Value type: boolean
Definition: GPII number statically assigned to TUI LA touch se.
========
Example:
========

11
bindings/gpu/adreno.txt
View File

@@ -3,7 +3,10 @@ Qualcomm Technologies, Inc. GPU
Qualcomm Technologies, Inc. Adreno GPU
Required properties:
- compatible: Must be "qcom,kgsl-3d0" and "qcom,kgsl-3d"
- compatible: Must be "qcom,kgsl-3d0".
May also includes "qcom,adreno-gpu-*" for few targets.
Must include "qcom,adreno-gpu-a619-holi" for Holi target.
Must include "qcom,adreno-gpu-a660-shima" for Shima target.
- reg: Specifies the list of register regions for the device.
- reg-names: Resource names used for the register regions specified
in reg.
@@ -195,9 +198,9 @@ Optional Properties:
baseAddr - base address of the qtimer memory region
size - size of the qtimer region
- qcom,tsens-name:
Specify the name of GPU temperature sensor. This name will be used
to get the temperature from the thermal driver API.
- qcom,tzone-names:
Specify the names of GPU thermal zones. These will be used
to get gpu temperature from the thermal driver API.
- qcom,enable-midframe-timer:
Boolean. Enables the use of midframe sampling timer. This timer

177
bindings/haven/qcom,hypervisor.yml Normal file
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@@ -0,0 +1,177 @@
%YAML 1.2
---
$id: http://devicetree.org/schemas/haven/qcom,hypervisor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hypervisor node to define virtual devices and other services.
maintainers:
- Murali Nalajala <mnalajal@quicinc.com>
description: |+
Top-level node named /hypervisor that describes virtual devices and other
services.
properties:
compatible:
oneOf:
items:
- const: qcom,haven-hypervisor-1.0
- const: qcom,haven-hypervisor
properties:
"#address-cells":
const: 2
"#size-cells":
description: must be 0, because capability IDs are not memory address
ranges and do not have a size.
const: 0
required:
- compatible
- "#address-cells"
- "#size-cells"
description: |+
The VM Identification is a virtual node that conveys to the VM information
about itself in the context of the hypervisor-based system and may be
present as a child of the /hypervisor node
properties:
compatible:
oneOf:
description: |+
Must contain the VM-ID compatible string, which is provisionally
specified as "qcom,haven-vm-id". This should be preceded by
a string that specifies the VM ID API version, which is currently
1.0, thus "qcom,haven-vm-id-1.0".
items:
- const: qcom,haven-vm-id-1.0
- const: qcom,haven-vm-id
properties:
qcom,vendor:
description: must contain the VM vendor string, for example: "Qualcomm".
$ref: /schemas/types.yaml#/definitions/string
qcom,vmid:
$ref: /schemas/types.yaml#/definitions/uint32
description: must contain the hypervisor VMID of the VM, as
a 32-bit value
qcom,owner-vmid:
$ref: /schemas/types.yaml#/definitions/uint32
description: Contains the hypervisor VMID of the VM’s owner. The owner
is the VM that allocated and created the VM. VMs directly
managed by the resource manager, such as the HLOS do not
have an owner.
qcom,image-name:
$ref: /schemas/types.yaml#/definitions/string
description: contains the VM image name string.
qcom,swid:
$ref: /schemas/types.yaml#/definitions/uint32
description: must contain the Qualcomm PIL software ID value.
required:
- compatible
- qcom,vmid
- qcom,owner-vmid
description: |+
Resource Manager node which is required to communicate to Resource
Manager VM using RM Message Queues.
properties:
compatible:
oneOf:
description:
The resource manager RPC communicate link is required to be in the
device-tree of a VM at boot, without it, a VM may be unable to
communicate with the Resource Manager. Resource Manager VM can
support implementation of various versions i.e 1.0 or 2.0
items:
- const: qcom,resource-manager-1-0
- const: qcom,resource-manager
- const: qcom,haven-message-queue
- const: qcom,haven-capability
interrupts:
maxItems: 2
reg:
maxItems: 2
qcom,is-full-duplex:
$ref: /schemas/types.yaml#/definitions/flag
description: This node is a pair of message queues i.e. Tx and Rx
qcom,tx-message-size:
$ref: /schemas/types.yaml#/definitions/uint32
description: maximum message size in bytes, >= 240 bytes for RM IPC
qcom,tx-queue-depth:
$ref: /schemas/types.yaml#/definitions/uint32
description: depth(size) of transmit queue in hypervisor
qcom,rx-message-size:
$ref: /schemas/types.yaml#/definitions/uint32
description: maximum message size in bytes, >= 240 bytes for RM IPC
qcom,rx-queue-depth:
$ref: /schemas/types.yaml#/definitions/uint32
description: depth(size) of receive queue in hypervisor
qcom,console-dev:
$ref: /schemas/types.yaml#/definitions/flag
description: if set, the resource-manger will accept console logs
from the VM
qcom,free-irq-start:
$ref: /schemas/types.yaml#/definitions/uint32
description: first VIRQ number which is free for virtual interrupt
use. Here SPI 0 = VIRQ 32.
required:
- compatible
- interrupts
- reg
- qcom,is-full-duplex
examples:
- |
hypervisor {
#address-cells = <2>;
#size-cells = <0>;
compatible = "qcom,haven-hypervisor-1.0", "qcom,haven-hypervisor",
"simple-bus";
name = "hypervisor";
qcom,haven-vm {
compatible = "qcom,haven-vm-id-1.0", "qcom,haven-vm-id";
qcom,vendor = "Qualcomm Technologies, Inc.";
qcom,vmid = <45>;
qcom,owner-vmid = <3>;
};
qcom,resource-manager-rpc@0000000000000001 {
compatible = "qcom,resource-manager-1-0", "qcom,resource-manager",
"qcom,haven-message-queue", "qcom,haven-capability";
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, /* TX full IRQ */
<GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; /* RX empty IRQ */
reg = <0x00000000 0x00000000>, <0x00000000 0x00000001>;
/* TX, RX cap ids */
qcom,is-full-duplex;
qcom,free-irq-start = <0>;
qcom,tx-queue-depth = <8>;
qcom,tx-message-size = <0xf0>;
qcom,rx-queue-depth = <8>;
qcom,rx-message-size = <0xf0>;
};
};

74
bindings/hwmon/qcom,amoled-ecm.yaml Normal file
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@@ -0,0 +1,74 @@
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/hwmon/qcom,amoled-ecm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. AMOLED ECM binding
maintainers:
- Shyam Kumar Thella <sthella@qti.qualcomm.com>
description: |
Qualcomm Technologies, Inc. AMOLED ECM supports measurement of OLED
display power/current consumption with a time granularity in sub-frame
or multiple frames of image data. A power measurement can be for a
shorter period or for a longer period.
properties:
compatible:
const: qcom,amoled-ecm
reg:
description: Base address of AMOLED AB module. Registers of
AMOLED ECM are part of AMOLED AB module.
maxItems: 1
nvmem-names:
minItems: 1
description: Array of one or more nvmem device name(s) for ECM
measurement.
items:
- const: amoled-ecm-sdam0
- const: amoled-ecm-sdam1
$ref: /schemas/types.yaml#/definitions/string-array
nvmem:
minItems: 1
description: Array of one or more phandles of the nvmem device(s)
for ECM measurement.
$ref: /schemas/nvmem/nvmem.yaml
interrupts:
description: Specifies the interrupts for nvmem devices used by
AMOLED ECM.
minItems: 1
$ref: /schemas/interrupts.yaml
interrupt-names:
description: Specifies the interrupt names for nvmem devices used
by AMOLED ECM.
minItems: 1
items:
- const: ecm-sdam0
- const: ecm-sdam1
$ref: /schemas/types.yaml#/definitions/string-array
required:
- compatible
- reg
- nvmem-names
- nvmem
- interrupt-names
- interrupts
examples:
- |
qcom,amoled-ecm@f900 {
compatible = "qcom,amoled-ecm";
reg = <0xf900>;
nvmem-names = "amoled-ecm-sdam0", "amoled-ecm-sdam1";
nvmem = <&pmk8350_sdam_13>, <&pmk8350_sdam_14>;
interrupt-names = "ecm-sdam0", "ecm-sdam1";
interrupts = <0x0 0x7c 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x7d 0x1 IRQ_TYPE_EDGE_RISING>;
};

4
bindings/iio/adc/qcom,spmi-vadc.txt
View File

@@ -83,7 +83,9 @@ Channel node properties:
fed to VADC. The configuration for this node is to know the
pre-determined ratio and use it for post scaling. Select one from
the following options.
<1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10>
<1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10>, <1 16>,
<32 100>, <14, 100>, <28, 100>, <1000 305185>, <1000 610370>
If property is not found default value depending on chip will be used.
- qcom,ratiometric:

27
bindings/input/qcom-hv-haptics.txt
View File

@@ -23,7 +23,8 @@ Properties:
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: Register base for HAPTICS_CFG and HAPTICS_PATTERN modules.
Definition: Register base for following haptics modules: HAPTICS_CFG,
HAPTICS_PATTERN, HAPTICS_BOOST.
- interrupts:
Usage: required
@@ -99,6 +100,25 @@ Properties:
calibration settings. Please refer to nvmem bindings as
described in bindings/nvmem/nvmem.txt.
- nvmem-names:
Usage: optional
Value type: <string>
Definition: The nvmem device name of the SDAM module used for haptics
configuration. It must be "hap_cfg_sdam".
- nvmem:
Usage: optional
Value type: <phandle>
Definition: Phandle of the nvmem device used for haptics configuration.
Please refer to nvmem bindings as described in bindings/nvmem/nvmem.txt.
- qcom,pbs-client:
Usage: optional
Value type: <phandle>
Definition: Phandle of the PBS client used for triggering PBS to configure
haptics ISC (short circuit current) config during LRA impedance
detection.
The following properties are only required when LRA actuator is used:
- qcom,lra-period-us:
@@ -242,11 +262,14 @@ different vibration effects:
Example:
qcom,hv-haptics@f000 {
compatible = "qcom,hv-haptics";
reg = <0xf000>, <0xf100>;
reg = <0xf000>, <0xf100>, <0xf200>;
interrupts = <0x3 0xf0 0x1 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "fifo-empty";
nvmem-cell-names = "hap_cl_brake";
nvmem-cells = <&hap_cl_brake>;
nvmem-names = "hap_cfg_sdam";
nvmem = <&pmk8350_sdam_46>;
qcom,pbs-client = <&pm8350b_pbs2>;
qcom,vmax-mv = <900>;
qcom,brake-mode = <BRAKE_CLOSE_LOOP>;
qcom,brake-pattern = /bits/ 8 <0xff 0x3f 0x1f>;

71
bindings/input/touchscreen/synaptics_tcm_i2c.txt Normal file
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@@ -0,0 +1,71 @@
Synaptics TCM I2C touchscreen controller
Required properties:
- compatible:
should be "synaptics,tcm-i2c"
- reg:
i2c slave address of device
- interrupt-parent:
hardware controller of interrupt signal
- interrupts:
gpio number and flags of interrupt signal
- vdd-supply:
digital power source
- avdd-supply:
analog power source
- pinctrl-names:
- pinctrl-0:
- pinctrl-1:
should be defined if using pinctrl framework
"pmx_ts_active": active configuration of pins
"pmx_ts_suspend": disabled configuration of pins
- synaptics,bus-reg-name:
name of digital power source regulator
- synaptics,pwr-reg-name:
name of analog power source regulator
- synaptics,irq-gpio:
interrupt hardware controller, gpio number, and flags
- synaptics,irq-on-state:
active state of interrupt signal
Optional properties:
- synaptics,power-gpio:
hardware controller and gpio number of power control signal
- synaptics,power-delay-ms:
delay time in ms after powering on device
- synaptics,reset-gpio:
hardware controller and gpio number of reset signal
- synaptics,reset-delay-ms:
delay time in ms after issuing reset to device
- synaptics,reset-on-state:
active state of reset signal
- synaptics,reset-active-ms:
active duration in ms of reset signal
- synaptics,x-flip:
flip x axis
- synaptics,y-flip:
flip y axis
- synaptics,swap-axes:
swap x and y axes
- synaptics,ubl-i2c-addr:
i2c slave address of device in microbootloader mode
Example:
synaptics_tcm@2c {
compatible = "synaptics,tcm-i2c";
reg = <0x2c>;
interrupt-parent = <&msm_gpio>;
interrupts = <65 0x2008>;
vdd-supply = <&pm8994_lvs2>;
avdd-supply = <&pm8994_l22>;
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_suspend>;
synaptics,pwr-reg-name = "avdd";
synaptics,bus-reg-name = "vdd";
synaptics,irq-gpio = <&msm_gpio 65 0x2008>;
synaptics,irq-on-state = <0>;
synaptics,power-delay-ms = <200>;
synaptics,reset-delay-ms = <200>;
synaptics,ubl-i2c-addr = <0x2c>;
};

86
bindings/input/touchscreen/synaptics_tcm_spi.txt Normal file
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@@ -0,0 +1,86 @@
Synaptics TCM SPI touchscreen controller
Required properties:
- compatible:
should be "synaptics,tcm-spi"
- reg:
should be 0
- spi-max-frequency:
maximum spi clock frequency
- interrupt-parent:
hardware controller of interrupt signal
- interrupts:
gpio number and flags of interrupt signal
- vdd-supply:
digital power source
- avdd-supply:
analog power source
- pinctrl-names:
- pinctrl-0:
- pinctrl-1:
should be defined if using pinctrl framework
"pmx_ts_active": active configuration of pins
"pmx_ts_suspend": disabled configuration of pins
- synaptics,bus-reg-name:
name of digital power source regulator
- synaptics,pwr-reg-name:
name of analog power source regulator
- synaptics,irq-gpio:
interrupt hardware controller, gpio number, and flags
- synaptics,irq-on-state:
active state of interrupt signal
Optional properties:
- synaptics,spi-mode:
spi mode
- synaptics,byte-delay-us:
inter-byte delay time in us
- synaptics,block-delay-us:
inter-block delay time in us
- synaptics,power-gpio:
hardware controller and gpio number of power control signal
- synaptics,power-delay-ms:
delay time in ms after powering on device
- synaptics,reset-gpio:
hardware controller and gpio number of reset signal
- synaptics,reset-delay-ms:
delay time in ms after issuing reset to device
- synaptics,reset-on-state:
active state of reset signal
- synaptics,reset-active-ms:
active duration in ms of reset signal
- synaptics,x-flip:
flip x axis
- synaptics,y-flip:
flip y axis
- synaptics,swap-axes:
swap x and y axes
- synaptics,ubl-max-freq:
maximum spi clock frequency for microbootloader mode
- synaptics,ubl-byte-delay-us:
inter-byte delay time in us for microbootloader mode
Example:
synaptics_tcm@0 {
compatible = "synaptics,tcm-spi";
reg = <0>;
spi-max-frequency = <10000000>;
interrupt-parent = <&msm_gpio>;
interrupts = <65 0x2008>;
vdd-supply = <&pm8994_lvs2>;
avdd-supply = <&pm8994_l22>;
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_suspend>;
synaptics,bus-reg-name = "vdd";
synaptics,pwr-reg-name = "avdd";
synaptics,irq-gpio = <&msm_gpio 65 0x2008>;
synaptics,irq-on-state = <0>;
synaptics,spi-mode = <3>;
synaptics,byte-delay-us = <0>;
synaptics,block-delay-us = <0>;
synaptics,power-delay-ms = <200>;
synaptics,reset-delay-ms = <200>;
synaptics,ubl-max-freq = <5000000>;
synaptics,ubl-byte-delay-us = <20>;
};

35
bindings/interconnect/qcom,cpucp-l3.txt Normal file
View File

@@ -0,0 +1,35 @@
Qualcomm Technologies, Inc. CPUCP L3 interconnect driver binding
-----------------------------------------------------------
The CPUCP L3 Interconnect provider supports the scaling of L3 cache
performance states of the CPU subsystem.
Required properties :
- compatible : shall contain only one of the following:
"qcom,holi-cpucp-l3-shared",
"qcom,holi-cpucp-l3-cpu";
- reg : Address and length of the register set for the device
- clock-names: should contain "xo", "alternate"
- clocks: list of phandle and clock specifier pairs corresponding to
entries in the clock-names property.
- #interconnect-cells : should contain 1
Examples:
cpucp_l3_shared: l3_shared@fd90000 {
reg = <0x0fd90000 0x3000>;
compatible = "qcom,holi-cpucp-l3-shared";
#interconnect-cells = <1>;
clock-names = "xo", "alternate";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPLL0>;
};
cpucp_l3_cpu: l3_cpu@fd90000{
reg = <0x0fd90000 0x3000>;
compatible = "qcom,holi-cpucp-l3-cpu";
#interconnect-cells = <1>;
clock-names = "xo", "alternate";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPLL0>;
};

9
bindings/interconnect/qcom,holi.txt
View File

@@ -6,7 +6,7 @@ Required properties :
"qcom,holi-bimc",
"qcom,holi-system_noc",
"qcom,holi-config_noc",
"qcom,holi-qup_virt",
"qcom,holi-clk_virt",
"qcom,holi-mmnrt_virt",
"qcom,holi-mmrt_virt",
- #interconnect-cells : should contain 1
@@ -15,6 +15,12 @@ reg : specifies the physical base address and size of registers
clocks : list of phandles and specifiers to all interconnect bus clocks
clock-names : clock names should include both "bus" and "bus_a"
The following are optional properties:
qcom,util-factor : Parameter that represents the DDR utilization factor
to be used in aggregation scheme. It is represented as
actual util-factor * 100.
Examples:
soc {
@@ -22,6 +28,7 @@ soc {
system_noc: interconnect@1880000 {
reg = <0x1880000 0x5f080>;
compatible = "qcom,holi-system_noc";
qcom,util-factor = <142>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,

23
bindings/interconnect/qcom,sdxlemur.txt Normal file
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@@ -0,0 +1,23 @@
Qualcomm Technologies, Inc. SDXLEMUR Network-On-Chip interconnect driver binding
--------------------------------------------------------------------------------
SDXLEMUR interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
Required properties :
- compatible : shall contain only one of the following:
"qcom,sdxlemur-system_noc",
"qcom,sdxlemur-mem_noc",
"qcom,sdxlemur-mc_virt",
- #interconnect-cells : should contain 1
Examples:
system_noc: interconnect@1620000 {
compatible = "qcom,sdxlemur-system_noc";
interconnect-cells = <1>;
};

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QTI MPM interrupt controller
MPM (MSM sleep Power Manager) is QTI's platform parent
interrupt controller. It manages subsystem wakeups and
resources during sleep. This driver marks the wakeup
interrupts in APSS such that it monitors the interrupts
when the system is asleep, wakes up the APSS when one
of these interrupts occur and replays it to the subsystem
interrupt controller after it becomes operational.
Platform interrupt controller MPM is next in hierarchy,
followed by others.
This defines 2 interrupt controllers to monitor the
interrupts when system is asleep:
One to monitor the wakeup capable gic interrupts called
wakegic.
Properties:
- compatible:
Usage: required
Value type: <string>
Definition: Should contain "qcom,mpm-gic" and the respective
target compatible flag from below ones.
"qcom,mpm-gic-holi"
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the IRQ used by remote processor to
wakeup APSS.
- interrupt-parent:
Usage: required
Value type: <phandle>
Definition: Specifies the interrupt parent necessary for
hierarchical domain to operate.
- interrupt-controller:
Usage: required
Value type: <bool>
Definition: Identifies the node as an interrupt controller.
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: Specifies the base physical address to trigger an
interrupt into remote processor.
-reg-names:
Usage: required
Value type: <string>, <string>
Definition: Specifies the address field names.
- qcom,num-mpm-irqs:
Usage: optional
Value type: <value>
Defination: Specifies the number of interrupts supported.
Example:
wakegic: wake-gic@7781b8 {
compatible = "qcom,mpm", "qcom,mpm-gic-holi";
interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
reg = <0x601d4 0x1000>,
<0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */
reg-names = "vmpm", "ipc";
interrupt-controller;
interrupt-parent = <&intc>;
#interrupt-cells = <3>;
};

7
bindings/iommu/arm,smmu.txt
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@@ -128,6 +128,13 @@ conditions.
retention. No cache invalidation operations involving asid
may be used.
- qcom,split-tables:
Some hardware configurations can easily use a model where
the I/O virtual address space for a domain can be split into
two symmetric portions, and clients can manage each portion.
Set for hardware that supports this model, and requires
this feature.
- qcom,actlr:
An array of <sid mask actlr-setting>.
Any sid X for which X&~mask==sid will be programmed with the

23
bindings/iommu/iommu-debug-test.yaml
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@@ -18,14 +18,16 @@ properties:
items:
- const: iommu-debug-test
iommus:
minItems: 1
items:
- description: IOMMU specifier with a SID and an SMR mask
description:
The SID in the IOMMU specifier is a placeholder so that the SMMU driver
can recognize the node. Our test uses ATOS, which doesn't use SIDs anyway,
so using a dummy value is ok.
child nodes:
compatible: : iommu-debug-usecase
iommus:
minItems: 1
items:
- description: IOMMU specifier with a SID and an SMR mask
description:
The SID in the IOMMU specifier is a placeholder so that the SMMU driver
can recognize the node. Our test uses ATOS, which doesn't use SIDs anyway,
so using a dummy value is ok.
required:
- compatible
@@ -35,5 +37,8 @@ examples:
- |
iommu_test_device {
compatible = "iommu-debug-test";
iommus = <&cpp_fd_smmu 42>;
basic_usecase {
compatible = "iommu-debug-usecase";
iommus = <&cpp_fd_smmu 42>;
}
};

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Bindings for Qualcomm Technologies, Inc. WLED driver
WLED (White Light Emitting Diode) driver is used for controlling display
backlight that is part of PMIC on Qualcomm Technologies, Inc. reference
platforms. The PMIC is connected to the host processor via SPMI bus.
- compatible
Usage: required
Value type: <string>
Definition: should be one of the below.
"qcom,pmi8998-spmi-wled",
"qcom,pm8150l-spmi-wled",
"qcom,pm6150l-spmi-wled"
"qcom,pm660l-spmi-wled"
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: Base address and size of the WLED modules.
- reg-names
Usage: required
Value type: <string>
Definition: Names associated with base addresses. should be
"wled-ctrl-base", "wled-sink-base".
- interrupts
Usage: optional
Value type: <prop encoded array>
Definition: Interrupts associated with WLED. Interrupts can be
specified as per the encoding listed under
Documentation/devicetree/bindings/spmi/
qcom,spmi-pmic-arb.txt.
- interrupt-names
Usage: optional
Value type: <string>
Definition: Interrupt names associated with the interrupts.
Currently supported interrupts are "sc-irq", "ovp-irq",
"pre-flash-irq" and "flash-irq". Pre_flash and flash
interrupts can be specified only for PMICs that has WLED5.
- label
Usage: required
Value type: <string>
Definition: The name of the backlight device.
- default-brightness
Usage: optional
Value type: <u32>
Definition: Brightness value on boot. Default is 2048.
Range of values are:
For pmi8998, it is 0-4095.
For pm8150l, this can vary from 0-4095 or 0-32767 depending
on the brightness control mode. If CABC is enabled, 0-4095
range is used.
- max-brightness
Usage: optional
Value type: <u32>
Definition: Maximum brightness level. Allowed values are:
For pmi8998, it is 4095.
For pm8150l, this can be either 4095 or 32767.
If CABC is enabled, this is capped to 4095.
- qcom,fs-current-limit
Usage: optional
Value type: <u32>
Definition: per-string full scale current limit in uA. value from
0 to 30000 with 5000 uA resolution. Default: 25000 uA
- qcom,boost-current-limit
Usage: optional
Value type: <u32>
Definition: ILIM threshold in mA. values are 105, 280, 450, 620, 970,
1150, 1300, 1500. Default: 970 mA
- qcom,switching-freq
Usage: optional
Value type: <u32>
Definition: Switching frequency in KHz. values are
600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371,
1600, 1920, 2400, 3200, 4800, 9600.
Default: 800 KHz
- qcom,ovp
Usage: optional
Value type: <u32>
Definition: Over-voltage protection limit in mV. values are 31100,
29600, 19600, 18100.
Default: 29600 mV
- qcom,string-cfg
Usage: optional
Value type: <u32>
Definition: Bit mask of the WLED strings. Bit 0 to 3 indicates strings
0 to 3 respectively. WLED module has four strings of leds
numbered from 0 to 3. Each string of leds are operated
individually. Specify the strings using the bit mask. Any
combination of led strings can be used.
Default value is 15 (b1111).
- qcom,en-cabc
Usage: optional
Value type: <bool>
Definition: Specify if cabc (content adaptive backlight control) is
needed.
- qcom,ext-pfet-sc-pro-en
Usage: optional
Value type: <bool>
Definition: Specify if external PFET control for short circuit
protection is needed. This is not applicable for PM8150L.
- qcom,auto-calibration
Usage: optional
Value type: <bool>
Definition: Enables auto-calibration of the WLED sink configuration.
- qcom,modulator-sel
Usage: optional
Value type: <u32>
Definition: Selects the modulator used for brightness modulation.
Allowed values are:
0 - Modulator A
1 - Modulator B
If not specified, then modulator A will be used by default.
This property is applicable only to WLED5 peripheral.
- qcom,cabc-sel
Usage: optional
Value type: <u32>
Definition: Selects the CABC pin signal used for brightness modulation.
Allowed values are:
0 - CABC disabled
1 - CABC 1
2 - CABC 2
3 - External signal (e.g. LPG) is used for dimming
This property is applicable only to WLED5 peripheral.
- qcom,leds-per-string
Usage: optional
Value type: <u32>
Definition: If specified, can be used to calculate available current
during selfie flash operation. If not specified, available
current calculated is simply the configured threshold.
- io-channels
Usage: optional
Value type: <phandle-array>
Definition: IIO channel specifiers for each name in io-channel-names.
- io-channel-names
Usage: optional
Value type: <string-array>
Definition: Names of the IIO channels that are used by WLED.
For details about IIO bindings see:
Documentation/devicetree/bindings/iio/iio-bindings.txt
Following properties are for child subnodes that are needed for WLED preflash
(or torch), flash and switch. These child subnodes can be specified only for
PMICs that has WLED5 (e.g. PM8150L).
For wled_torch child subnode,
- label
Usage: required
Value type: <string>
Definition: Should be "torch".
- qcom,default-led-trigger
Usage: optional
Value type: <string>
Definition: Name for LED trigger. If unspecified, "wled_torch" is used.
- qcom,wled-torch-fsc
Usage: optional
Value type: <u32>
Definition: WLED torch full scale current in mA. This configures the
maximum current allowed for torch device. Allowed values
are from 5 to 60 mA with a step of 5 mA. If not specified,
default value is set to 30 mA.
- qcom,wled-torch-step
Usage: optional
Value type: <u32>
Definition: WLED torch step delay in us. This configures the step delay
when the output is ramped up to the desired target current.
Allowed values are from 50 to 400 us with a step of 50 us.
If not specified, default value is set to 200 us.
- qcom,wled-torch-timer
Usage: optional
Value type: <u32>
Definition: WLED torch safety timer in ms. This configures the safety
timer to turn off torch automatically after timer expiry.
Allowed values are: 50, 100, 200, 400, 600, 800, 1000 and
1200. If not specified, default value is set to 1200 ms.
For wled_flash child subnode,
- label
Usage: required
Value type: <string>
Definition: Should be "flash".
- qcom,default-led-trigger
Usage: optional
Value type: <string>
Definition: Name for LED trigger. If unspecified, "wled_flash" is used.
- qcom,wled-flash-fsc
Usage: optional
Value type: <u32>
Definition: WLED flash full scale current in mA. This configures the
maximum current allowed for flash device. Allowed values
are from 5 to 60 mA with a step of 5 mA. If not specified,
default value is set to 40 mA.
- qcom,wled-flash-step
Usage: optional
Value type: <u32>
Definition: WLED flash step delay in us. This configures the step delay
when the output is ramped up to the desired target current.
Allowed values are from 50 to 400 us with a step of 50 us.
If not specified, default value is set to 200 us.
- qcom,wled-flash-timer
Usage: optional
Value type: <u32>
Definition: WLED flash safety timer in ms. This configures the safety
timer to turn off flash automatically after timer expiry.
Allowed values are: 50, 100, 200, 400, 600, 800, 1000 and
1200. If not specified, default value is set to 100 ms.
For wled_switch child subnode,
- label
Usage: required
Value type: <string>
Definition: Should be "switch".
- qcom,default-led-trigger
Usage: optional
Value type: <string>
Definition: Name for LED trigger. If unspecified, "wled_switch" is
used.
Example:
qcom-wled@d800 {
compatible = "qcom,pmi8998-spmi-wled";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xd800 0xd900>;
reg-names = "wled-ctrl-base", "wled-sink-base";
label = "backlight";
interrupts = <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "sc-irq", "ovp-irq";
qcom,fs-current-limit = <25000>;
qcom,boost-current-limit = <970>;
qcom,switching-freq = <800>;
qcom,ovp = <29600>;
qcom,string-cfg = <15>;
};
qcom-wled@d800 {
compatible = "qcom,pm8150l-spmi-wled";
#address-cells = <2>;
#size-cells = <0>;
reg = <0xd800 0x100>, <0xd900 0x100>;
reg-names = "wled-ctrl-base", "wled-sink-base";
label = "backlight";
interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp-irq";
qcom,string-cfg = <7>;
io-channels = <&pm7250b_qg PSY_IIO_RESISTANCE>,
<&pm7250b_qg PSY_IIO_VOLTAGE_OCV>,
<&pm7250b_qg PSY_IIO_CURRENT_NOW>;
io-channel-names = "rbatt",
"voltage_ocv",
"current_now";
wled_torch: qcom,wled-torch {
label = "torch";
qcom,wled-torch-fsc = <40>;
qcom,wled-torch-step = <300>;
qcom,wled-torch-timer = <600>;
};
wled_flash: qcom,wled-flash {
label = "flash";
qcom,wled-flash-fsc = <60>;
qcom,wled-flash-step = <100>;
qcom,wled-flash-timer = <200>;
};
wled_switch: qcom,wled-switch {
label = "switch";
};
};
qcom,leds@d800 {
compatible = "qcom,pm660l-spmi-wled";
reg = <0xd800 0x100>,
<0xd900 0x100>;
reg-names = "qpnp-wled-ctrl-base",
"qpnp-wled-sink-base";
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp-irq";
linux,name = "wled";
linux,default-led-trigger = "bkl-trigger";
};

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Qualcomm Technologies Inc. PNP v2 Flash LED
QPNP (Qualcomm Technologies Inc. Plug N Play) Flash LED (Light
Emitting Diode) driver v2 is used to provide illumination to
camera sensor when background light is dim to capture good
picture. It can also be used for flashlight/torch application.
It is part of PMIC on Qualcomm Technologies Inc. reference platforms.
Main node:
Required properties:
- compatible : one of "qcom,pm6150l-flash-led-v2"
"qcom,pmi632-flash-led-v2"
- reg : Base address and size for flash LED modules
Optional properties:
- interrupts : Specifies the interrupts associated with flash-led.
- interrupt-names : Specify the interrupt names associated with interrupts.
- qcom,hdrm-auto-mode : Boolean type to select headroom auto mode enabled or not
- qcom,isc-delay-us : Integer type to specify short circuit delay. Valid values are 32, 64,
128, 192. Unit is uS.
- qcom,warmup-delay-us : Integer type to specify warm up delay. Valid values are 32, 64,
128, 192. Unit is uS.
- qcom,short-circuit-det : Boolean property which enables short circuit fault detection.
- qcom,open-circuit-det : Boolean property which enables open circuit fault detection.
- qcom,vph-droop-det : Boolean property which enables VPH droop detection.
- qcom,vph-droop-hysteresis-mv : Integer property to specify VPH droop hysteresis. It is only used if
qcom,vph-droop-det is specified. Valid values are 0, 25, 50 and 75.
Unit is mV.
- qcom,vph-droop-threshold-mv : Integer property to specify VPH droop threshold. It is only used if
qcom,vph-droop-det is specified. Valid values are
2500 to 3200 with step size of 100. Unit is mV.
- qcom,vph-droop-debounce-us : Integer property to specify VPH droop debounce time. It is only used
if qcom,vph-droop-det is specified. Valid values are 0, 8, 16 and 26.
Unit is uS.
- qcom,led1n2-iclamp-low-ma : Integer property to specify current clamp low
level for mitigation. Unit is mA. Allowed
values are same as under qcom,max-current.
- qcom,led1n2-iclamp-mid-ma : Integer property to specify current clamp mid
level for mitigation. Unit is mA. Allowed
values are same as under qcom,max-current.
- qcom,led3-iclamp-low-ma : Integer property to specify current clamp low
level for mitigation. Unit is mA. Allowed
values are same as under qcom,max-current.
- qcom,led3-iclamp-mid-ma : Integer property to specify current clamp mid
level for mitigation. Unit is mA. Allowed
values are same as under qcom,max-current.
- qcom,vled-max-uv : Integer property for flash current predictive mitigation.
Default value is 3500000 uV.
- qcom,ibatt-ocp-threshold-ua : Integer property for flash current predictive mitigation.
Default value is 4500000 uA.
- qcom,rparasitic-uohm : Integer property for flash current predictive mitigation indicating
parasitic component of battery resistance. Default value is 0 uOhm.
- qcom,lmh-ocv-threshold-uv : Required property for flash current preemptive LMH mitigation.
Default value is 3700000 uV.
- qcom,lmh-rbatt-threshold-uohm : Required property for flash current preemptive LMH mitigation.
Default value is 400000 uOhm.
- qcom,lmh-mitigation-sel : Optional property to configure flash current preemptive LMH mitigation.
Accepted values are:
0: MITIGATION_DISABLED
1: MITIGATION_BY_ILED_THRESHOLD
2: MITIGATION_BY_SW
Default value is 2.
- qcom,chgr-mitigation-sel : Optional property to configure flash current preemptive charger mitigation.
Accepted values are:
0: MITIGATION_DISABLED
1: MITIGATION_BY_ILED_THRESHOLD
2: MITIGATION_BY_SW
Default value is 2.
- qcom,lmh-level : Optional property to configure flash current preemptive LMH mitigation.
Accepted values are 0, 1, and 3. Default value is 0.
- qcom,iled-thrsh-ma : Optional property to configure the led current threshold at which HW
preemptive mitigation is triggered. Unit is mA. Default value is 1000.
Accepted values are in the range 0 - 3100, with steps of 100.
0 disables autonomous HW mitigation.
- qcom,thermal-derate-en : Boolean property to enable flash current thermal mitigation.
- qcom,thermal-derate-current : Array of currrent limits for thermal mitigation. Required if
qcom,thermal-derate-en is specified. Unit is mA. Format is
qcom,thermal-derate-current = <OTST1_LIMIT, OTST2_LIMIT, OTST3_LIMIT>.
- qcom,otst-ramp-back-up-dis : Boolean property to disable current ramp
backup after thermal derate trigger is
deasserted.
- qcom,thermal-derate-slow : Integer property to specify slow ramping
down thermal rate. Unit is in uS. Allowed
values are: 128, 256, 512, 1024, 2048, 4096,
8192 and 314592.
- qcom,thermal-derate-fast : Integer property to specify fast ramping
down thermal rate. Unit is in uS. Allowed
values are: 32, 64, 96, 128, 256, 384 and
512.
- qcom,thermal-debounce : Integer property to specify thermal debounce
time. It is only used if qcom,thermal-derate-en
is specified. Unit is in uS. Allowed values
are: 0, 16, 32, 64.
- qcom,thermal-hysteresis : Integer property to specify thermal derating
hysteresis. Unit is in deciDegC. It is only
used if qcom,thermal-derate-en is specified.
Allowed values are:
0, 15, 30, 45 for pmi8998.
0, 20, 40, 60 for pm660l.
- qcom,thermal-thrsh1 : Integer property to specify OTST1 threshold
for thermal mitigation. Unit is in Celsius.
Accepted values are:
85, 79, 73, 67, 109, 103, 97, 91.
- qcom,thermal-thrsh2 : Integer property to specify OTST2 threshold
for thermal mitigation. Unit is in Celsius.
Accepted values are:
110, 104, 98, 92, 134, 128, 122, 116.
- qcom,thermal-thrsh3 : Integer property to specify OTST3 threshold
for thermal mitigation. Unit is in Celsius.
Accepted values are:
125, 119, 113, 107, 149, 143, 137, 131.
- qcom,hw-strobe-option : Integer type to specify hardware strobe option. Based on the specified
value, additional GPIO configuration may be required to provide strobing
support. Supported values are:
0: Flash strobe is used for LED1, LED2, LED3
1: Flash strobe is used for LED1, LED2 and GPIO10 is used for LED3
2: Flash strobe is used for LED1; GPIO9 is used for LED2; GPIO10 is used for LED3
For PM8150L/A and its derivatives, supported values are:
0: Flash strobe is used for LED1, LED2, LED3
1: Flash strobe is used for LED1, LED2 and GPIO12 is used for LED3
- switchX-supply : phandle of the regulator that needs to be used
as a supply for flash switch_X device.
- qcom,bst-pwm-ovrhd-uv : Charger flash VPH overhead. Applicable for PMI632 only.
Supported values (in mV) are: 300, 400, 500, 600. Default is 300.
Child node: Contains settings for each individual LED. Each LED channel needs a flash node and
torch node for itself, and an individual switch node to serve as an overall switch.
Required Properties:
- label : Type of led that will be used, either "flash", "torch", or "switch.
- qcom,led-name : Name of the LED.
- qcom,default-led-trigger : Trigger for the camera flash and torch. Accepted values are
"flash0_trigger", "flash1_trigger", "flash2_trigger, "torch0_trigger",
"torch1_trigger", "torch2_trigger", and "switch_trigger".
- qcom,id : ID for each physical LED equipped. In order to handle situation when
only 1 or 2 LEDs are installed, flash and torch nodes on LED channel 0
should be specified with ID 0; nodes on channel 1 be ID 1, etc. This is
not required for switch node.
- qcom,max-current : Maximum current allowed on this LED. Valid values should be
integer from 0 to 1500 inclusive. Flash 2 should have maximum current of
750 per hardware requirement. Unit is mA. For torch, the maximum current
is clamped at 500 mA. This is not required for the switch node.
- qcom,duration-ms : Required property for flash nodes but not needed for torch. Integer
type specifying flash duration. Values are from 10ms to 1280ms with
10ms resolution. This is not required for switch node.
- qcom,led-mask : Required property for switch nodes. Bitmask to indicate which leds are
controlled by this switch node. Accepted values are in the range 1 to 7,
inclusive. Example:
qcom,led-mask = <4>; /* This switch node controls the flash2/torch2 led. */
Optional properties:
- qcom,current-ma : operational current intensity for LED in mA. Accepted values are a
positive integer in the range of 0 to qcom,max-current inclusive.
- qcom,ires-ua : Integer type to specify current resolution. Accepted values should be
12500, 10000, 7500, and 5000. Unit is uA.
- qcom,hdrm-voltage-mv : Integer type specifying headroom voltage. Values are from 125mV to 500mV
with 25mV resolution. Default setting is 325mV
- qcom,hdrm-vol-hi-lo-win-mv : Integer type to specify headroom voltage swing range. Values are
from 0mV to 375mV with 25mV resolution. Default setting is 100mV.
- pinctrl-names : Name of the pinctrl configuration that will be used when external GPIOs
are used for enabling/disabling, HW strobing of flash LEDs. For more
information on using pinctrl, please refer
Documentation/devicetree/bindings/pinctrl/msm-pinctrl.txt
Following are the pinctrl configs that can be specified:
"led_enable" : pinctrl config to enable led. This should specify the active
configuration defined for each pin or pin group.
"led_disable" : pinctrl config to disable led. This should specify the sleep
configuration defined for each pin or pin group.
"strobe_enable" : pinctrl config to enable hw-strobe. This should specify the
active configuration defined for each pin or pin group.
"strobe_disable" : pinctrl config to disable hw-strobe. This should specify the
sleep configuration defined for each pin or pin group.
- qcom,hw-strobe-gpio : phandle to specify GPIO for hardware strobing. This is used when there is no
pinctrl support or PMIC GPIOs are used.
- qcom,strobe-sel : Property to select strobe type. If not defined,
software strobe will be used. Allowed options are:
0 - SW strobe
1 - HW strobe
2 - LPG strobe
LPG strobe is supported only for LED3.
If LPG strobe is specified, then strobe control is
configured for active high and level triggered. Also
qcom,hw-strobe-option should be set to 1 or 2.
- qcom,hw-strobe-edge-trigger : Boolean property to select trigger type. If defined, hw-strobe is set to
be edge triggered. Otherwise, it is level triggered.
- qcom,hw-strobe-active-low : Boolean property to select strobe signal polarity. If defined, hw-strobe
signal polarity is set to active-low, else it is active-high.
- qcom,symmetry-en : Boolean property to specify if the flash LEDs under a
switch node are controlled symmetrically. This needs
to be specified if a group of flash LED channels are
connected to a single LED.
Example:
qcom,leds@d300 {
compatible = "qcom,pm6150l-flash-led-v2";
status = "okay";
reg = <0xd300 0x100>;
label = "flash";
interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x3 0xd3 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x3 0xd3 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x3 0xd3 0x3 IRQ_TYPE_EDGE_BOTH>,
<0x3 0xd3 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x3 0xd3 0x5 IRQ_TYPE_EDGE_BOTH>,
<0x3 0xd3 0x6 IRQ_TYPE_EDGE_BOTH>,
<0x3 0xd3 0x7 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "led-fault-irq",
"mitigation-irq",
"flash-timer-exp-irq",
"all-ramp-down-done-irq",
"all-ramp-up-done-irq",
"led3-ramp-up-done-irq",
"led2-ramp-up-done-irq",
"led1-ramp-up-done-irq";
qcom,hdrm-auto-mode;
qcom,isc-delay = <192>;
switch0-supply = <&pmi8998_bob>;
pmi8998_flash0: qcom,flash_0 {
label = "flash";
qcom,led-name = "led:flash_0";
qcom,max-current = <1500>;
qcom,default-led-trigger =
"flash0_trigger";
qcom,id = <0>;
qcom,current-ma = <1000>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <325>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
pmi8998_flash1: qcom,flash_1 {
label = "flash";
qcom,led-name = "led:flash_1";
qcom,max-current = <1500>;
qcom,default-led-trigger =
"flash1_trigger";
qcom,id = <1>;
qcom,current-ma = <1000>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <325>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
pmi8998_flash2: qcom,flash_2 {
label = "flash";
qcom,led-name = "led:flash_2";
qcom,max-current = <750>;
qcom,default-led-trigger =
"flash2_trigger";
qcom,id = <2>;
qcom,current-ma = <500>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <325>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
pinctrl-names = "led_enable","led_disable";
pinctrl-0 = <&led_enable>;
pinctrl-1 = <&led_disable>;
};
pmi8998_torch0: qcom,torch_0 {
label = "torch";
qcom,led-name = "led:torch_0";
qcom,max-current = <500>;
qcom,default-led-trigger =
"torch0_trigger";
qcom,id = <0>;
qcom,current-ma = <300>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <325>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
pmi8998_torch1: qcom,torch_1 {
label = "torch";
qcom,led-name = "led:torch_1";
qcom,max-current = <500>;
qcom,default-led-trigger =
"torch1_trigger";
qcom,id = <1>;
qcom,current-ma = <300>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <325>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
pmi8998_torch2: qcom,torch_2 {
label = "torch";
qcom,led-name = "led:torch_2";
qcom,max-current = <500>;
qcom,default-led-trigger =
"torch2_trigger";
qcom,id = <2>;
qcom,current-ma = <300>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <325>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
pinctrl-names = "led_enable","led_disable";
pinctrl-0 = <&led_enable>;
pinctrl-1 = <&led_disable>;
};
pmi8998_switch0: qcom,led_switch_0 {
label = "switch";
qcom,led-name = "led:switch_0";
qcom,led-mask = <3>;
qcom,default-led-trigger =
"switch0_trigger";
qcom,symmetry-en;
};
pmi8998_switch1: qcom,led_switch_1 {
label = "switch";
qcom,led-name = "led:switch_1";
qcom,led-mask = <4>;
qcom,default-led-trigger =
"switch1_trigger";
};
};

1
bindings/media/msm-cvp.txt
View File

@@ -6,6 +6,7 @@ cvp
Required properties:
- compatible : one of:
- "qcom,msm-cvp"
- "qcom,shima-cvp" : Invokes driver specific data for shima.
- "qcom,lahaina-cvp" : Invokes driver specific data for Lahaina.
- "qcom,kona-cvp" : Invokes driver specific data for kona.

237
bindings/media/video/msm-sde-rotator.txt Normal file
View File

@@ -0,0 +1,237 @@
SDE Rotator
SDE rotator is a v4l2 rotator driver, which manages the rotator hw
block inside the Snapdragon Display Engine (or Mobile Display Subsystem)
Required properties
- compatible: Must be "qcom,sde-rotator".
- reg: offset and length of the register set for the device.
- reg-names: names to refer to register sets related to this device
- interrupt-parent: phandle for the interrupt controller that
services interrupts for this device.
- interrupts: Interrupt associated with rotator.
- <name>-supply: Phandle for <name> regulator device node.
- qcom,supply-names: names to refer to regulator device node.
- clocks: List of Phandles for clock device nodes
needed by the device.
- clock-names: List of clock names needed by the device.
- #list-cells: Number of rotator cells, must be 1
Bus Scaling Data:
- qcom,msm-bus,name: String property describing rotator client.
- qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases
defined in the vectors property. This must be
set to <3> for rotator driver where use-case 0 is
used to take off rotator BW votes from the system.
And use-case 1 & 2 are used in ping-pong fashion
to generate run-time BW requests.
- qcom,msm-bus,num-paths: This represents the number of paths in each
Bus Scaling Usecase. This value depends on
how many number of AXI master ports are
dedicated to rotator for particular chipset.
- qcom,msm-bus,vectors-KBps: * A series of 4 cell properties, with a format
of (src, dst, ab, ib) which is defined at
Documentation/devicetree/bindings/arm/msm/msm_bus.txt
* Current values of src & dst are defined at
include/linux/msm-bus-board.h
src values allowed for rotator are:
25 = MSM_BUS_MASTER_ROTATOR
dst values allowed for rotator are:
512 = MSM_BUS_SLAVE_EBI_CH0
ab: Represents aggregated bandwidth.
ib: Represents instantaneous bandwidth.
* Total number of 4 cell properties will be
(number of use-cases * number of paths).
* These values will be overridden by the driver
based on the run-time requirements. So initial
ab and ib values defined here are random and
bare no logic except for the use-case 0 where ab
and ib values needs to be 0.
* Define realtime vector properties followed by
non-realtime vector properties.
Optional properties
- qcom,rot-vbif-settings: Array with key-value pairs of constant VBIF register
settings used to setup MDSS QoS for optimum performance.
The key used should be offset from "rot_vbif_phys" register
defined in reg property.
- qcom,mdss-rot-block-size: This integer value indicates the size of a memory block
(in pixels) to be used by the rotator. If this property
is not specified, then a default value of 128 pixels
would be used.
- qcom,mdss-highest-bank-bit: This integer value indicate tile format as opposed to usual
linear format. The value tells the GPU highest memory
bank bit used.
- qcom,mdss-default-ot-wr-limit: This integer value indicates maximum number of pending
writes that can be allowed on each WR xin.
This value can be used to reduce the pending writes
limit and can be tuned to match performance
requirements depending upon system state.
Some platforms require a dynamic ot limiting in
some cases. Setting this default ot write limit
will enable this dynamic limiting for the write
operations in the platforms that require these
limits.
- qcom,mdss-default-ot-rd-limit: This integer value indicates the default number of pending
reads that can be allowed on each RD xin.
Some platforms require a dynamic ot limiting in
some cases. Setting this default ot read limit
will enable this dynamic limiting for the read
operations in the platforms that require these
limits.
- qcom,mdss-rot-vbif-qos-setting: This array is used to program vbif qos remapper register
priority for rotator clients.
- qcom,mdss-rot-vbif-memtype: Array of u32 vbif memory type settings for each xin port.
- qcom,mdss-rot-cdp-setting: Integer array of size two, to indicate client driven
prefetch is available or not. Index 0 represents
if CDP is enabled for read and index 1, if CDP
is enabled for write operation.
- qcom,mdss-rot-qos-lut A 4 cell property with the format of <rd_lut_0,
rd_lut_1, wr_lut_0, wr_lut_1> indicating the qos
lut settings for the rotator sspp and writeback
client.
- qcom,mdss-rot-danger-lut A two cell property with the format of <rd_lut,
wr_lut> indicating the danger lut settings for
the rotator sspp and writeback client.
- qcom,mdss-rot-safe-lut A two cell property with the format of <rd_lut,
wr_lut> indicating the safe lut settings for the
rotator sspp and writeback client.
- qcom,mdss-inline-rot-qos-lut: A 4 cell property with the format of <rd_lut_0,
rd_lut_1, wr_lut_0, wr_lut_1> indicating the qos
lut settings for the inline rotator sspp and
writeback client.
- qcom,mdss-inline-rot-danger-lut: A two cell property with the format of
<rd_lut, wr_lut> indicating the danger lut
settings for the inline rotator sspp and
writeback client.
- qcom,mdss-inline-rot-safe-lut: A two cell property with the format of
<rd_lut, wr_lut> indicating the safe lut
settings for the inline rotator sspp and
writeback client.
- qcom,mdss-rot-qos-cpu-mask: A u32 value indicating desired PM QoS CPU
affine mask.
- qcom,mdss-rot-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA
latency in usec.
- qcom,mdss-rot-mode: This is integer value indicates operation mode
of the rotator device
- qcom,mdss-sbuf-headroom: This integer value indicates stream buffer headroom in lines.
- qcom,mdss-rot-linewidth: This integer value indicates rotator line width supported in pixels.
- cache-slice-names: A set of names that identify the usecase names of a client that uses
cache slice. These strings are used to look up the cache slice
entries by name.
- cache-slices: The tuple has phandle to llcc device as the first argument and the
second argument is the usecase id of the client.
- qcom,sde-ubwc-malsize: A u32 property to specify the default UBWC
minimum allowable length configuration value.
- qcom,sde-ubwc-swizzle: A u32 property to specify the default UBWC
swizzle configuration value.
- qcom,rot-reg-bus: Property to provide Bus scaling for register
access for rotator blocks.
- power-domains: A phandle to respective power domain node.
- qcom,mdss-rot-parent: A 2 cell property, with format of (mdp phandle,
instance id), of mdp device.
- qcom,mdss-rot-xin-id: An integer array of xin-ids when nrt path for rotation
is not available.
Subnode properties:
- compatible: Compatible name used in smmu v2.
smmu_v2 names should be:
"qcom,smmu_sde_rot_unsec"- smmu context bank device for
unsecure rotation domain.
"qcom,smmu_sde_rot_sec" - smmu context bank device for
secure rotation domain.
- iommus: specifies the SID's used by this context bank
- gdsc-mdss-supply: Phandle for mdss supply regulator device node.
- clocks: List of Phandles for clock device nodes
needed by the device.
- clock-names: List of clock names needed by the device.
Example:
mdss_rotator: qcom,mdss_rotator {
compatible = "qcom,sde_rotator";
reg = <0xfd900000 0x22100>,
<0xfd925000 0x1000>;
reg-names = "mdp_phys", "rot_vbif_phys";
#list-cells = <1>;
interrupt-parent = <&mdss_mdp>;
interrupts = <2 0>;
power-domains = <&mdss_mdp>;
qcom,mdss-mdp-reg-offset = <0x00001000>;
rot-vdd-supply = <&gdsc_mdss>;
qcom,supply-names = "rot-vdd";
clocks = <&clock_mmss clk_mmss_mdss_ahb_clk>,
<&clock_mmss clk_mmss_mdss_rot_clk>;
clock-names = "iface_clk", "rot_core_clk";
qcom,mdss-highest-bank-bit = <0x2>;
qcom,sde-ubwc-malsize = <0>;
qcom,sde-ubwc-swizzle = <1>;
/* Bus Scale Settings */
qcom,msm-bus,name = "mdss_rotator";
qcom,msm-bus,num-cases = <3>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<25 512 0 0>,
<25 512 0 6400000>,
<25 512 0 6400000>;
/* VBIF QoS remapper settings*/
qcom,mdss-rot-vbif-qos-setting = <1 1 1 1>;
qcom,mdss-rot-vbif-memtype = <3 3>;
com,mdss-rot-cdp-setting = <1 1>;
qcom,mdss-default-ot-rd-limit = <8>;
qcom,mdss-default-ot-wr-limit = <16>;
qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
qcom,mdss-rot-danger-lut = <0x0 0x0>;
qcom,mdss-rot-safe-lut = <0x0000ffff 0x0>;
qcom,mdss-rot-qos-cpu-mask = <0xf>;
qcom,mdss-rot-qos-cpu-dma-latency = <75>;
qcom,mdss-inline-rot-qos-lut = <0x0 0x0 0x00112233 0x44556677>;
qcom,mdss-inline-rot-danger-lut = <0x0 0x0000ffff>;
qcom,mdss-inline-rot-safe-lut = <0x0 0x0000ff00>;
qcom,mdss-sbuf-headroom = <20>;
cache-slice-names = "rotator";
cache-slices = <&llcc 4>;
rot_reg: qcom,rot-reg-bus {
qcom,msm-bus,name = "mdss_rot_reg";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,active-only;
qcom,msm-bus,vectors-KBps =
<1 590 0 0>,
<1 590 0 76800>;
};
smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
compatible = "qcom,smmu_sde_rot_unsec";
iommus = <&mdp_smmu 0xe00>;
gdsc-mdss-supply = <&gdsc_bimc_smmu>;
clocks = <&clock_mmss clk_bimc_smmu_ahb_clk>,
<&clock_mmss clk_bimc_smmu_axi_clk>;
clock-names = "rot_ahb_clk", "rot_axi_clk";
};
smmu_sde_rot_sec: qcom,smmu_sde_rot_sec_cb {
compatible = "qcom,smmu_sde_rot_sec";
iommus = <&mmss_smmu 0xe01>;
gdsc-mdss-supply = <&gdsc_bimc_smmu>;
clocks = <&clock_mmss clk_bimc_smmu_ahb_clk>,
<&clock_mmss clk_bimc_smmu_axi_clk>;
clock-names = "rot_ahb_clk", "rot_axi_clk";
};
};

3
bindings/media/video/msm-vidc.txt
View File

@@ -7,8 +7,11 @@ Required properties:
- compatible : one of:
- "qcom,msm-vidc"
- "qcom,lahaina-vidc" : Invokes driver-specific data for LAHAINA.
- "qcom,shima-vidc" : Invokes driver-specific data for SHIMA.
- "qcom,holi-vidc" : Invokes driver-specific data for HOLI.
Optional properties:
- vidc,firmware-name : Video Firmware ELF image name to be loaded by PIL
- reg : offset and length of the register set for the device.
- sku-index : sku version of the hardware.
- interrupts : should contain the vidc interrupt.

17
bindings/mmc/sdhci-msm.txt
View File

@@ -69,6 +69,20 @@ Optional Properties:
Please refer to Documentation/devicetree/bindings/
interconnect/ for more details.
- devfreq,freq-table - specifies supported frequencies for clock scaling.
Clock scaling logic shall toggle between these frequencies based
on card load. In case the defined frequencies are over or below
the supported card frequencies, they will be overridden
during card init. In case this entry is not supplied,
the driver will construct one based on the card
supported max and min frequencies.
The frequencies must be ordered from lowest to highest.
- scaling-lower-bus-speed-mode - Few hosts can support DDR52 mode at the
same lower system voltage corner as high-speed mode. In such
cases, it is always better to put it in DDR mode which will
improve the performance without any power impact.
Example:
sdhc_1: sdhci@f9824900 {
@@ -112,4 +126,7 @@ Example:
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
qcom,devfreq,freq-table = <50000000 200000000>;
qcom,scaling-lower-bus-speed-mode = "DDR52";
};

5
bindings/pci/pci-msm-msi.txt
View File

@@ -30,6 +30,11 @@ Main node
Value type: <prop-encoded-array>
Definition: Array of tuples which describe interrupt lines for PCIe MSI
-qcom,snps:
Usage: optional
Value type: <bool>
Definition: Set if interrupt controller is Synopsys instead of QGIC
=======
Example
=======

12
bindings/pci/pci-msm.txt
View File

@@ -69,12 +69,11 @@ Main node
Usage: required
Value type: <stringlist>
Definition: Should contain
- "int_msi"
- "int_global_int"
- "int_a"
- "int_b"
- "int_c"
- "int_d",
- "int_global_int"
- #interrupt-cells:
Usage: required
@@ -434,16 +433,15 @@ Example
interrupt-parent = <&pcie0>;
interrupts = <0 1 2 3 4 5>;
interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",
"int_global_int",
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d",
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
interrupt-map = <0 0 0 0 &intc 0 141 0
interrupt-map = <0 0 0 0 &intc 0 140 0
0 0 0 1 &intc 0 149 0
0 0 0 2 &intc 0 150 0
0 0 0 3 &intc 0 151 0
0 0 0 4 &intc 0 152 0
0 0 0 5 &intc 0 140 0>;
0 0 0 4 &intc 0 152 0>;
msi-parent = <&pcie0_msi>;
perst-gpio = <&tlmm 35 0>;

2
bindings/pinctrl/qcom,pmic-gpio.txt
View File

@@ -39,6 +39,7 @@ PMIC's from Qualcomm.
"qcom,pm6350-gpio"
"qcom,pm6150l-gpio"
"qcom,pm8450-gpio"
"qcom,pmx65-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
if the device is on an spmi bus or an ssbi bus respectively
@@ -130,6 +131,7 @@ to specify in a pin configuration subnode:
gpio1-gpio9 for pm6350
gpio1-gpio12 for pm6150l
gpio1-gpio4 for pm8450
gpio1-gpio16 for pmx65
- function:
Usage: required

199
bindings/pinctrl/qcom,sdxlemur-pinctrl.yaml Normal file
View File

@@ -0,0 +1,199 @@
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,sdxlemur-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SDXLEMUR TLMM block
maintainers:
- Jeevan Shriram <jshriram@quicinc.com>
description: |
This binding describes the Top Level Mode Multiplexer block found in the
SDXLEMUR platform.
properties:
compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,sdxlemur-pinctrl"
reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
#interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
#gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
wakeup-parent:
Usage: optional
Value type: <phandle>
Definition: A phandle to the wakeup interrupt controller for the SoC.
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode.
Valid pins:
gpio0-gpio149
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
sdc2_data sdc1_rclk
Supports bias and drive-strength
function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values:
blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
atest_usb20, atest_char0, dac_calib10, qdss_stm10,
qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
gpio
bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull up.
output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven high.
Not valid for sdc pins.
output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven low.
Not valid for sdc pins.
drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values: 2, 4, 6, 8, 10, 12, 14 and 16
examples:
- |
tlmm: pinctrl@f100000 {
compatible = "qcom,sdxlemur-pinctrl";
reg = <0x03000000 0xdc2000>;
interrupts = <0 208 0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
};

27
bindings/power/reset/qcom,dload-mode.yaml Normal file
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@@ -0,0 +1,27 @@
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,dload-mode.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Technologies, Inc. Download Mode binding
maintainers:
- Elliot Berman <eberman@quicinc.com>
description: |
The Download Mode driver is used to manage sending SoC into a dump collection
mode after a reboot.
properties:
compatible:
items:
- const: qcom,dload-mode
required:
- compatible
examples:
- |
qcom,dload-mode {
compatible = "qcom,dload-mode";
};

44
bindings/power/reset/qcom,reboot-reason.yaml Normal file
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%YAML 1.2
---
$id: "http://devicetree.org/schemas/power/reset/qcom-reboot-reason.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Technologies, Inc. reboot reason binding
maintainers:
- Elliot Berman <eberman@quicinc.com>
description: |
Qualcomm Technologies, Inc. SoCs support booting to special download
modes after a restart. These modes could be a normal restart,
restarting into a ramdump collection mode (CrashDump), or restarting
into "emergency download mode".
properties:
compatible:
items:
- const: qcom,reboot-mode
allOf:
- $ref: /schemas/nvmem/nvmem-consumer.yaml#/properties
- items:
nvmem-cell-names:
items:
- const: restart_reason
required:
- compatible
- nvmem-cells-names
dependencies:
allOf:
- $ref: /schemas/nvmem/nvmem-consumer.yaml#/dependencies
examples:
- |
reboot-reason {
compatible = "qcom,reboot-reason";
nvmem-cells = <&restart_reason>;
nvmem-cell-names = "restart_reason";
};

7
bindings/power/supply/qcom,battery-charger.txt
View File

@@ -22,6 +22,12 @@ information on "qcom,pmic_glink" device which is used in the example below.
way that the next element is always less than or equal to
the current element (descending order).
- qcom,wireless-fw-name:
Usage: optional
Value type: <string>
Definition: Firmware name that needs to be used for updating wireless
charger firmware.
= EXAMPLE
&soc {
@@ -31,6 +37,7 @@ information on "qcom,pmic_glink" device which is used in the example below.
compatible = "qcom,battery-charger";
qcom,thermal-mitigation =
<3000000 1500000 1000000 500000>;
qcom,wireless-fw-name = "idt9412.bin";
};
...
};

517
bindings/power/supply/qcom/qpnp-qg.txt Normal file
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@@ -0,0 +1,517 @@
Qualcomm Technologies, Inc. QPNP PMIC QGAUGE (QG) Device
QPNP PMIC QGAUGE device provides the ability to gauge the State-of-Charge
of the battery. It provides an interface to the clients to read various
battery related parameters.
=======================
Required Node Structure
=======================
Qgauge device must be described in two level of nodes. The first level
describes the properties of the Qgauge device and the second level
describes the peripherals managed/used of the module.
====================================
First Level Node - QGAUGE device
====================================
- compatible
Usage: required
Value type: <string>
Definition: Should be "qcom,qpnp-qg-lite" for PM2250.
Should be "qcom,pm6150-qg" for PM6150.
Should be "qcom,pmi632-qg" for PMI632.
Should be "qcom,pm7250b-qg" for PM7250B.
- io-channels
Usage: required
Value type: <phandle-array>
Definition: IIO channel specifiers for each name in io-channel-names.
- io-channel-names
Usage: required
Value type: <string-array>
Definition: Names of the IIO channels that are used by QG device.
- qcom,qg-vadc
Usage: required
Value type: <phandle>
Definition: Phandle for the VADC node, it is used for BATT_ID and
BATT_THERM readings.
- qcom,vbatt-empty-mv
Usage: optional
Value type: <u32>
Definition: The battery voltage threshold (in mV) at which the
vbatt-empty interrupt fires. The SOC is forced to 0
when this interrupt fires. If not specified, the
default value is 3200 mV.
- qcom,vbatt-empty-cold-mv
Usage: optional
Value type: <u32>
Definition: The battery voltage threshold (in mV) at which the
vbatt-empty interrupt fires. This threshold is only
applied at cold temperature specified by
'qcom,cold-temp-threshold'. The SOC is forced to 0
when this interrupt fires. If not specified, the
default value is 3000 mV.
- qcom,vbatt-cutoff-mv
Usage: optional
Value type: <u32>
Definition: The battery voltage threshold (in mV) at which the
the Qgauge algorithm converges to 0 SOC. If not specified
the default value is 3400 mV.
- qcom,vbatt-low-mv
Usage: optional
Value type: <u32>
Definition: The battery voltage threshold (in mV) at which the
the VBAT_LOW interrupt fires. Software can take necessary
the action when this interrupt fires. If not specified
the default value is 3500 mV.
- qcom,vbatt-low-cold-mv
Usage: optional
Value type: <u32>
Definition: The battery voltage threshold (in mV) at which the
the VBAT_LOW interrupt fires. The threshold is only
applied at cold temperature specified by
'qcom,cold-temp-threshold'. Software can take necessary
the action when this interrupt fires. If not specified
the default value is 3800 mV.
- qcom,qg-iterm-ma
Usage: optional
Value type: <u32>
Definition: The battery current (in mA) at which the the QG algorithm
converges the SOC to 100% during charging and can be used to
terminate charging. If not specified, the default value is
100mA.
- qcom,delta-soc
Usage: optional
Value type: <u32>
Definition: The SOC percentage increase at which the SOC is
periodically reported to the userspace. If not specified,
the value defaults to 1%.
- qcom,s2-fifo-length
Usage: optional
Value type: <u32>
Definition: The total number if FIFO samples which need to be filled up
in S2 state of QG to fire the FIFO DONE interrupt.
Minimum value = 1 Maximum Value = 8. If not specified,
the default value is 5.
- qcom,s2-acc-length
Usage: optional
Value type: <u32>
Definition: The number of distinct V & I samples to be accumulated
in each FIFO in the S2 state of QG.
Minimum Value = 0 Maximum Value = 256. If not specified,
the default value is 128.
- qcom,s2-acc-interval-ms
Usage: optional
Value type: <u32>
Definition: The time (in ms) between each of the V & I samples being
accumulated in FIFO.
Minimum Value = 0 ms Maximum Value = 2550 ms. If not
specified the default value is 100 ms.
- qcom,ocv-timer-expiry-min
Usage: optional
Value type: <u32>
Definition: The maximum time (in minutes) for the QG to transition from
S3 to S2 state.
Minimum Value = 2 min Maximum Value = 30 min. If not
specified the hardware default is set to 14 min.
- qcom,ocv-tol-threshold-uv
Usage: optional
Value type: <u32>
Definition: The OCV detection error tolerance (in uV). The maximum
voltage allowed between 2 VBATT readings in the S3 state
to qualify for a valid OCV.
Minimum Value = 0 uV Maximum Value = 12262 uV Step = 195 uV
- qcom,s3-entry-fifo-length
Usage: optional
Value type: <u32>
Definition: The minimum number if FIFO samples which have to qualify the
S3 IBAT entry threshold (qcom,s3-entry-ibat-ua) for QG
to enter into S3 state.
Minimum Value = 1 Maximum Value = 8. The hardware default
is configured to 3.
- qcom,s3-entry-ibat-ua
Usage: optional
Value type: <u32>
Definition: The battery current (in uA) for the QG to enter into the S3
state. The QG algorithm enters into S3 if the battery
current is lower than this threshold consecutive for
the FIFO length specified in 'qcom,s3-entry-fifo-length'.
Minimum Value = 0 uA Maximum Value = 155550 uA
Step = 610 uA.
- qcom,s3-exit-ibat-ua
Usage: optional
Value type: <u32>
Definition: The battery current (in uA) for the QG to exit S3 state.
If the battery current is higher than this threshold QG
exists S3 state.
Minimum Value = 0 uA Maximum Value = 155550 uA
Step = 610 uA.
- qcom,rbat-conn-mohm
Usage: optional
Value type: <u32>
Definition: Resistance of the battery connectors in mOhms.
- qcom,ignore-shutdown-soc-secs
Usage: optional
Value type: <u32>
Definition: Time in seconds beyond which shutdown SOC is ignored.
If not specified the default value is 360 secs.
- qcom,hold-soc-while-full
Usage: optional
Value type: <empty>
Definition: A boolean property that when defined holds SOC at 100% when
the battery is full until recharge starts.
- qcom,linearize-soc
Usage: optional
Value type: <empty>
Definition: A boolean property that when defined linearizes SOC when
the SOC drops after charge termination monotonically to
improve the user experience. This is applicable only if
"qcom,hold-soc-while-full" is specified.
- qcom,cold-temp-threshold
Usage: optional
Value type: <u32>
Definition: Temperature threshold in decidegree at which the low
temperature specific configuration as applied. If not
specified, the default value is 0 degree centigrade.
- qcom,cl-disable
Usage: optional
Value type: <empty>
Definition: A boolean property to disable the battery capacity
learning when charging.
- qcom,cl-feedback-on
Usage: optional
Value type: <empty>
Definition: A boolean property to feedback the learned capacity into
the capacity lerning algorithm. This has to be used only if the
property "qcom,cl-disable" is not specified.
- qcom,cl-max-start-soc
Usage: optional
Value type: <u32>
Definition: Battery SOC has to be below or equal to this value at the
start of a charge cycle to start the capacity learning.
If this is not specified, then the default value used
will be 15. Unit is in percentage.
- qcom,cl-min-start-soc
Usage: optional
Value type: <u32>
Definition: Battery SOC has to be above or equal to this value at the
start of a charge cycle to start the capacity learning.
If this is not specified, then the default value used
will be 10. Unit is in percentage.
- qcom,cl-min-temp
Usage: optional
Value type: <u32>
Definition: Lower limit of battery temperature to start the capacity
learning. If this is not specified, then the default value
used will be 150 (15 C). Unit is in decidegC.
- qcom,cl-max-temp
Usage: optional
Value type: <u32>
Definition: Upper limit of battery temperature to start the capacity
learning. If this is not specified, then the default value
used will be 500 (50 C). Unit is in decidegC.
- qcom,cl-max-increment
Usage: optional
Value type: <u32>
Definition: Maximum capacity increment allowed per capacity learning
cycle. If this is not specified, then the default value
used will be 5 (0.5%). Unit is in decipercentage.
- qcom,cl-max-decrement
Usage: optional
Value type: <u32>
Definition: Maximum capacity decrement allowed per capacity learning
cycle. If this is not specified, then the default value
used will be 100 (10%). Unit is in decipercentage.
- qcom,cl-min-limit
Usage: optional
Value type: <u32>
Definition: Minimum limit that the capacity cannot go below in a
capacity learning cycle. If this is not specified, then
the default value is 0. Unit is in decipercentage.
- qcom,cl-max-limit
Usage: optional
Value type: <u32>
Definition: Maximum limit that the capacity cannot go above in a
capacity learning cycle. If this is not specified, then
the default value is 0. Unit is in decipercentage.
- qcom,cl-min-delta-batt-soc
Usage: optional
Value type: <u32>
Definition: Minimum change in battery SOC to qualify for capacity
learning. If this is not specified, then the default
value is 10. Unit is in percentage.
- qcom,cl-wt-enable
Usage: optional
Value type: <bool>
Definition: A boolean property to enable weighted capacity learning
based on change in battery SOC during a charging cycle.
If this is specified, then "qcom,cl-min-start-soc" and
"qcom,cl-max-start-soc" is not used.
- qcom,esr-disable
Usage: optional
Value type: <bool>
Definition: Boolean property to disable ESR estimation. If not defined
ESR estimation stays enabled for charge-cycles.
- qcom,esr-discharge-enable
Usage: optional
Value type: <bool>
Definition: Boolean property to enable ESR estimation during discharge.
Only valid if 'qcom,esr-disable' is not defined.
- qcom,esr-qual-current-ua
Usage: optional
Value type: <u32>
Definition: Minimum current differential in uA to qualify an ESR
reading as valid. If not defined the value defaults
to 130mA.
- qcom,esr-qual-vbatt-uv
Usage: optional
Value type: <u32>
Definition: Minimum vbatt differential in uV to qualify an ESR
reading as valid. If not defined the value defaults
to 7mV.
- qcom,esr-disable-soc
Usage: optional
Value type: <u32>
Definition: Minimum battery SOC below which ESR will not be
attempted by QG. If not defined the value defaults
to 10%.
- qcom,esr-chg-min-ibat-ua
Usage: optional
Value type: <int>
Definition: Minimun charge current (IBAT) in uA at which ESR will
be attempted. If not specified the default value is
in -450mA.
- qcom,qg-ext-sns
Usage: optional
Value type: <bool>
Definition: Boolean property to support external-rsense based
configuration.
- qcom,shutdown-temp-diff
Usage: optional
Value type: <u32>
Definition: The allowed battery temperature in deci-degree difference
between shutdown and power-on to continue with the shutdown
SOC. If not specified the default value is 6 degrees C (60).
- qcom,shutdown-soc-threshold
Usage: optional
Value type: <u32>
Definition: The SOC difference allowed between PON and SHUTDOWN SOC
for the shutdown SOC to be used. If the difference is
beyond this value the PON SOC is used.
- qcom,qg-use-s7-ocv
Usage: optional
Value type: <bool>
Definition: Boolean property to use S7 for PON OCV.
- qcom,min-sleep-time-secs
Usage: optional
Value type: <u32>
Definition: The minimum sleep time in secs to allow a SOC
jump if there has been a GOOD_OCV.
- qcom,qg-sys-min-voltage
Usage: optional
Value type: <u32>
Definition: The voltage threshold (in mV) which describes the system
minimum voltage as per the hardware recommendation. This
is not used for any configuration but only for calculating
the available power. If this property is not specified,
then the default value used is 2800 mV.
- qcom,qg-sleep-config
Usage: optional
Value type: bool
Definition: Enables sleep-state configurtion for QG. This
allows configuring the FIFO length, accumulator
interval and the accumulator length when system
enters sleep.
- qcom,sleep-s2-fifo-length
Usage: optional
Value type: <u32>
Definition: The FIFO length to be applied when system enters sleep
while discharging. Takes effect only if
'qcom,qg-sleep-config' is enabled. the default value
if not specified is 8.
- qcom,sleep-s2-acc-length
Usage: optional
Value type: <u32>
Definition: The accululator length to be applied when system
enters sleep while discharging. Takes effect only if
'qcom,qg-sleep-config' is enabled. the default value
if not specified is 256.
- qcom,sleep-s2-acc-intvl-ms
Usage: optional
Value type: <u32>
Definition: The accululator count to be applied when system
enters sleep while discharging. Takes effect only if
'qcom,qg-sleep-config' is enabled. the default value
if not specified is 200ms.
- qcom,qg-fast-chg-config
Usage: optional
Value type: bool
Definition: Enables fast-charge configurtion for QG. This
allows configuring the FIFO length during
fast charge.
- qcom,fast-chg-s2-fifo-length
Usage: optional
Value type: <u32>
Definition: The FIFO length to be applied when system enters
fast-chargging. Takes effect only if
'qcom,qg-fast-chg-config' is enabled. The
default value if not specified is 1.
- qcom,fvss-enable
Usage: optional
Value type: bool
Definition: Enable Filtered Voltage based SOC scaling.
This logic enables SOC scaling to report
0 at the cutoff voltage.
- qcom,fvss-vbatt-mv
Usage: optional
Value type: <u32>
Definition: Battery voltage threshold at which FVSS is
enabled. Applicable only if 'qcom,fvss-enable'
is set.
- qcom,multi-profile-load
Usage: optional
Value type: <bool>
Definition: A boolean property that when specified indicates that
multiple profile loading needs to be enabled. This requires
multiple battery profiles to be specified for a battery for
proper functionality.
- qcom,tcss-enable
Usage: optional
Value type: bool
Definition: Enable Termination current based SOC scaling.
This logic enables SOC scaling to report
100% at the QG termination current defined by
qcom,qg-iterm-ma.
- qcom,tcss-entry-soc
Usage: optional
Value type: <u32>
Definition: SOC threshold at which TCSS starts. The default
value is 90%. This property is valid only if
qcom,tcss-enable is defined.
- qcom,bass-enable
Usage: optional
Value type: bool
Definition: Enable Battery SOC based SOC scaling. This logic
allows monotonic-SOC scaling at low-temperatures
when there is variation in system-SOC due to
changes in the load.
==========================================================
Second Level Nodes - Peripherals managed by QGAUGE driver
==========================================================
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: Addresses and sizes for the specified peripheral
- interrupts
Usage: optional
Value type: <prop-encoded-array>
Definition: Interrupt mapping as per the interrupt encoding
- interrupt-names
Usage: optional
Value type: <stringlist>
Definition: Interrupt names. This list must match up 1-to-1 with the
interrupts specified in the 'interrupts' property.
========
Example
========
pmi632_qg: qpnp,qg {
compatible = "qcom,pm7250b-qg";
qcom,qg-vadc = <&pmi632_vadc>;
qcom,vbatt-empty-mv = <3200>;
qcom,vbatt-low-mv = <3500>;
qcom,vbatt-cutoff-mv = <3400>;
qcom,qg-iterm-ma = <100>;
#io-channel-cells = <1>;
io-channels = <&pm7250b_charger PSY_IIO_RECHARGE_SOC>,
<&pm7250b_charger PSY_IIO_CHARGE_DONE>;
io-channel-names = "recharge_soc",
"charge_done";
qcom,qgauge@4800 {
status = "okay";
reg = <0x4800 0x100>;
interrupts = <0x2 0x48 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x48 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x48 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x48 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x48 0x5 IRQ_TYPE_EDGE_BOTH>,
<0x2 0x48 0x6 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "qg-batt-missing",
"qg-vbat-low",
"qg-vbat-empty",
"qg-fifo-done",
"qg-good-ocv",
"qg-fsm-state-chg",
"qg-event";
};
qcom,qg-sdam@b000 {
status = "okay";
reg = <0xb000 0x100>;
};
};

573
bindings/power/supply/qcom/qpnp-smb5.txt Normal file
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Qualcomm Technologies, Inc. SMB5 Charger Specific Bindings
SMB5 Charger is an efficient programmable battery charger capable of charging a
high-capacity lithium-ion battery over micro-USB or USB Type-C ultrafast with
Quick Charge 2.0, Quick Charge 3.0, and USB Power Delivery support. Wireless
charging features full A4WP Rezence 1.2, WPC 1.2, and PMA support.
=======================
Required Node Structure
=======================
SMB5 Charger must be described in two levels of devices nodes.
===============================
First Level Node - SMB5 Charger
===============================
Charger specific properties:
- compatible
Usage: required
Value type: <string>
Definition: "qcom,pm8150-smb5" for SMB5 on PM8150.
"qcom,pm7250b-smb5" for SMB5 on PM7250B.
"qcom,pm6150-smb5" for SMB5 on PM6150.
"qcom,pmi632-smb5" for SMB5 on PMI632.
- #io-channel-cells:
Usage: required
Value type: <u32>
Definition: Number of cells in an IIO specifier.
Needed to indicate other clients can query charger for
IIO channels.
For details about IIO bindings see:
Documentation/devicetree/bindings/iio/iio-bindings.txt
- qcom,sec-charger-config
Usage: optional
Value type: <u32>
Definition: Specify how the secondary chargers are configured.
0 - No secondary charger.
1 - Charge Pump SMB1390.
2 - SMB1355 parallel charger.
3 - Both Charge Pump and SMB1355.
If the value is not present, 0 is used as default.
- io-channels
- io-channel-names
Usage: optional
Value type: <phandle>
Definition: For details about IIO bindings see:
Documentation/devicetree/bindings/iio/iio-bindings.txt
- qcom,batteryless-platform
Usage: optional
Value type: <empty>
Definition: Boolean flag which indicates that the platform does not have a
battery, and therefore charging should be disabled. In
addition battery properties will be faked such that the device
assumes normal operation.
- qcom,charger-temp-max
Usage: optional
Value type: <u32>
Definition: Specifies the charger temp REG_H_THRESHOLD for PM8150B in deciDegC.
If the value is not present, use the setting read from the device.
- qcom,smb-temp-max
Usage: optional
Value type: <u32>
Definition: Specifies the charger temp REG_H_THRESHOLD for SMB1355 in deciDegC.
If the value is not present, use the setting read from the device.
- qcom,fcc-max-ua
Usage: optional
Value type: <u32>
Definition: Specifies the maximum fast charge current in micro-amps.
If the value is not present, 1Amp is used as default.
- qcom,fv-max-uv
Usage: optional
Value type: <u32>
Definition: Specifies the maximum float voltage in micro-volts.
If the value is not present, 4.35V is used as default.
- qcom,usb-icl-ua
Usage: optional
Value type: <u32>
Definition: Specifies the USB input current limit in micro-amps.
If the value is not present, 1.5Amps is used as default.
- qcom,usb-ocl-ua
Usage: optional
Value type: <u32>
Definition: Specifies the OTG output current limit in micro-amps.
If the value is not present, 1.5Amps is used as default.
- qcom,dc-icl-ua
Usage: optional
Value type: <u32>
Definition: Specifies the DC input current limit in micro-amps.
- qcom,boost-threshold-ua
Usage: optional
Value type: <u32>
Definition: Specifies the boost current threshold in micro-amps.
If the value is not present, 100mA is used as default.
- qcom,thermal-mitigation
Usage: optional
Value type: Array of <u32>
Definition: Array of fast charge current limit values for
different system thermal mitigation levels.
This should be a flat array that denotes the
maximum charge current in mA for each thermal
level.
- qcom,float-option
Usage: optional
Value type: <u32>
Definition: Configures how the charger behaves when a float charger is
detected by APSD.
1 - Treat as a DCP.
2 - Treat as a SDP.
3 - Disable charging.
4 - Suspend USB input.
- qcom,hvdcp-disable
Usage: optional
Value type: <empty>
Definition: Specifies if hvdcp charging is to be enabled or not.
If this property is not specified hvdcp will be enabled.
If this property is specified, hvdcp 2.0 detection will still
happen but the adapter won't be asked to switch to a higher
voltage point.
- qcom,chg-inhibit-threshold-mv
Usage: optional
Value type: <u32>
Definition: Charge inhibit threshold in milli-volts. Charging will be
inhibited when the battery voltage is within this threshold
from Vfloat at charger insertion. If this is not specified
then charge inhibit will be disabled by default.
Allowed values are: 50, 100, 200, 300.
- qcom,chg-term-src
Usage: optional
Value type: <u32>
Definition: Specify either the ADC or analog comparators to be used in order
to set threshold values for charge termination current.
0 - Unspecified
1 - Select ADC comparator
2 - Select ANALOG comparator
- qcom,chg-term-current-ma
Usage: optional
Value type: <u32>
Definition: When ADC comparator is selected as qcom,chg-term-src, this
parameter should be set to the desired upper threshold.
- qcom,chg-term-base-current-ma
Usage: optional
Value type: <u32>
Definition: When ADC comparator is selected as qcom,chg-term-src, this
parameter should be set to the desired lower threshold.
- qcom,auto-recharge-soc
Usage: optional
Value type: <u32>
Definition: Specifies the SOC threshold at which the charger will
restart charging after termination. The value specified
ranges from 0 - 100. The feature is enabled if this
property is specified with a valid SOC value.
- qcom,auto-recharge-vbat-mv
Usage: optional
Value type: <u32>
Definition: Specifies the battery voltage threshold at which the charger
will restart charging after termination. The value specified
is in milli-volts.
- qcom,suspend-input-on-debug-batt
Usage: optional
Value type: <empty>
Definition: Boolean flag which when present enables input suspend for
debug battery.
- qcom,fake-chg-status-on-debug-batt
Usage: optional
Value type: <empty>
Definition: Boolean flag which when present shows charging status as
unknown for debug battery. This needs to be specified only if
the device needs to be kept powered on always with
"svc power stayon true".
- qcom,min-freq-khz
Usage: optional
Value type: <u32>
Definition: Specifies the minimum charger buck/boost switching frequency
in KHz. It overrides the min frequency defined for the charger.
- qcom,max-freq-khz
Usage: optional
Value type: <u32>
Definition: Specifies the maximum charger buck/boost switching frequency in
KHz. It overrides the max frequency defined for the charger.
- qcom,otg-deglitch-time-ms
Usage: optional
Value type: <u32>
Definition: Specifies the deglitch interval for OTG detection.
If the value is not present, 50 msec is used as default.
- qcom,step-charging-enable
Usage: optional
Value type: bool
Definition: Boolean flag which when present enables step-charging.
- qcom,typec-legacy-rp-icl
Usage: optional
Value type: bool
Definition: Boolean property to enable setting ICL based on Rp for
Type-C non-compliant legacy cables.
- qcom,wd-bark-time-secs
Usage: optional
Value type: <u32>
Definition: WD bark-timeout in seconds. The possible values are
16, 32, 64, 128. If not defined it defaults to 64.
- qcom,sw-jeita-enable
Usage: optional
Value type: bool
Definition: Boolean flag which when present enables sw compensation for
jeita.
- qcom,battery-data
Usage: optional
Value type: <phandle>
Definition: Specifies the phandle of the node which contains the battery
profiles supported on the device.
- qcom,flash-derating-soc
Usage: optional
Value type: <u32>
Definition: SOC threshold in percentage below which hardware will start
derating flash. This is only applicable to certain PMICs like
PMI632 which has SCHGM_FLASH peripheral.
- qcom,flash-disable-soc
Usage: optional
Value type: <u32>
Definition: SOC threshold in percentage below which hardware will disable
flash. This is only applicable to certain PMICs like PMI632
which has SCHGM_FLASH peripheral.
- qcom,headroom-mode
Usage: optional
Value type: <u32>
Definition: Specifies flash hardware headroom management policy. The
possible values are:
<0>: Fixed mode, constant 5V at flash input.
<1>: Adaptive mode allows charger output voltage to be
dynamically controlled by the flash module based on the
required flash headroom.
This is only applicable to certain PMICs like PMI632 which
has SCHGM_FLASH peripheral.
- qcom,fcc-stepping-enable
Usage: optional
Value type: bool
Definition: Boolean flag which when present enables stepwise change in FCC.
The default stepping rate is 100mA/sec.
- qcom,disable-suspend-on-collapse
Usage: optional
Value type: bool
Definition: Boolean flag which when present disables suspend on collapse
feature of charger hardware.
- qcom,uusb-moisture-protection-enable
Usage: optional
Value type: bool
Definition: Boolean flag which when present enables mositure protection
feature for uUSB connector type.
- qcom,hvdcp-autonomous-enable
Usage: optional
Value type: bool
Definition: Boolean flag which when present enables hardware-controlled
operation of HVDCP.
- qcom,usb-pd-disable
Usage: optional
Value type: bool
Definition: Boolean flag which when present disables USB-PD operation.
- qcom,lpd-disable
Usage: optional
Value type: bool
Definition: Boolean flag which when present disables liquid presence
detection.
- qcom,hw-die-temp-mitigation
Usage: optional
Value type: bool
Definition: Boolean flag which when present enables h/w based thermal
mitigation.
- qcom,hw-connector-mitigation
Usage: optional
Value type: bool
Definition: Boolean flag which when present enables h/w based
connector temperature mitigation.
- qcom,hw-skin-temp-mitigation
Usage: optional
Value type: bool
Definition: Boolean flag which when present enables h/w based skin
temperature mitigation.
- qcom,en-skin-therm-mitigation
Usage: optional
Value type: bool
Definition: Boolean flag which when present enables skin
thermal mitigation.
- qcom,connector-internal-pull-kohm
Usage: optional
Value type: <u32>
Definition: Specifies internal pull-up configuration to be applied to
connector THERM. The only valid values are (0/30/100/400).
If not specified 100K is used as default pull-up.
- qcom,smb-internal-pull-kohm
Usage: optional
Value type: <u32>
Definition: Specifies internal pull-up configuration to be applied to
connector THERM, only valid values are (0/30/100/400).
If not specified 100K is used as default pull-up.
- qcom,wd-snarl-time-config
Usage: optional
Value type: <u32>
Definition: WDOG snarl timeout configuration value. The possible values are
0 to 7, where 0 = 62.5ms, 1 = 125ms, 2 = 250ms, 3 = 500ms,
4 = 1s, 5 = 2s, 6 = 4s and 7 = 8s. If not defined, wdog-snarl
irq is disabled by default.
- qcom,adc-based-aicl
Usage: optional
Value type: bool
Definition: Boolean flag which when present enables ADC based AICL.
- qcom,wls-current-max-ua
Usage: optional
Value type: <u32>
Definition: Upper limit of charging current supplied by the wireless charger.
If left unspecified, the HW min value of 1.5 A is applied by
default.
- qcom,fcc-step-delay-ms
Usage: optional
Value type: <u32>
Definition: Specifies the delay between each step of FCC stepper algorithm.
If left unspecified, the default value is 1 Sec.
- qcom,fcc-step-size-ua
Usage: optional
Value type: <u32>
Definition: Specifies the step size of each step of FCC stepper algorithm.
If left unspecified, the default value is 100mA.
- qcom,hvdcp2-max-icl-ua
Usage: optional
Value type: <u32>
Definition: Specifies the maximum input current limit that can be configured
for HVDCP2 adapter.
If left unspecified, the default value is 3000mA.
- qcom,hvdcp3-max-icl-ua
Usage: optional
Value type: <u32>
Definition: Specifies the maximum input current limit that can be configured
for HVDCP3 adapter.
If left unspecified, the default value is 3000mA.
- qcom,hvdcp3-standalone-config
Usage: optional
Value type: bool
Definition: Boolean flag which when present indicates that the charging is
only done by the main charger (standalone, no CP) with a QC 3.0
adapter.
- qcom,disable-fcc-restriction
Usage: optional
Value type: bool
Definition: Boolean flag which when present disables FCC restriction.
=============================================
Second Level Nodes - SMB5 Charger Peripherals
=============================================
Peripheral specific properties:
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: Address and size of the peripheral's register block.
- interrupts
Usage: required
Value type: <prop-encoded-array>
Definition: Peripheral interrupt specifier.
- interrupt-names
Usage: required
Value type: <stringlist>
Definition: Interrupt names. This list must match up 1-to-1 with the
interrupts specified in the 'interrupts' property.
=======
Example
=======
pm8150b_charger: qcom,qpnp-smb5 {
compatible = "qcom,qpnp-smb5";
#address-cells = <1>;
#size-cells = <1>;
#io-channel-cells = <1>;
dpdm-supply = <&qusb_phy0>;
qcom,sec-charger-config = <1>;
io-channels = <&pm8150b_vadc ADC_USB_IN_V_16>,
<&pm8150b_vadc ADC_USB_IN_I>,
<&pm8150b_vadc ADC_CHG_TEMP>,
<&pm7250b_qg PSY_IIO_RESISTANCE_ID>,
<&pm7250b_qg PSY_IIO_CHARGE_COUNTER>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
"resistance_id",
"charge_counter",
"charge_full";
qcom,chgr@1000 {
reg = <0x1000 0x100>;
interrupts = <0x2 0x10 0x0 IRQ_TYPE_NONE>,
<0x2 0x10 0x1 IRQ_TYPE_NONE>,
<0x2 0x10 0x2 IRQ_TYPE_NONE>,
<0x2 0x10 0x3 IRQ_TYPE_NONE>,
<0x2 0x10 0x4 IRQ_TYPE_NONE>;
interrupt-names = "chg-error",
"chg-state-change",
"step-chg-state-change",
"step-chg-soc-update-fail",
"step-chg-soc-update-request";
};
qcom,otg@1100 {
reg = <0x1100 0x100>;
interrupts = <0x2 0x11 0x0 IRQ_TYPE_NONE>,
<0x2 0x11 0x1 IRQ_TYPE_NONE>,
<0x2 0x11 0x2 IRQ_TYPE_NONE>,
<0x2 0x11 0x3 IRQ_TYPE_NONE>;
interrupt-names = "otg-fail",
"otg-overcurrent",
"otg-oc-dis-sw-sts",
"testmode-change-detect";
};
qcom,bat-if@1200 {
reg = <0x1200 0x100>;
interrupts = <0x2 0x12 0x0 IRQ_TYPE_NONE>,
<0x2 0x12 0x1 IRQ_TYPE_NONE>,
<0x2 0x12 0x2 IRQ_TYPE_NONE>,
<0x2 0x12 0x3 IRQ_TYPE_NONE>,
<0x2 0x12 0x4 IRQ_TYPE_NONE>,
<0x2 0x12 0x5 IRQ_TYPE_NONE>;
interrupt-names = "bat-temp",
"bat-ocp",
"bat-ov",
"bat-low",
"bat-therm-or-id-missing",
"bat-terminal-missing";
};
qcom,usb-chgpth@1300 {
reg = <0x1300 0x100>;
interrupts = <0x2 0x13 0x0 IRQ_TYPE_NONE>,
<0x2 0x13 0x1 IRQ_TYPE_NONE>,
<0x2 0x13 0x2 IRQ_TYPE_NONE>,
<0x2 0x13 0x3 IRQ_TYPE_NONE>,
<0x2 0x13 0x4 IRQ_TYPE_NONE>,
<0x2 0x13 0x5 IRQ_TYPE_NONE>,
<0x2 0x13 0x6 IRQ_TYPE_NONE>,
<0x2 0x13 0x7 IRQ_TYPE_NONE>;
interrupt-names = "usbin-collapse",
"usbin-lt-3p6v",
"usbin-uv",
"usbin-ov",
"usbin-plugin",
"usbin-src-change",
"usbin-icl-change",
"type-c-change";
};
qcom,dc-chgpth@1400 {
reg = <0x1400 0x100>;
interrupts = <0x2 0x14 0x0 IRQ_TYPE_NONE>,
<0x2 0x14 0x1 IRQ_TYPE_NONE>,
<0x2 0x14 0x2 IRQ_TYPE_NONE>,
<0x2 0x14 0x3 IRQ_TYPE_NONE>,
<0x2 0x14 0x4 IRQ_TYPE_NONE>,
<0x2 0x14 0x5 IRQ_TYPE_NONE>,
<0x2 0x14 0x6 IRQ_TYPE_NONE>;
interrupt-names = "dcin-collapse",
"dcin-lt-3p6v",
"dcin-uv",
"dcin-ov",
"dcin-plugin",
"div2-en-dg",
"dcin-icl-change";
};
qcom,chgr-misc@1600 {
reg = <0x1600 0x100>;
interrupts = <0x2 0x16 0x0 IRQ_TYPE_NONE>,
<0x2 0x16 0x1 IRQ_TYPE_NONE>,
<0x2 0x16 0x2 IRQ_TYPE_NONE>,
<0x2 0x16 0x3 IRQ_TYPE_NONE>,
<0x2 0x16 0x4 IRQ_TYPE_NONE>,
<0x2 0x16 0x5 IRQ_TYPE_NONE>,
<0x2 0x16 0x6 IRQ_TYPE_NONE>,
<0x2 0x16 0x7 IRQ_TYPE_NONE>;
interrupt-names = "wdog-snarl",
"wdog-bark",
"aicl-fail",
"aicl-done",
"high-duty-cycle",
"input-current-limiting",
"temperature-change",
"switcher-power-ok";
};
qcom,schgm-flash@a600 {
reg = <0xa600 0x100>;
interrupts = <0x2 0xa6 0x0 IRQ_TYPE_NONE>,
<0x2 0xa6 0x1 IRQ_TYPE_NONE>,
<0x2 0xa6 0x2 IRQ_TYPE_NONE>,
<0x2 0xa6 0x3 IRQ_TYPE_NONE>,
<0x2 0xa6 0x4 IRQ_TYPE_NONE>,
<0x2 0xa6 0x5 IRQ_TYPE_NONE>,
<0x2 0xa6 0x6 IRQ_TYPE_NONE>,
<0x2 0xa6 0x7 IRQ_TYPE_NONE>;
interrupt-names = "flash-en",
"torch-req",
"flash-state-change",
"vout-up",
"vout-down",
"ilim1-s1",
"ilim2-s2",
"vreg-ok";
};
};

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Qualcomm Technologies, Inc. SMBLITE Charger Specific Bindings
SMBLITE Charger is an efficient programmable battery charger capable of charging a
lithium-ion battery over micro-USB or USB Type-C.
=======================
Required Node Structure
=======================
SMBLITE Charger must be described in two levels of devices nodes.
===================================
First Level Node - SMBLITE Charger
===================================
Charger specific properties:
- compatible
Usage: required
Value type: <string>
Definition: "qcom,qpnp-smblite".
- qcom,pmic-revid
Usage: required
Value type: phandle
Definition: Should specify the phandle of PMI's revid module. This is used to
identify the PMI subtype.
- io-channels
- io-channel-names
Usage: optional
Value type: <phandle>
Definition: For details about IIO bindings see:
Documentation/devicetree/bindings/iio/iio-bindings.txt
- qcom,batteryless-platform
Usage: optional
Value type: <empty>
Definition: Boolean flag which indicates that the platform does not have a
battery, and therefore charging should be disabled. In
addition battery properties will be faked such that the device
assumes normal operation.
- qcom,fcc-max-ua
Usage: optional
Value type: <u32>
Definition: Specifies the maximum fast charge current in micro-amps in
battery profile.
If the value is not present, 1Amp is used as default.
- qcom,fv-max-uv
Usage: optional
Value type: <u32>
Definition: Specifies the maximum float voltage in micro-volts in
battery profile.
If the value is not present, 4.35V is used as default.
- qcom,usb-icl-ua
Usage: optional
Value type: <u32>
Definition: Specifies the USB input current limit in micro-amps.
If the value is not present, 1.5Amps is used as default.
- qcom,thermal-mitigation
Usage: optional
Value type: Array of <u32>
Definition: Array of fast charge current limit values for
different system thermal mitigation levels.
This should be a flat array that denotes the
maximum charge current in mA for each thermal
level.
- qcom,chg-inhibit-threshold-mv
Usage: optional
Value type: <u32>
Definition: Charge inhibit threshold in milli-volts. Charging will be
inhibited when the battery voltage is within this threshold
from Vfloat at charger insertion. If this is not specified
then charge inhibit will be disabled by default.
Allowed values are: 50, 100, 200, 300.
- qcom,chg-term-src
Usage: optional
Value type: <u32>
Definition: Specify either the ADC or analog comparators to be used in order
to set threshold values for charge termination current.
0 - Unspecified
1 - Select ADC comparator
2 - Select ANALOG comparator
- qcom,chg-term-current-ma
Usage: optional
Value type: <u32>
Definition: When ADC comparator is selected as qcom,chg-term-src, this
parameter should be set to the desired upper threshold.
- qcom,chg-term-base-current-ma
Usage: optional
Value type: <u32>
Definition: When ADC comparator is selected as qcom,chg-term-src, this
parameter should be set to the desired lower threshold.
- qcom,auto-recharge-soc
Usage: optional
Value type: <u32>
Definition: Specifies the SOC threshold at which the charger will
restart charging after termination. The value specified
ranges from 0 - 100. The feature is enabled if this
property is specified with a valid SOC value.
- qcom,auto-recharge-vbat-mv
Usage: optional
Value type: <u32>
Definition: Specifies the battery voltage threshold at which the charger
will restart charging after termination. The value specified
is in milli-volts.
- qcom,suspend-input-on-debug-batt
Usage: optional
Value type: <empty>
Definition: Boolean flag which when present enables input suspend for
debug battery.
- qcom,fake-chg-status-on-debug-batt
Usage: optional
Value type: <empty>
Definition: Boolean flag which when present shows charging status as
unknown for debug battery. This needs to be specified only if
the device needs to be kept powered on always with
"svc power stayon true".
- qcom,typec-legacy-rp-icl
Usage: optional
Value type: bool
Definition: Boolean property to enable setting ICL based on Rp for
Type-C non-compliant legacy cables.
- qcom,wd-bark-time-secs
Usage: optional
Value type: <u32>
Definition: WD bark-timeout in seconds. The possible values are
16, 32, 64, 128. If not defined it defaults to 64.
- qcom,battery-data
Usage: optional
Value type: <phandle>
Definition: Specifies the phandle of the node which contains the battery
profiles supported on the device.
- qcom,flash-derating-soc
Usage: optional
Value type: <u32>
Definition: SOC threshold in percentage below which hardware will start
derating flash. This is only applicable to certain PMICs like
PMI632 which has SCHGM_FLASH peripheral.
- qcom,flash-disable-soc
Usage: optional
Value type: <u32>
Definition: SOC threshold in percentage below which hardware will disable
flash. This is only applicable to certain PMICs like PMI632
which has SCHGM_FLASH peripheral.
- qcom,headroom-mode
Usage: optional
Value type: <u32>
Definition: Specifies flash hardware headroom management policy. The
possible values are:
<0>: Fixed mode, constant 5V at flash input.
<1>: Adaptive mode allows charger output voltage to be
dynamically controlled by the flash module based on the
required flash headroom.
This is only applicable to certain PMICs like PMI632 which
has SCHGM_FLASH peripheral.
- qcom,fcc-stepping-enable
Usage: optional
Value type: bool
Definition: Boolean flag which when present enables stepwise change in FCC.
The default stepping rate is 100mA/sec.
- qcom,disable-suspend-on-collapse
Usage: optional
Value type: bool
Definition: Boolean flag which when present disables suspend on collapse
feature of charger hardware.
- qcom,fcc-step-delay-ms
Usage: optional
Value type: <u32>
Definition: Specifies the delay between each step of FCC stepper algorithm.
If left unspecified, the default value is 1 Sec.
- qcom,fcc-step-size-ua
Usage: optional
Value type: <u32>
Definition: Specifies the step size of each step of FCC stepper algorithm.
If left unspecified, the default value is 100mA.
=================================================
Second Level Nodes - SMBLITE Charger Peripherals
=================================================
Peripheral specific properties:
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: Address and size of the peripheral's register block.
- interrupts
Usage: required
Value type: <prop-encoded-array>
Definition: Peripheral interrupt specifier.
- interrupt-names
Usage: required
Value type: <stringlist>
Definition: Interrupt names. This list must match up 1-to-1 with the
interrupts specified in the 'interrupts' property.
=======
Example
=======
pm2250_charger: qcom,qpnp-smblite {
compatible = "qcom,qpnp-smblite";
#address-cells = <1>;
#size-cells = <1>;
#cooling-cells = <2>;
qcom,pmic-revid = <&pm2250_revid>;
qcom,chgr@1000 {
reg = <0x1000 0x100>;
interrupts =
<0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>,
<0x0 0x10 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "chgr-error",
"chg-state-change",
"buck-oc",
"vph-ov";
};
qcom,dcdc@1100 {
reg = <0x1100 0x100>;
interrupts =
<0x0 0x11 0x0 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x6 IRQ_TYPE_EDGE_RISING>,
<0x0 0x11 0x7 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "otg-fail",
"otg-fault",
"skip-mode",
"input-current-limiting",
"switcher-power-ok";
};
qcom,batif@1200 {
reg = <0x1200 0x100>;
interrupts =
<0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x3 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x12 0x4 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "bat-temp",
"bat-therm-or-id-missing",
"bat-low",
"bat-ov",
"bsm-active";
};
qcom,usb@1300 {
reg = <0x1300 0x100>;
interrupts =
<0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x3 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "usbin-plugin",
"usbin-collapse",
"usbin-uv",
"usbin-ov",
"usbin-gtvt",
"usbin-icl-change";
};
qcom,typec@1500 {
reg = <0x1500 0x100>;
interrupts =
<0x0 0x15 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x15 0x5 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x6 IRQ_TYPE_EDGE_RISING>,
<0x0 0x15 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "typec-or-rid-detect-change",
"typec-vpd-detect",
"typec-cc-state-change",
"typec-vbus-change",
"typec-attach-detach",
"typec-legacy-cable-detect",
"typec-try-snk-src-detect";
};
qcom,misc@1600 {
reg = <0x1600 0x100>;
interrupts =
<0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x2 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x3 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x5 IRQ_TYPE_EDGE_RISING>,
<0x0 0x16 0x6 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "wdog-snarl",
"wdog-bark",
"aicl-fail",
"aicl-done",
"imp-trigger",
"all-chnl-cond-done",
"temp-change";
};
};

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Qualcomm Technologies, Inc. SMB1355 Charger Specific Bindings
SMB1355 slave charger is paired with QTI family of standalone chargers to
enable a high current, low profile Li+ battery charging system.
The device provides 28V DC withstand, wide operating input range of 3.8 to
14.2V for standard 5V USB inputs as well as a wide variety of HVDCP Travel
Adapters and is compatible with QTI's Quick Charge technology.
=======================
Required Node Structure
=======================
SMB1355 Charger must be described in two levels of device nodes.
==================================
First Level Node - SMB1355 Charger
==================================
Charger specific properties:
- compatible
Usage: required
Value type: <string>
Definition: "qcom,smb1355".
- qcom,pmic-revid
Usage: required
Value type: phandle
Definition: Should specify the phandle of SMB's revid module. This is used
to identify the SMB subtype.
- qcom,disable-ctm
Usage: optional
Value type: <empty>
Definition: boolean flag. Usually a thermistor near usb/typeC connector is
connected to AUX. Set this flag to indicate the thermistor
doesn't exist.
- qcom,parallel-mode
Usage: optional
Value type: <u32>
Definition: Specifies parallel charging mode. If not specified, MID-MID
option is selected by default.
- qcom,stacked-batfet
Usage: optional
Value type: <empty>
Definition: boolean flag. Specifies if parallel charger has stacked BATFET
configuration.
In stacked batfet the main and parallel charger's batfet are
stacked one after the other and thus all the charge current
(FCC) flows through main. In a non-stacked configuration each
charger controls the charge current (FCC) separately.
- qcom,die-temp-threshold-degc
Usage: optional
Value type: <u32>
Definition: Specifies DIE temp threshold beyond which h/w starts mitigation.
If not sepcified, 90 degrees centigrade is used.
- qcom,hw-die-temp-mitigation
Usage: optional
Value type: bool
Definition: Boolean property to enable h/w controlled die temp mitigation.
================================================
Second Level Nodes - SMB1355 Charger Peripherals
================================================
Peripheral specific properties:
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: Address and size of the peripheral's register block.
- interrupts
Usage: required
Value type: <prop-encoded-array>
Definition: Peripheral interrupt specifier.
- interrupt-names
Usage: required
Value type: <stringlist>
Definition: Interrupt names. This list must match up 1-to-1 with the
interrupts specified in the 'interrupts' property.
=======
Example
=======
smb1355_charger: qcom,smb1355-charger {
compatible = "qcom,smb1355";
#address-cells = <1>;
#size-cells = <1>;
qcom,chgr@1000 {
reg = <0x1000 0x100>;
interrupts = <0x10 0x1 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "chg-state-change";
};
qcom,chgr-misc@1600 {
reg = <0x1600 0x100>;
interrupts = <0x16 0x1 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "wdog-bark";
};
};

113
bindings/power/supply/qcom/smb1398-charger.txt Normal file
View File

@@ -0,0 +1,113 @@
Qualcomm Technologies, Inc. SMB1398 Charger Specific Bindings
SMB1398 combo charge chip can be working in different modes:
(1) DIV2 charge pump mode to work as a companion charger that can be paired
with Qualcomm Technologies, Inc. family of standalone chargers;
(2) DIV2 and 3-level buck combo mode to regulate output power from wireless
charger receiver and provide input power for downstream chargers.
=======================
Required Node Structure
=======================
SMB1398 Charger must be described in two levels of device nodes.
==================================
First Level Node - SMB1398 Charger
==================================
Charger specific properties:
- compatible
Usage: required
Value type: <string>
Definition: "qcom,smb1396-div2-cp-master" for SMB1396 working in DIV2
mode as a companion master charger.
"qcom,smb1396-div2-cp-slave" for SMB1396 working in DIV2
mode as a companion slave charger.
"qcom,smb1398-pre-regulator" for SMB1398 working in combo
mode (auto transition between DIV2 CP and 3-level buck) as a
pre-regulator stand between wireless receiver and downstream
chargers.
- interrupts
Usage: optional
Value type: <prop-encoded-array>
Definition: Peripheral interrupt specifier. This is required when SMB1396
working as a DIV2 CP master.
- interrupt-names
Usage: optional
Value type: <stringlist>
Definition: Interrupt names. This list must match up 1-to-1 with the
interrupts specified in the 'interrupts' property. This is
required when SMB1396 working as a DIV2 CP master.
- io-channels
Usage: optional
Value type: <phandle-array>
Definition: IIO channel specifiers for each name in io-channel-names.
For other details about IIO bindings see:
Documentation/devicetree/bindings/iio/iio-bindings.txt
These properties are required when SMB1396 working as a DIV2 CP
master.
- io-channel-names
Usage: optional
Value type: <string-array>
Definition: Names of the IIO channels that are used by CP master.
- qcom,div2-cp-min-ilim-ua
Usage: optional
Value type: <u32>
Definition: The minimum ILIM settings to enable SMB1398 working in DIV2 mode.
The switcher is disabled when ILIM is below this value.
If this values is not specified, the default minimum ILIM is 1A.
This is only applicable when SMB1396 working as a DIV2 CP master.
- qcom,max-cutoff-soc
Usage: optional
Value type: <u32>
Definition: SOC beyond which SMB1398 is kept disabled.
If this value is not specified then default value is 85%.
This is only applicable when SMB1396 working as a DIV2 CP master.
- qcom,ilim-ua-disable-slave
Usage: optional
Value type: <u32>
Definition: The minimum ILIM setting to disable slave CP after hitting taper.
If this value is not specified, the default value is 3 times of
"qcom,div2-cp-min-ilim-ua". This is only applicable when both
SMB1396 DIV2 CP master and slave are present.
Peripheral specific properties:
=======
Example
=======
smb1398_charger: qcom,combo_charger {
compatible = "qcom,smb1396-div2-cp-master";
interrupt-parent = <&smb1398>;
status = "disabled";
io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_vadc ADC5_AMUX_THM2>;
io-channel-names = "current_capability",
"real_type",
"die_temp";
interrupts = <0x26 0x1 IRQ_TYPE_EDGE_RISING>,
<0x26 0x3 IRQ_TYPE_EDGE_RISING>,
<0x26 0x5 IRQ_TYPE_EDGE_RISING>,
<0x26 0x7 IRQ_TYPE_EDGE_RISING>,
<0x27 0x5 IRQ_TYPE_EDGE_RISING>,
<0x27 0x6 IRQ_TYPE_EDGE_RISING>,
<0x27 0x7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "temp-shdwn",
"div2-irev",
"usbin-uv",
"usbin-ov",
"div2-ilim",
"div2-win-uv",
"div2-win-ov";
};

78
bindings/pwm/pwm-qti-lpg.txt
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@@ -36,27 +36,34 @@ device module in Qualcomm Technologies, Inc. PMIC chips.
- nvmem-names:
Usage: optional
Value type: <string>
Definition: The nvmem device name for the SDAM module where the LUT
pattern is stored. It must be "ppg_sdam". This property
is required only when LUT mode is supported with a SDAM
module instead of a LUT module.
Value type: <stringlist>
Definition: The nvmem device name(s) for the SDAM module(s) where the
LUT pattern data is stored. This property is required
only when LUT mode is supported with a SDAM module
instead of a LUT module. It can take the following
mutually exclusive sets of values:
(a) "ppg_sdam":
LUT pattern data and per-channel data are stored in a
single SDAM module.
(b) "lut_sdam", "lpg_chan_sdam":
LUT pattern data and per-channel data are stored in
two different SDAM modules.
- nvmem:
Usage: optional
Value type: <phandle>
Definition: Phandle of the nvmem device to access the LUT stored
in the SDAM module. This property is required only when
LUT mode is supported and the LUT pattern is stored in a
SDAM module instead of a LUT module.
Value type: <phandle-list>
Definition: Phandle(s) of the nvmem device(s) to access the LUT stored
in the SDAM module(s). This property is required only when
LUT mode is supported and the LUT pattern is stored in
SDAM modules instead of a LUT module.
- qcom,pbs-client
Usage: optional
Value type: <phandle>
Definition: Phandle of the PBS client used for sending the PBS
trigger. This property is required when LUT mode is
supported and the LUT pattern is stored in a SDAM
module instead of a LUT module.
supported and the LUT pattern is stored in a single SDAM
module (not two) instead of a LUT module.
- qcom,lut-sdam-base:
Usage: optional
@@ -118,6 +125,12 @@ parameters needs to be configured for that channel.
1 - 511 when LUT module is used, and 8 - 2000 when SDAM
is used.
- qcom,tick-duration-us:
Usage: optional
Value type: <u32>
Definition: The tick duration in microseconds for PPG. If this property
is not specified, a default value of 7800 will be used.
- qcom,ramp-high-index:
Usage: required
Value type: <u32>
@@ -252,3 +265,44 @@ Example when LUT pattern is stored in a SDAM module:
qcom,lpg-sdam-base = <0x64>;
};
};
Example when LUT pattern is stored in two SDAM modules:
pm8350c_pwm_1: pwms@e800 {
compatible = "qcom,pwm-lpg";
reg = <0xe800>;
reg-names = "lpg-base";
#pwm-cells = <2>;
qcom,num-lpg-channels = <3>;
nvmem = <&pmk8350_sdam_21 &pmk8350_sdam_22>;
nvmem-names = "lpg_chan_sdam", "lut_sdam";
qcom,lut-sdam-base = <0x45>;
qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100
90 80 70 60 50 40 30 20 10 0>;
lpg@1 {
qcom,lpg-chan-id = <1>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x48>;
};
lpg@2 {
qcom,lpg-chan-id = <2>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x56>;
};
lpg@3 {
qcom,lpg-chan-id = <3>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x64>;
};
};

3
bindings/regulator/gdsc-regulator.txt
View File

@@ -55,6 +55,9 @@ Optional properties:
- reset-names: reset signal name strings sorted in the same order as the resets
property. These can be supplied only if we support
qcom,skip-logic-collapse.
- qcom,skip-disable-before-sw-enable : Presence denotes a hardware requirement
to leave the GDSC on that has been
enabled by an entity external to HLOS.
Example:
gdsc_oxili_gx: qcom,gdsc@fd8c4024 {

6
bindings/regulator/qpnp-amoled-regulator.txt
View File

@@ -71,6 +71,12 @@ Subnode common properties for OLEDB and AB/IBB regulator devices.
Definition: A boolean property to specify that the pull down control
for AB/IBB needs to be configured during AOD mode.
- qcom,ibb-single-phase:
Usage: optional
Value type: <empty>
Definition: A boolean property to specify that IBB regulator needs to
be configured in single phase always.
Example:
pm8150a_amoled: oledb@e000 {

21
bindings/regulator/rpm-smd-regulator.txt
View File

@@ -50,6 +50,22 @@ Optional properties:
"pmic4-ldo" for PMIC4.
"pmic5-ldo" for PMIC5.
- qcom,supported-modes
Usage: optional; BOB regulators only
Value type: <prop-encoded-array>
Definition: A list of integers specifying the PMIC regulator modes
supported by this regulator. Supported values are
RPMH_REGULATOR_MODE_* (i.e. 0 to 4). Elements must be
specified in order from lowest to highest.
- qcom,mode-threshold-currents
Usage: required if qcom,supported-modes is specified
Value type: <prop-encoded-array>
Definition: A list of integers specifying minimum allowed current in
microamps for each of the modes listed in
qcom,supported-modes. The first element should always be 0.
Elements must be specified in order from lowest to highest.
[Second Level Nodes]
Required properties:
@@ -142,6 +158,11 @@ Optional properties:
regulator to be enabled. Each element supports
the same set of values as the
qcom,init-pin-ctrl-enable property listed below.
- qcom,min-dropout-voltage: Specifies the minimum voltage level difference that the
parent supply regulator must output above the output of
this regulator. It is only meaningful if the property
<regulator-name>-parent-supply has been specified in
the first level node.
The following properties specify initial values for parameters to be sent to the
RPM in regulator requests.

8
bindings/reserved-memory/ramoops.txt
View File

@@ -56,5 +56,13 @@ Optional properties:
max_reason is not specified, it is equivalent to max_reason = 1
(KMSG_DUMP_PANIC).
- mem-type: determine the memory type of the reserved region, compatible with
<unbuffered>, 0: writecombine(same as <unbuffered> is not set), 1: noncached
(same as <unbuffered> is set), 2: normal memory(fully cached for better
performance)
(defaults to 0: writecombine)
- no-dump-oops: if present, only dump panics (defaults to panics and oops)
- flags: if present, pass ramoops behavioral flags (defaults to 0,
see include/linux/pstore_ram.h RAMOOPS_FLAG_* for flag values).

57
bindings/soc/qcom/cdsprm.txt
View File

@@ -4,7 +4,8 @@ CDSP Request Manager driver implements an rpmsg interface with
CDSP subsystem to serve L3 frequency and CPU QoS requests from CDSP.
It also interacts with NPU, Camera modules for Cx iPeak mitigations and
thermal module via CDSP/HVX cooling devices for thermal mitigation of
CDSP core.
CDSP core. It sends VTCM partitioning information on supported chipsets
to CDSP.
Required properties:
- compatible: Must be "qcom,msm-cdsprm-rpmsg"
@@ -12,13 +13,18 @@ Required properties:
- qcom,intents: A list of <number of intents, size of each intent>
- qcom,msm-cdsp-rm: A sub-device node to define CDSPM RM, Cx iPeak mitigation
driver and CDSP core thermal cooling device
driver, CDSP core thermal cooling device and CDSP VTCM partitioning
Required properties:
- compatible: Must be "qcom,msm-cdsp-rm"
- qcom,qos-latency-us: pm_qos latency vote to be applied on CDSP request in
micro seconds
- qcom,qos-maxhold-ms: Maximum hold time for pm_qos latency vote from CDSP
in milli seconds
Optional properties:
Cx iPeak limit management:
- qcom,compute-cx-limit-en: To enable CX ipeak limit management for compute
subsystem
- qcom,compute-priority-mode: when Cx iPeak mitigation is enabled,
@@ -35,6 +41,41 @@ Required properties:
frequency than NPU during concurrency
4 : AIX_OVER_HVX - Allows NPU to run at a higher
frequency than HVX during concurrency
VTCM partitioning:
- qcom,vtcm-paritions: Number of VTCM partitions (maximum 16)
- qcom,vtcm-partition-info: Specifies the partitions, their sizes and
flags. Most importantly flags can be used to
set some partitions as privileged,
i.e. only available to privileged clients.
Currently VTCM_FLAG_PRIMARY(0x1), VTCM_FLAG_SECONDARY (0x2)and
VTCM_FLAG_PRIVILEGED(0x4) are the supported flags per partition
(only one per partition).
Size of each partition should be a multiple of 256KB.
Given 256KB is the minimum VTCM allocation size,
256K, 1M, 4M are supported page sizes.
Specifying a 3MB partition will allow maximum of 1MB page (3x).
Similarly, a 512KB partition will be of 256KB pages (2x).
PRIMARY and SECONDARY partitions are available to all the clients while
the PRIMARY partition is used by default. Partition selection is
controlled by the vtcm-partition-map information.
There must be only one PRIMARY partition.
Partitions must be defined with a linear partition index
starting with 0 till (Number of VTCM partitions - 1).
VTCM memory will be partitioned in the order provided
(0 being the first partition).
- qcom,vtcm-partition-map: Maps application type identifiers to
partitions. Clients use application type IDs to
request non-default partitions.
Application identifier is specified as a value [0 – 31]
in the device tree. The default application identifier
will be 0. Application identifier must be unique for each
partition map. Any unassigned application identifier
in the set of [0 – 31] will be mapped to the PRIMARY partition
and will return failure if there is no
PRIMARY partition configured.
Thermal cooling device:
- #cooling-cells: Number of cooling cells for CDSP cooling device based on
CDSP Q6 core clock throttling
@@ -69,9 +110,19 @@ Example:
qcom,compute-cx-limit-en;
qcom,compute-priority-mode = <2>;
#cooling-cells = <2>;
qcom,vtcm-paritions = <4>;
qcom,vtcm-partition-info = < 0 2048 0x1 >,
< 1 1024 0x2 >,
< 2 512 0x4 >,
< 3 512 0x4 >;
qcom,vtcm-partition-map = < 0 0 >,
< 1 0 >,
< 2 1 >,
< 30 2 >,
< 31 3 >;
};
msm_hvx_rm: qcom,msm_hvx_rm {
msm_hvx_rm: qcom,msm_hvx_rm {
compatible = "qcom,msm-hvx-rm";
#cooling-cells = <2>;
};

29
bindings/soc/qcom/qcom,altmode-glink.txt
View File

@@ -15,20 +15,37 @@ REQUIRED PROPERTIES:
Value type: <stringlist>
Definition: must be "qcom,altmode-glink"
- qcom,altmode-name:
- #altmode-cells:
Usage: required
Value type: <string>
Definition: must be "altmode_N" where N is [0-9]
Value type: <u32>
Definition: must be <1>
EXAMPLE:
EXAMPLE of altmode node definition:
&soc {
qcom,pmic_glink {
...
qcom,altmode {
altmode: qcom,altmode {
compatible = "qcom,altmode-glink";
qcom,altmode-name = "altmode_0";
#altmode-cells = <1>;
};
...
};
};
Altmode client bindings:
REQUIRED PROPERTIES:
- qcom,altmode-dev:
Usage: required
Value type: <phandle>
Definition: must be <phandle_to_altmode_node, N> where N is port index
EXAMPLE of altmode client node definition:
altmode-client {
...
qcom,altmode-dev = <&altmode 0>;
...
}

16
bindings/soc/qcom/qcom,mem-buf.yaml
View File

@@ -17,11 +17,27 @@ properties:
items:
- const: qcom,mem-buf
qcom,mem-buf-capabilities:
oneOf:
- const: supplier
description: Allows the mem-buf driver to supply memory to other VMs.
- const: consumer
description:
Allows the mem-buf driver to request and accept memory from other VMs.
- const: dual
description:
Allows the mem-buf driver to supply memory to other VMs, as well as
request and accept memory from other VMs
required:
- compatible
- qcom,mem-buf-capabilities
examples:
- |
qcom,mem-buf {
compatible = "qcom,mem-buf";
qcom,mem-buf-capabilities = "supplier";
};

28
bindings/soc/qcom/qcom,pmic-pon-log.txt Normal file
View File

@@ -0,0 +1,28 @@
Qualcomm Technologies, Inc. PMIC PON Log
Certain Qualcomm Technologies, Inc. PMIC devices capture power-on, power-off,
and fault information in a binary log found within SDAM peripherals. The PMIC
PON Log device accesses this log and parses it into a human readable format.
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,pmic-pon-log"
- nvmem:
Usage: required
Value type: <phandle-list>
Definition: phandle of the PMIC nvmem device containing the PON log
- nvmem-names:
Usage: required
Value type: <stringlist>
Definition: must be "pon_log"
Example:
pmic-pon-log {
compatible = "qcom,pmic-pon-log";
nvmem = <&pmk8350_sdam_5>;
nvmem-names = "pon_log";
};

31
bindings/soc/qcom/qcom,rimps-log.yaml Normal file
View File

@@ -0,0 +1,31 @@
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/soc/qcom/qcom,rimps-log.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Rimps Logging
description: |
RIMPS logging is a device that uses mailbox to collect the logs
generated from rimps, and dump them into a dedicated log buffer
through ipc_logging framework.
An instance of rimps-log should have the mailbox controller phandle and
addresses of log buffer set aside for this purpose.
properties:
compatible:
Usage: required
Value type: <string>
Definition: Must be "qcom,rimps-log"
example:
- |
rimps_log: qcom,rimps_log@fd04780 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "qcom,rimps-log";
reg = <0x0fd04580 0x200>,
<0x0fd04780 0x200>;
mboxes = <&rimps 1>;
};

80
bindings/soc/qcom/qcom,rimps-memlat.txt Normal file
View File

@@ -0,0 +1,80 @@
RIMPS memory latency
RIMPS memlat is a device that represents the use of the PMU in ARM cores
to measure the parameters for latency driven memory access patterns in rimps.
Required structure:
An instance of rimps-memlat must be described in two levels of device nodes.
The first level describes the controller while the second level describes the
monitors that the controller manages. At least one monitor is required per
controller.
[First Level Nodes]
Required properties:
- compatible: Must be "qcom,rimps-memlat-cpugrp"
- qcom,cpulist: List of CPU phandles to be monitored in a
cluster. Must be a superset of cpulists
described in second level nodes.
- reg-names: pmu-base addresses need to store the pmu events
during LPM and hotplug scenario.
[Second Level Nodes]
Required properties:
- compatible: Must be "qcom,rimps-memlat-mon-l3"
- qcom,core-dev-table: A mapping table of core frequency to a required
bandwidth vote at the given core frequency.
A phandle that contains this property may be
provided instead (to share tables across nodes).
- qcom,cachemiss-ev: The cache miss event that this monitor is
supposed to measure. Optional for compute only.
- reg-names: ftbl_base address required to populate
L3 frequency and perf_base address required to know the current
L3 frequency set.
Optional properties:
- qcom,cpulist: List of CPU phandles to be monitored in a
cluster. Must be a subset of the cpulist
described in first level node. Defaults to
cpulist in first level node if not specified.
- qcom,inst-ev: The instruction count event that this monitor is
supposed to measure. Defaults to 0x08 if not
specified.
- qcom,stall-cycle-ev: The stall cycle count that this monitor is
supposed to measure. Assumes 100% stall if not
specified.
Example:
cpu0_grp: qcom,cpu0_grp {
compatible = "qcom,rimps-memlat-cpugrp";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x0fd04900 0x1000>;
reg-names = "pmu-base";
cpu0_rimps_l3_latmon: qcom,cpu0-rimps-l3-latmon {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "qcom,rimps-memlat-mon-l3";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,cachemiss-ev = <0x17>;
reg = <0x18590100 0xa0>, <0x18590320 0x4>;
reg-names = "ftbl-base", "perf-base";
qcom,core-dev-table =
< 300000 300000000 >,
< 403200 403200000 >,
< 499200 499200000 >,
< 691200 614400000 >,
< 806400 710400000 >,
< 998400 806400000 >,
< 1190400 998400000 >,
< 1286400 1094400000 >,
< 1459200 1248000000 >,
< 1728000 1344000000 >,
< 1804800 1440000000 >,
< 1900800 1516800000 >;
};
};

28
bindings/soc/qcom/qcom,rimps.yaml Normal file
View File

@@ -0,0 +1,28 @@
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/soc/qcom/qcom,rimps.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Rimps Mailbox controller driver
description: |
This mailbox controller act as interface to do doorbell between
HLOS and Rimps subsystem.
properties:
compatible:
Usage: required
Value type: <string>
Definition: Must be "qcom,rimps"
example:
- |
qcom,rimps@0f400000 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "qcom,rimps";
reg = <0x0f400000 0x10>,
<0x0fd90000 0x2000>;
#mbox-cells = <1>;
status = "ok";
};

6
bindings/soc/qcom/qcom,secure-buffer.yaml
View File

@@ -19,6 +19,12 @@ properties:
items:
- const: qcom,secure-buffer
qcom,vmid-cp-camera-preview-ro:
$ref: /schemas/types.yaml#/definitions/flag
description:
Buffers accessible to VMID_CP_CAMERA_PREVIEW must be mapped with
read-only permissions.
required:
- compatible

155
bindings/sound/qcom-audio-dev.txt
View File

@@ -253,6 +253,10 @@ Optional properties:
0 - Unsupported
1 - Supported
- qcom,msm-dai-cdc-dma-dev-id: Indicate how data is packed within
codec DMA.
0 - MSB
1 - LSB
* msm-auxpcm
Required properties:
@@ -961,6 +965,16 @@ Example:
qcom,smmu-enabled;
};
* msm-audio-ion-cma
Required properties:
- compatible : "qcom,msm-audio-ion-cma"
Example:
qcom,msm-audio-ion-cma {
compatible = "qcom,msm-audio-ion-cma";
};
* msm-dai-tdm
[First Level Nodes]
@@ -2164,6 +2178,7 @@ Optional properties:
- qcom,msm_audio_ssr_devs: List the snd event framework clients
- qcom,afe-rxtx-lb: AFE RX to TX loopback.
- qcom,tlmm-gpio: TLMM gpio number for corresponding LPASS gpio
- qcom,wcd-disabled : Property to specify if wcd codec is disabled for the target
Example:
lahaina_snd: sound {
@@ -2173,6 +2188,7 @@ Example:
qcom,wcn-bt = <0>;
qcom,ext-disp-audio-rx = <0>;
qcom,afe-rxtx-lb = <0>;
qcom,wcd-disabled = <0>;
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
@@ -2267,6 +2283,145 @@ Example:
};
};
* HOLI ASoC Machine driver
Required properties:
- compatible : "qcom,holi-asoc-snd".
>>>>>>> kernel.lnx.5.4-200915
- qcom,model : The user-visible name of this sound card.
- qcom,audio-routing : A list of the connections between audio components.
- asoc-platform: This is phandle list containing the references to platform device
nodes that are used as part of the sound card dai-links.
- asoc-platform-names: This property contains list of platform names. The order of
the platform names should match to that of the phandle order
given in "asoc-platform".
- asoc-cpu: This is phandle list containing the references to cpu dai device nodes
that are used as part of the sound card dai-links.
- asoc-cpu-names: This property contains list of cpu dai names. The order of the
cpu dai names should match to that of the phandle order given
in "asoc-cpu". The cpu names are in the form of "%s.%d" form,
where the id (%d) field represents the back-end AFE port id that
this CPU dai is associated with.
- asoc-codec: This is phandle list containing the references to codec dai device
nodes that are used as part of the sound card dai-links.
- asoc-codec-names: This property contains list of codec dai names. The order of the
codec dai names should match to that of the phandle order given
in "asoc-codec".
- qcom,codec-aux-devs: This is phandle list containing the references to Auxilary
codec devices.
Optional properties:
- qcom,msm-mi2s-master: This property is used to inform machine driver
if MSM is the clock master of mi2s. 1 means master and 0 means slave. The
first entry is primary mi2s; the second entry is secondary mi2s, and so on.
- qcom,msm-mbhc-hphl-swh: This property is used to distinguish headset HPHL
switch type on target typically the switch type will be normally open or
normally close, value for this property 0 for normally close and 1 for
normally open.
- qcom,msm-mbhc-gnd-swh: This property is used to distinguish headset GND
switch type on target typically the switch type will be normally open or
normally close, value for this property 0 for normally close and 1 for
normally open.
- qcom,wsa-max-devs : Maximum number of WSA881x devices present in the target
- qcom,wsa-devs : List of phandles for all possible WSA881x devices supported for the target
- qcom,wsa-aux-dev-prefix : Name prefix with Left/Right configuration for WSA881x device
- qcom,ext-disp-audio-rx: Property to specify if Audio over Display port is supported for the target
- qcom,wcn-btfm : Property to specify if WCN BT/FM chip is used for the target
- qcom,mi2s-audio-intf: Property to specify if MI2S interface is used for the target
- qcom,auxpcm-audio-intf: Property to specify if Aux PCM interface is used for the target
- qcom,cdc-dmic-gpios : phandle for Digital mic clk and data gpios.
- qcom,msm_audio_ssr_devs: List the snd event framework clients
- qcom,afe-rxtx-lb: AFE RX to TX loopback.
- qcom,tlmm-gpio: TLMM gpio number for corresponding LPASS gpio
Example:
holi_snd: sound {
compatible = "qcom,holi-asoc-snd";
qcom,mi2s-audio-intf = <1>;
qcom,auxpcm-audio-intf = <1>;
qcom,wcn-bt = <0>;
qcom,afe-rxtx-lb = <0>;
qcom,is-wcd937x-codec = <1>;
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
<&loopback>, <&compress>, <&hostless>,
<&afe>, <&lsm>, <&routing>, <&compr>,
<&pcm_noirq>;
asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
"msm-pcm-dsp.2", "msm-voip-dsp",
"msm-pcm-voice", "msm-pcm-loopback",
"msm-compress-dsp", "msm-pcm-hostless",
"msm-pcm-afe", "msm-lsm-client",
"msm-pcm-routing", "msm-compr-dsp",
"msm-pcm-dsp-noirq";
asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>,
<&dai_mi2s2>, <&dai_mi2s3>,
<&dai_pri_auxpcm>,
<&dai_sec_auxpcm>, <&dai_tert_auxpcm>,
<&dai_quat_auxpcm>,
<&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>,
<&afe_proxy_tx>, <&incall_record_rx>,
<&incall_record_tx>, <&incall_music_rx>,
<&incall_music_2_rx>,
<&afe_proxy_tx_1>,
<&proxy_rx>, <&proxy_tx>,
<&usb_audio_rx>, <&usb_audio_tx>,
<&sb_7_rx>, <&sb_7_tx>,
<&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>,
<&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>,
<&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>,
<&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>,
<&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>,
<&va_cdc_dma_2_tx>,
<&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>,
<&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>,
<&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>,
<&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>,
<&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>,
<&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>,
<&rx_cdc_dma_7_rx>,<&afe_loopback_tx>;
asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",
"msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",
"msm-dai-q6-auxpcm.1",
"msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3",
"msm-dai-q6-auxpcm.4",
"msm-dai-q6-dev.224",
"msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
"msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
"msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
"msm-dai-q6-dev.32770",
"msm-dai-q6-dev.242",
"msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195",
"msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673",
"msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399",
"msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865",
"msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881",
"msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897",
"msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913",
"msm-dai-cdc-dma-dev.45089",
"msm-dai-cdc-dma-dev.45091",
"msm-dai-cdc-dma-dev.45093",
"msm-dai-cdc-dma-dev.45104",
"msm-dai-cdc-dma-dev.45105",
"msm-dai-cdc-dma-dev.45106",
"msm-dai-cdc-dma-dev.45107",
"msm-dai-cdc-dma-dev.45108",
"msm-dai-cdc-dma-dev.45109",
"msm-dai-cdc-dma-dev.45110",
"msm-dai-cdc-dma-dev.45111",
"msm-dai-cdc-dma-dev.45112",
"msm-dai-cdc-dma-dev.45113",
"msm-dai-cdc-dma-dev.45114",
"msm-dai-cdc-dma-dev.45115",
"msm-dai-cdc-dma-dev.45118",
"msm-dai-q6-dev.24577";
};
};
* Waipio ASoC Machine driver
Required properties:

2
bindings/sound/wcd_codec.txt
View File

@@ -66,6 +66,8 @@ Optional properties:
- qcom,va-clk-mux-select VA macro MCLK MUX selection
- qcom,va-island-mode-muxsel VA macro island mode MUX selection
This property is required if qcom,va-clk-mux-select is provided
- qcom,disable-afe-wakeup-event-listener : If enabled wakeup event listener
will not be called from VA macro.
Example:

7
bindings/spi/qcom,spi-msm-geni.txt
View File

@@ -30,6 +30,13 @@ Optional properties:
- qcom,rt: Specifies if the framework worker thread for this
controller device should have "real-time" priority.
- qcom,disable-autosuspend: Specifies to disable runtime PM auto suspend.
- qcom,disable-dma: Set this flag to use FIFO mode only.
- qcom,shared_ee: Specifies that this serial engine is shared between
execution environments.
- qcom,shared_se: Specifies that this serial engine is shared simultaneously
between execution environments. A true multi-EE usecase.
- qcom,le_vm: Specifies that this serial engine is operating in a trusted VM.
SPI slave nodes must be children of the SPI master node and can contain
the following properties.

27
bindings/thermal/qcom,rpm-smd-cdev.txt Normal file
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@@ -0,0 +1,27 @@
Qualcomm Technologies, Inc. RPM SMD cooling device
The RPM shared memory(SMD) cooling device, will be used to set
different thermal band level to RPM hardware. When threshold violation
occurs, RPM SMD cooling device sends pre-configured thermal band level
to RPM hardware via SMD.
Required Parameters:
- compatible:
Usage: required
Value type: <string>
Definition: should be "qcom,rpm-smd-cooling-device"
- #cooling-cells:
Usage: required
Value type: <integer>
Definition: Must be 2. This is required by of-thermal and refer the doc
<devicetree/bindings/thermal/thermal.txt> for more details.
Example:
&rpm_bus {
rpm_smd_cdev: rpm-smd-cdev {
compatible = "qcom,rpm-smd-cooling-device";
#cooling-cells = <2>;
};
};

7
bindings/thermal/qcom-bcl-pmic5.txt
View File

@@ -30,6 +30,12 @@ Required Parameters:
"bcl-lvl1",
"bcl-lvl2",
Optional Parameters:
- qcom,pmic7-threshold:
Value type: <bool>
Definition: When this flag is defined, the BCL driver will account for
no bit shift in the threshold registers.
Example:
bcl@4200 {
compatible = "qcom,bcl-v5";
@@ -38,4 +44,5 @@ Example:
<0x2 0x42 0x1 IRQ_TYPE_NONE>;
interrupt-names = "bcl-lvl0",
"bcl-lvl1";
qcom,pmic7-threshold;
};

41
bindings/thermal/qcom-pe-sensor.txt Normal file
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@@ -0,0 +1,41 @@
Policy Engine(PE) recommendation as sensor.
The QTI Policy Engine sensor device will register the policy engine
recommendation with thermal framework as a sensor. This will enable
to provide configuration to mitigate cooling devices when a recommendation
is sent from Policy Engine hardware. The recommendations are mitigation
levels based on CX operating level.
There can be multiple Policy Engine hardwares for different rails.
Properties:
- compatible:
Usage: required
Value type: <string>
Definition: should be "qcom,policy-engine"
- reg:
Usage: required
Value type: <u32>
Definition: RDPM_PE base address.
- #thermal-sensor-cells:
Usage: required
Value type: <integer>
Definition: Must be 0. See thermal.txt for description.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: Policy Engine master interrupt.
Example:
cx_rdpm_pe@0x00635000 {
compatible = "qcom,policy-engine";
#thermal-sensor-cells = <0>;
reg = <0x00635000 0x1000>;
interrupts = <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>;
};

65
bindings/thermal/qcom-sdpm.txt Normal file
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@@ -0,0 +1,65 @@
Simple Digital Power Meter(SDPM) clock monitoring.
SDPM is used to monitor the operating frequency of different clocks and based
on operating levels of different clients, the Policy Engine will recommend a
new max operating level. The SDPM driver will register with the clock
framework for rate change notification of different clocks. These clock rate
will be updated to SDPM.
Properties:
- compatible:
Usage: required
Value type: <string>
Definition: should be "qcom,sdpm"
- reg:
Usage: required
Value type: <u32>
Definition: RDPM base address.
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: A List of phandle and clock specifier pairs as listed
in clock-names property.
- clock-names:
Usage: required
Value type: <stringlist>
Definition: List of clock names matching the clock order mentioned in
the clocks property.
- <supply-name>-supply:
Usage: Optional
Value type: <regulator phandle>
Definition: phandle to the regulator device tree node that powers
this domain.
- cpu:
Usage: optional
Value type: <CPU phandle>
Definition: The CPU for which the clock changes should be monitored.
- csr-id:
Usage: required
Value type: <array of u32>
Definition: Array of CSR ID matching the clock order mentioned in the
clocks property. The last ID can be the CSR
corresponding to the CPU that needs to be monitored.
Example:
cx_sdpm@0x00634000 {
compatible = "qcom,sdpm";
reg = <0x00634000 0x1000>;
clock-names = "cam_cc_ipe", "compo_aux";
clocks = <&clock_camcc CAM_CC_IPE_0_CLK_SRC>,
<&clk_m_a2_div1 CLK_M_COMPO_AUX>;
cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>;
cpu = <&CPU7>;
csr-id = <5 7 4>;
//CSR 5 <=> cam_cc
//CSR 7 <=> compo_aux
//CSR 4 <=> CPU7
};

14
bindings/thermal/qti-isense-cdsp.txt Normal file
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@@ -0,0 +1,14 @@
===============================================================================
QTI Limits cdsp isense driver:
===============================================================================
Limits cdsp isense driver reads cdsp isense calibration data from shared memory
and enables sysfs file support to access the data read from shared memory.
Required Parameters:
- compatible: must be 'qcom,msm-limits-cdsp' for limits cdsp isense driver.
Optional Parameters:
lmh_isense_cdsp {
compatible = "qcom,msm-limits-cdsp";
};

38
bindings/thermal/regulator-cdev.txt Normal file
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@@ -0,0 +1,38 @@
Regulator cooling device.
The regulator cooling device, will be used to place a voltage floor
restriction on a rail.
Properties:
- compatible:
Usage: required
Value type: <string>
Definition: shall be "qcom,regulator-cooling-device"
- cdev-supply:
Usage: required
Value type: <phandle>
Definition: phandle to the regulator to which the cooling device will
place a floor mitigation.
- regulator-levels:
Usage: required
Value type: <U32 array>
Definition: Array of regulator voltages the cooling device should
use to place a floor restriction. The voltages should
be specified in ascending order.
- #cooling-cells: Must be 2. Please refer to
<devicetree/bindings/thermal/thermal.txt> for more
details.
Example:
mv_cdev: mx-cdev-lvl {
compatible = "qcom,regulator-cooling-device";
cdev-supply = <&regulator-cdev-supply>;
regulator-levels = <RPMH_REGULATOR_LEVEL_OFF
RPMH_REGULATOR_LEVEL_NOM>;
#cooling-cells = <2>;
};

5
bindings/ufs/ufs-qcom.txt
View File

@@ -16,6 +16,11 @@ Required properties:
present on SM8350, SM8450 chipsets.
"qcom,ufs-phy-qrbtc-sdm845" for phy support
for sdm845 emulation.
for sdm845 emulation,
"qcom,ufs-phy-qmp-v4-lahaina" for V4 ufs phy
present on Lahaina chipset.
"qcom,ufs-phy-qmp-v3" for V3 ufs phy
present on holi chipset.
- reg : should contain PHY register address space (mandatory),
- reg-names : indicates various resources passed to driver (via reg proptery) by name.
Required "reg-names" is "phy_mem".

4
bindings/ufs/ufshcd-pltfrm.txt
View File

@@ -23,6 +23,10 @@ Optional properties:
with "phys" attribute, provides phandle to UFS PHY node
- vdd-hba-supply : phandle to UFS host controller supply regulator node
- vcc-supply : phandle to VCC supply regulator node
- vcc-voltage-level : specifies voltage levels for VCC supply.
Should be specified in pairs (min, max), units uV.
- vccq2-voltage-level : specifies voltage levels for VCCQ2 supply.
Should be specified in pairs (min, max), units uV.
- vccq-supply : phandle to VCCQ supply regulator node
- vccq2-supply : phandle to VCCQ2 supply regulator node
- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V

5
bindings/uio/msm_sharedmem.txt
View File

@@ -9,10 +9,15 @@ Required properties:
- reg-names : Indicates various client-names.
- qcom,client-id : The client id for the QMI clients.
Optional properties:
- qcom,vm-nav-path: If this dtsi property is set, then the shared memory region
will be given access to vm-nav-path also.
Example:
qcom,msm_sharedmem@0dc80000 {
compatible = "qcom,sharedmem-uio";
reg = <0x0dc80000 0x00180000>,
reg-names = "rmtfs";
qcom,client-id = <0x00000001>;
qcom,vm-nav-path;
};

2
bindings/usb/dwc3.txt
View File

@@ -78,6 +78,8 @@ Optional properties:
park mode are disabled.
- snps,dis_metastability_quirk: when set, disable metastability workaround.
CAUTION: use only if you are absolutely sure of it.
- snps,ssp-u3-u0-quirk: when set, core always changes PHY power state to P2
before attempting a U3 exit handshake.
- snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
utmi_l1_suspend_n, false when asserts utmi_sleep_n
- snps,hird-threshold: HIRD threshold

102
bindings/usb/qcom,msm-phy.txt
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@@ -151,3 +151,105 @@ Example:
"phy_phy_reset";
};
QUSB2 High-Speed PHY
Required properties:
- compatible: Should be "qcom,qusb2phy" or "qcom,qusb2phy-v2"
- reg: Address and length of the QUSB2 PHY register set
- reg-names: Should be "qusb_phy_base".
- <supply-name>-supply: phandle to the regulator device tree node
Required supplies are:
"vdd" : vdd supply for digital circuit operation
"vdda18" : 1.8v high-voltage analog supply
"vdda33" : 3.3v high-voltage analog supply
"refgen" : 1.2v high-voltage analog supply
- clocks: a list of phandles to the PHY clocks. Use as per
Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
property. "ref_clk_src" is a mandatory clock.
- qcom,vdd-voltage-level: This property must be a list of three integer
values (no, min, max) where each value represents either a voltage in
microvolts or a value corresponding to voltage corner
- phy_type: Should be one of "ulpi" or "utmi". ChipIdea core uses "ulpi" mode.
- resets: reset specifier pair consists of phandle for the reset controller
and reset lines used by this controller.
- reset-names: reset signal name strings sorted in the same order as the resets
property.
- qcom,qusb-phy-reg-offset: Provides important phy register offsets in an order defined in phy driver.
Optional properties:
- reg-names: Additional registers corresponding with the following:
"efuse_addr": EFUSE address to read and update analog tune parameter.
"emu_phy_base" : phy base address used for programming emulation target phy.
"ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset.
"tcsr_clamp_dig_n" : To enable/disable digital clamp to the phy. When
de-asserted, it will prevent random leakage from qusb2 phy resulting from
out of sequence turn on/off of 1p8, 3p3 and DVDD regulators.
"refgen_north_bg_reg" : address used to read REFGEN status for overriding QUSB PHY register.
"tcsr_conn_box_spare" : To enable/disable USB HS AC/DC coupling feature. When
enabled, DP/DM signals will take path through capacitor when USB HS device is
connected. This is a required property if 'qcom,usb-hs-ac-bitmask' property is present.
- clocks: a list of phandles to the PHY clocks. Use as per
Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
property. "cfg_ahb_clk" and "ref_clk" are optional clocks.
- qcom,qusb-phy-init-seq: QUSB PHY initialization sequence with value,reg pair.
- qcom,qusb-phy-host-init-seq: QUSB PHY initialization sequence for host mode
with value,reg pair.
- qcom,emu-init-seq : emulation initialization sequence with value,reg pair.
- qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair.
- qcom,emu-dcm-reset-seq : emulation DCM reset sequence with value,reg pair.
- qcom,tune2-efuse-bit-pos: TUNE2 parameter related start bit position with EFUSE register for "qcom,qusb2phy".
- qcom,tune2-efuse-num-bits: Number of bits based value to use for TUNE2 high nibble for "qcom,qusb2phy".
- qcom,efuse-bit-pos: start bit position within EFUSE register for "qcom,qusb2phy-v2".
- qcom,efuse-num-bits: Number of bits to read from EFUSE register for "qcom,qusb2phy-v2".
- qcom,emulation: Indicates that we are running on emulation platform.
- qcom,hold-reset: Indicates that hold QUSB PHY into reset state.
- qcom,phy-clk-scheme: Should be one of "cml" or "cmos" if ref_clk_addr is provided.
- qcom,major-rev: provide major revision number to differentiate power up sequence. default is 2.0
- pinctrl-names/pinctrl-0/1: The GPIOs configured as output function. Allowed names are
"default" and "sleep".
- qcom,tune2-efuse-correction: The value to be adjusted from fused value for
improved rise/fall times.
- qcom,host-chirp-erratum: Indicates host chirp fix is required.
- qcom,override-bias-ctrl2: Indicates override is done from driver for
BIAS_CTRL2 register.
- nvmem-cells: specifies the handle to represent the SoC revision.
usually it is defined by qfprom device node.
- nvmem-cell-names: specifies the given nvmem cell name as defined in
qfprom node.
- qcom,usb-hs-ac-bitmask: Specifies the polarity and enable bitfields in
tcsr_conn_box_spare register so as to enable USB HS AC/DC coupling feature.
- qcom,usb-hs-ac-value: Specifies the value to be written to polarity and
enable bitfields so as to enable USB HS AC/DC coupling feature. This is a
required property if 'qcom,usb-hs-ac-bitmask' property is present.
Example:
qusb_phy: qusb@f9b39000 {
compatible = "qcom,qusb2phy";
reg = <0x00079000 0x7000>;
reg-names = "qusb_phy_base";
vdd-supply = <&pm8994_s2_corner>;
vdda18-supply = <&pm8994_l6>;
vdda33-supply = <&pm8994_l24>;
refgen-supply = <&pm8994_l21>;
qcom,vdd-voltage-level = <1 5 7>;
qcom,qusb-phy-reg-offset =
<0x240 /* QUSB2PHY_PORT_TUNE1 */
0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */
0x210 /* QUSB2PHY_PWR_CTRL1 */
0x230 /* QUSB2PHY_INTR_CTRL */
0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */
0x254 /* QUSB2PHY_TEST1 */
0x198>; /* QUSB2PHY_PLL_BIAS_CONTROL_2 */
qcom,efuse-bit-pos = <21>;
qcom,efuse-num-bits = <3>;
clocks = <&clock_rpm clk_ln_bb_clk>,
clock_gcc clk_gcc_rx2_usb1_clkref_clk>,
<&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>;
clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk";
resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;
reset-names = "phy_reset";
};

71
bindings/usb/qpnp-pdphy.txt Normal file
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@@ -0,0 +1,71 @@
Qualcomm Technologies, Inc. QPNP PD PHY - USB Power Delivery Physical layer
Required properties:
- compatible: Must be "qcom,qpnp-pdphy"
- reg: The base address for this peripheral
- vdd-pdphy-supply: phandle to the VDD supply regulator node
- interrupts: Specifies the interrupt associated with the peripheral.
- interrupt-names: Specifies the interrupt names for the peripheral. Every
available interrupt needs to have an associated name
with it to indentify its purpose.
The following interrupts are required:
0: sig-tx
Triggers when a signal (HardReset or CableReset)
has been sent.
1: sig-rx
Triggers when a signal has been received.
2: msg-tx
Triggers when a message has been sent and the
related GoodCRC has been received.
3: msg-rx
Triggers when a message has been received and
the related GoodCRC was sent successfully.
4: msg-tx-failed
Triggers when a message failed all its
transmission attempts, either due to a non-idle
bus or missing GoodCRC reply.
5: msg-tx-discarded
Triggers when a message is received while a
transmission request was in place. The request
itself is discarded.
6: msg-rx-discarded
Triggers when a message was received but had to
be discarded due to the RX buffer still in use
by SW.
Optional properties:
- vbus-supply: Regulator that enables VBUS source output
- vconn-supply: Regulator that enables VCONN source output. This will
be supplied on the USB CC line that is not used for
communication when Ra resistance is detected.
- qcom,default-sink-caps: List of 32-bit values representing the nominal sink
capabilities in voltage (millivolts) and current
(milliamps) pairs.
Example:
qcom,qpnp-pdphy@1700 {
compatible = "qcom,qpnp-pdphy";
reg = <0x1700 0x100>;
vdd-pdphy-supply = <&pm8998_l24>;
interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x1 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x2 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x3 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x4 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x5 IRQ_TYPE_EDGE_RISING>,
<0x2 0x17 0x6 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "sig-tx",
"sig-rx",
"msg-tx",
"msg-rx",
"msg-tx-failed",
"msg-tx-discarded",
"msg-rx-discarded";
qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */
<9000 3000>, /* 9V @ 3A */
<12000 2250>; /* 12V @ 2.25A */
};

2
bindings/vendor-prefixes.yaml
View File

@@ -1017,7 +1017,7 @@ patternProperties:
description: Sun Microsystems, Inc
"^swir,.*":
description: Sierra Wireless
"^syna,.*":
"^synaptics,.*":
description: Synaptics Inc.
"^synology,.*":
description: Synology, Inc.

115
qcom/Makefile
View File

@@ -5,33 +5,74 @@ dtbo-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi-overlay.dtbo \
lahaina-mtp-hsp-overlay.dtbo \
lahaina-cdp-overlay.dtbo \
lahaina-qrd-overlay.dtbo \
lahaina-atp-overlay.dtbo \
lahaina-hdk-overlay.dtbo \
lahaina-qrd-hsp-overlay.dtbo \
lahaina-qrd-module-overlay.dtbo \
lahainap-mtp-overlay.dtbo \
lahainap-cdp-overlay.dtbo \
lahainap-qrd-overlay.dtbo
lahainap-atp-overlay.dtbo \
lahainap-qrd-overlay.dtbo \
lahaina-cdp-v2.2-overlay.dtbo \
lahaina-mtp-v2-overlay.dtbo \
lahaina-mtp-v2.1-overlay.dtbo
lahaina-rumi-overlay.dtbo-base := lahaina.dtb
lahaina-mtp-hsp-overlay.dtbo-base := lahaina.dtb
lahaina-mtp-overlay.dtbo-base := lahaina.dtb
lahaina-cdp-overlay.dtbo-base := lahaina.dtb
lahaina-mtp-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb
lahaina-cdp-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb
lahaina-atp-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb
lahaina-hdk-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb
lahaina-qrd-hsp-overlay.dtbo-base := lahaina.dtb
lahaina-qrd-overlay.dtbo-base := lahaina.dtb
lahaina-qrd-module-overlay.dtbo-base := lahaina.dtb
lahainap-mtp-overlay.dtbo-base := lahainap.dtb
lahainap-cdp-overlay.dtbo-base := lahainap.dtb
lahainap-qrd-overlay.dtbo-base := lahainap.dtb
lahaina-qrd-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb
lahaina-qrd-module-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb lahaina-v2.1.dtb
lahainap-mtp-overlay.dtbo-base := lahainap.dtb lahainap-v2.dtb lahainap-v2.1.dtb
lahainap-cdp-overlay.dtbo-base := lahainap.dtb lahainap-v2.dtb lahainap-v2.1.dtb
lahainap-atp-overlay.dtbo-base := lahainap.dtb lahainap-v2.dtb lahainap-v2.1.dtb
lahainap-qrd-overlay.dtbo-base := lahainap.dtb lahainap-v2.dtb lahainap-v2.1.dtb
lahaina-cdp-v2.2-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb \
lahaina-v2.1.dtb
lahaina-mtp-v2-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb \
lahaina-v2.1.dtb
lahaina-mtp-v2.1-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb \
lahaina-v2.1.dtb
else
dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \
lahaina-mtp-hsp.dtb \
lahaina-mtp.dtb \
lahaina-cdp.dtb \
lahaina-atp.dtb \
lahaina-hdk.dtb \
lahaina-qrd-hsp.dtb \
lahaina-qrd.dtb \
lahaina-qrd-module.dtb \
lahainap-mtp.dtb \
lahainap-cdp.dtb \
lahainap-qrd.dtb
lahainap-atp.dtb \
lahainap-qrd.dtb \
lahaina-v2-mtp.dtb \
lahaina-v2-cdp.dtb \
lahaina-v2-atp.dtb \
lahaina-v2-hdk.dtb \
lahaina-v2-qrd.dtb \
lahaina-v2-qrd-module.dtb \
lahainap-v2-mtp.dtb \
lahainap-v2-cdp.dtb \
lahainap-v2-atp.dtb \
lahainap-v2-qrd.dtb \
lahaina-cdp-v2.2.dtb \
lahaina-v2.1-mtp.dtb \
lahaina-v2.1-cdp.dtb \
lahaina-v2.1-atp.dtb \
lahaina-v2.1-hdk.dtb \
lahaina-v2.1-qrd.dtb \
lahaina-v2.1-qrd-module.dtb \
lahainap-v2.1-mtp.dtb \
lahainap-v2.1-cdp.dtb \
lahainap-v2.1-atp.dtb \
lahainap-v2.1-qrd.dtb \
lahaina-mtp-v2.dtb \
lahaina-mtp-v2.1.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
@@ -54,19 +95,50 @@ endif
dtb-$(CONFIG_ARCH_QTI_VM) += trustedvm.dtb
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo
dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \
holi-mtp-overlay.dtbo \
holi-cdp-overlay.dtbo \
holi-cdp-lcd-overlay.dtbo \
holi-qrd-overlay.dtbo \
holi-atp-overlay.dtbo \
holi-mtp-usbc-overlay.dtbo
holi-rumi-overlay.dtbo-base := holi.dtb
holi-mtp-overlay.dtbo-base := holi.dtb
holi-cdp-overlay.dtbo-base := holi.dtb
holi-cdp-lcd-overlay.dtbo-base := holi.dtb
holi-qrd-overlay.dtbo-base := holi.dtb
holi-atp-overlay.dtbo-base := holi.dtb
holi-mtp-usbc-overlay.dtbo-base := holi.dtb
else
dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb
dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb \
holi-mtp.dtb \
holi-cdp.dtb \
holi-cdp-lcd.dtb \
holi-qrd.dtb \
holi-atp.dtb \
holi-mtp-usbc.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_SHIMA) += \
shima-rumi-overlay.dtbo
dtbo-$(CONFIG_ARCH_SHIMA) += \
shima-rumi-overlay.dtbo \
shima-idp-overlay.dtbo \
shima-atp-overlay.dtbo \
shima-qrd-overlay.dtbo \
shima-idps-digital-mics-overlay.dtbo
shima-rumi-overlay.dtbo-base := shima.dtb
shima-idp-overlay.dtbo-base := shima.dtb
shima-atp-overlay.dtbo-base := shima.dtb
shima-qrd-overlay.dtbo-base := shima.dtb
shima-idps-digital-mics-overlay.dtbo-base := shima.dtb
else
dtb-$(CONFIG_ARCH_SHIMA) += shima-rumi.dtb
dtb-$(CONFIG_ARCH_SHIMA) += shima-rumi.dtb \
shima-idp.dtb \
shima-atp.dtb \
shima-qrd.dtb \
shima-idps-digital-mics.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
@@ -95,7 +167,22 @@ endif
ifeq ($(CONFIG_ARCH_LAHAINA), y)
ifeq ($(CONFIG_ARCH_QTI_VM), y)
dtb-$(CONFIG_ARCH_QTI_VM) += trustedvm.dtb
dtb-$(CONFIG_ARCH_QTI_VM) += lahaina-vm-mtp.dtb \
lahaina-vm-cdp.dtb \
lahaina-vm-qrd.dtb
endif
endif
dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \
sdxlemur-cdp.dtb \
sdxlemur-mtp.dtb
ifeq ($(CONFIG_ARCH_SHIMA), y)
ifeq ($(CONFIG_ARCH_QTI_VM), y)
dtb-$(CONFIG_ARCH_QTI_VM) += shima-vm-rumi.dtb \
shima-vm-atp.dtb \
shima-vm-idp.dtb \
shima-vm-qrd.dtb
endif
endif

50
qcom/holi-atp-overlay.dts Normal file
View File

@@ -0,0 +1,50 @@
/dts-v1/;
/plugin/;
#include "holi-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Holi ATP";
compatible = "qcom,holi-atp", "qcom,holi", "qcom,atp";
qcom,msm-id = <454 0x10000>, <472 0x10000>;
qcom,board-id = <33 0>;
};
&wsa881x_i2c_e {
status = "disabled";
};
&wsa881x_i2c_44 {
status = "disabled";
};
&wcd937x_tx_slave {
status = "disabled";
};
&wcd937x_rx_slave {
status = "disabled";
};
&wcd937x_codec {
status = "disabled";
};
&holi_snd {
qcom,wcd-disabled = <1>;
qcom,audio-routing =
"RX_TX DEC0_INP", "TX DEC0 MUX",
"RX_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC2_INP", "TX DEC2 MUX",
"RX_TX DEC3_INP", "TX DEC3 MUX",
"VA SWR_INPUT", "VA_SWR_CLK",
"VA_AIF1 CAP", "VA_SWR_CLK",
"VA_AIF2 CAP", "VA_SWR_CLK",
"VA_AIF3 CAP", "VA_SWR_CLK",
"VA DMIC0", "Digital Mic0",
"VA DMIC1", "Digital Mic1",
"VA DMIC2", "Digital Mic2",
"VA DMIC3", "Digital Mic3",
"VA DMIC4", "Digital Mic4",
"VA DMIC5", "Digital Mic5";
};

10
qcom/holi-atp.dts Normal file
View File

@@ -0,0 +1,10 @@
/dts-v1/;
#include "holi.dtsi"
#include "holi-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Holi ATP";
compatible = "qcom,holi-atp", "qcom,holi", "qcom,atp";
qcom,board-id = <33 0>;
};

298
qcom/holi-atp.dtsi Normal file
View File

@@ -0,0 +1,298 @@
#include "holi-audio-overlay.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include "holi-pmic-overlay.dtsi"
#include "holi-thermal-overlay.dtsi"
#include <dt-bindings/iio/qti_power_supply_iio.h>
&sdhc_1 {
status = "ok";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
vdd-supply = <&L7E>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L12A>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 325000>;
};
&sdhc_2 {
status = "ok";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
vdd-supply = <&L9E>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&L6E>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v3";
vdda-phy-supply = <&L18A>;
vdda-pll-supply = <&L22A>;
vdda-phy-max-microamp = <62900>;
vdda-pll-max-microamp = <18300>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vdd-hba-fixed-regulator;
vcc-supply = <&L7E>;
vcc-voltage-level = <2950000 2960000>;
vcc-max-microamp = <800000>;
vccq2-supply = <&L12A>;
vccq2-max-microamp = <800000>;
vccq2-voltage-level = <1800000 1800000>;
qcom,vddp-ref-clk-supply = <&L22A>;
qcom,vddp-ref-clk-max-microamp = <100>;
status = "ok";
};
&qupv3_se0_i2c {
status = "ok";
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 9 0x00>;
qcom,sn-ven = <&tlmm 6 0x00>;
qcom,sn-firm = <&tlmm 8 0x00>;
qcom,sn-clkreq = <&tlmm 7 0x00>;
qcom,sn-vdd-1p8-supply = <&L11A>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <9 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};
&soc {
gpio_keys {
compatible = "gpio-keys";
label = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_vol_up_default>;
vol_up {
label = "volume_up";
gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
gpio-key,wakeup;
debounce-interval = <15>;
linux,can-disable;
};
};
};
&qupv3_se10_i2c {
status = "disabled";
};
&pm8008_8 {
status = "disabled";
};
&pm8008_9 {
status = "disabled";
};
&pm6150a_amoled {
status = "ok";
};
&pm7250b_charger {
status = "ok";
#io-channel-cells = <1>;
io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>,
<&pm7250b_vadc ADC5_USB_IN_I>,
<&pm7250b_vadc ADC5_CHG_TEMP>,
<&pm7250b_vadc ADC5_DIE_TEMP>,
<&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>,
<&pm7250b_vadc ADC5_SBUx>,
<&pm7250b_vadc ADC5_VPH_PWR>,
<&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>,
<&pm7250b_qg PSY_IIO_RESISTANCE_ID>,
<&pm7250b_qg PSY_IIO_VOLTAGE_NOW>,
<&pm7250b_qg PSY_IIO_TEMP>,
<&pm7250b_qg PSY_IIO_CAPACITY>,
<&pm7250b_qg PSY_IIO_VOLTAGE_OCV>,
<&pm7250b_qg PSY_IIO_VOLTAGE_AVG>,
<&pm7250b_qg PSY_IIO_DEBUG_BATTERY>,
<&pm7250b_qg PSY_IIO_REAL_CAPACITY>,
<&pm7250b_qg PSY_IIO_CC_SOC>,
<&pm7250b_qg PSY_IIO_CURRENT_NOW>,
<&pm7250b_qg PSY_IIO_VOLTAGE_MAX>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL>,
<&pm7250b_qg PSY_IIO_CHARGE_COUNTER>,
<&pm7250b_qg PSY_IIO_CYCLE_COUNT>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>,
<&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
"die_temp",
"conn_temp",
"sbux_res",
"vph_voltage",
"skin_temp",
"resistance_id",
"voltage_now",
"temp",
"capacity",
"voltage_ocv",
"voltage_avg",
"debug_battery",
"real_capacity",
"cc_soc",
"current_now",
"voltage_max",
"charge_full",
"charge_counter",
"cycle_count",
"charge_full_design",
"time_to_full_now";
qcom,batteryless-platform;
qcom,sec-charger-config = <0>;
qcom,auto-recharge-soc = <98>;
qcom,step-charging-enable;
qcom,sw-jeita-enable;
qcom,charger-temp-max = <800>;
qcom,smb-temp-max = <800>;
qcom,suspend-input-on-debug-batt;
};
&pm7250b_qg {
status = "ok";
#io-channel-cells = <1>;
io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>,
<&pm7250b_vadc ADC5_BAT_ID_100K_PU>,
<&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>,
<&pm7250b_charger PSY_IIO_RECHARGE_SOC>,
<&pm7250b_charger PSY_IIO_FORCE_RECHARGE>,
<&pm7250b_charger PSY_IIO_CHARGE_DONE>;
io-channel-names = "batt-therm",
"batt-id",
"input_current_limited",
"recharge_soc",
"force_recharge",
"charge_done";
qcom,qg-iterm-ma = <150>;
qcom,hold-soc-while-full;
qcom,linearize-soc;
qcom,cl-feedback-on;
};
&qupv3_se8_i2c {
status = "okay";
qcom,i2c-touch-active="synaptics,tcm-i2c";
synaptics_tcm@20 {
compatible = "synaptics,tcm-i2c";
reg = <0x20>;
interrupt-parent = <&tlmm>;
interrupts = <22 0x2008>;
pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
"pmx_ts_release";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&pmx_ts_release>;
vdd-supply = <&L11A>;
avdd-supply = <&L6A>;
synaptics,pwr-reg-name = "avdd";
synaptics,bus-reg-name = "vdd";
synaptics,irq-gpio = <&tlmm 22 0x2008>;
synaptics,irq-on-state = <0>;
synaptics,reset-gpio = <&tlmm 21 0x00>;
synaptics,reset-on-state = <0>;
synaptics,reset-active-ms = <20>;
synaptics,reset-delay-ms = <200>;
synaptics,power-delay-ms = <200>;
synaptics,ubl-i2c-addr = <0x20>;
synaptics,extend_report;
synaptics,firmware-name = "synaptics_firmware.img";
panel = <&dsi_rm69299_visionox_amoled_video
&dsi_rm69299_visionox_amoled_cmd>;
};
};
&pm7250b_charger {
dpdm-supply = <&qusb_phy0>;
smb5_vbus: qcom,smb5-vbus {
regulator-name = "smb5-vbus";
};
smb5_vconn: qcom,smb5-vconn {
regulator-name = "smb5-vconn";
};
};
&pm7250b_pdphy {
vdd-pdphy-supply = <&L3A>;
vbus-supply = <&smb5_vbus>;
vconn-supply = <&smb5_vconn>;
#io-channel-cells = <1>;
io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>,
<&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>,
<&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>,
<&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>,
<&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>,
<&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>,
<&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>,
<&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>,
<&pm7250b_charger PSY_IIO_PR_SWAP>,
<&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>,
<&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_charger PSY_IIO_TYPEC_MODE>,
<&pm7250b_charger PSY_IIO_PE_START>;
io-channel-names = "pd_active",
"typec_cc_orientation",
"connector_type",
"typec_power_role",
"pd_usb_suspend_supported",
"typec_src_rp",
"pd_in_hard_reset",
"pr_current_max",
"pr_swap",
"pd_voltage_min",
"pd_voltage_max",
"real_type",
"typec_mode",
"pe_start";
};
&usb0 {
extcon = <&pm7250b_pdphy>, <&eud>;
};

421
qcom/holi-audio-overlay.dtsi Normal file
View File

@@ -0,0 +1,421 @@
#include <dt-bindings/clock/qcom,audio-ext-clk.h>
#include <dt-bindings/sound/qcom,bolero-clk-rsc.h>
#include <dt-bindings/sound/audio-codec-port-types.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
&bolero {
qcom,num-macros = <3>;
qcom,bolero-version = <5>;
#address-cells = <1>;
#size-cells = <1>;
bolero-clk-rsc-mngr {
compatible = "qcom,bolero-clk-rsc-mngr";
qcom,fs-gen-sequence = <0x3000 0x1>,
<0x3004 0x1>, <0x3080 0x2>;
qcom,rx_mclk_mode_muxsel = <0x0A5640D8>;
qcom,va_mclk_mode_muxsel = <0x0A7A0000>;
clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
"va_core_clk", "va_npl_clk";
clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
<&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
<&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
};
va_macro: va-macro@A730000 {
compatible = "qcom,va-macro";
reg = <0xA730000 0x0>;
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
qcom,va-dmic-sample-rate = <600000>;
qcom,default-clk-id = <TX_CORE_CLK>;
qcom,is-used-swr-gpio = <1>;
qcom,va-swr-gpios = <&va_swr_gpios>;
swr0: va_swr_master {
compatible = "qcom,swr-mstr";
qcom,is_wcd937x = <1>;
#address-cells = <2>;
#size-cells = <0>;
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
qcom,swr_master_id = <3>;
qcom,swrm-hctl-reg = <0x0A7EC100>;
qcom,mipi-sdw-block-packing-mode = <1>;
swrm-io-base = <0xA740000 0x0>;
interrupts-extended =
<&wakegic 5 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 128 GPIO_ACTIVE_HIGH>;
interrupt-names = "swr_master_irq", "swr_wake_irq";
qcom,swr-num-ports = <3>;
qcom,swr-port-mapping = <1 SWRM_TX1_CH1 0x1>,
<1 SWRM_TX1_CH2 0x2>,
<1 SWRM_TX1_CH3 0x4>, <1 SWRM_TX1_CH4 0x8>,
<2 SWRM_TX2_CH1 0x1>, <2 SWRM_TX2_CH2 0x2>,
<2 SWRM_TX2_CH3 0x4>, <2 SWRM_TX2_CH4 0x8>,
<3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>,
<3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>;
qcom,swr-num-dev = <1>;
qcom,swr-clock-stop-mode0 = <1>;
qcom,swr-mstr-irq-wakeup-capable = <1>;
wcd937x_tx_slave: wcd937x-tx-slave {
compatible = "qcom,wcd937x-slave";
reg = <0x0A 0x01170223>;
};
wcd938x_tx_slave: wcd938x-tx-slave {
status = "disabled";
compatible = "qcom,wcd938x-slave";
reg = <0x0D 0x01170223>;
};
};
};
tx_macro: tx-macro@A620000 {
compatible = "qcom,tx-macro";
reg = <0xA620000 0x0>;
clock-names = "tx_core_clk", "tx_npl_clk";
clocks = <&clock_audio_tx_1 0>,
<&clock_audio_tx_2 0>;
qcom,tx-dmic-sample-rate = <2400000>;
qcom,is-used-swr-gpio = <0>;
};
rx_macro: rx-macro@A600000 {
compatible = "qcom,rx-macro";
reg = <0xA600000 0x0>;
clock-names = "rx_core_clk", "rx_npl_clk";
clocks = <&clock_audio_rx_1 0>,
<&clock_audio_rx_2 0>;
qcom,rx-swr-gpios = <&rx_swr_gpios>;
qcom,rx_mclk_mode_muxsel = <0xA5640D8>;
qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
qcom,default-clk-id = <TX_CORE_CLK>;
swr1: rx_swr_master {
compatible = "qcom,swr-mstr";
#address-cells = <2>;
#size-cells = <0>;
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
qcom,swr_master_id = <2>;
qcom,swrm-hctl-reg = <0x0A6A9098>;
qcom,mipi-sdw-block-packing-mode = <1>;
swrm-io-base = <0xA610000 0x0>;
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "swr_master_irq";
qcom,swr-num-ports = <6>;
qcom,swr-port-mapping = <1 HPH_L 0x1>,
<1 HPH_R 0x2>, <2 CLSH 0x1>,
<3 COMP_L 0x1>, <3 COMP_R 0x2>,
<4 LO 0x1>, <5 DSD_L 0x1>,
<5 DSD_R 0x2>, <6 PCM_OUT1 0x01>;
qcom,swr-num-dev = <1>;
qcom,swr-clock-stop-mode0 = <1>;
wcd937x_rx_slave: wcd937x-rx-slave {
compatible = "qcom,wcd937x-slave";
reg = <0x0A 0x01170224>;
};
wcd938x_rx_slave: wcd938x-rx-slave {
status = "disabled";
compatible = "qcom,wcd938x-slave";
reg = <0x0D 0x01170224>;
};
};
};
wcd938x_codec: wcd938x-codec {
status = "disabled";
compatible = "qcom,wcd938x-codec";
qcom,split-codec = <1>;
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
<4 DSD_R 0x2 0 DSD_R>;
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
<0 ADC2 0x2 0 SWRM_TX1_CH2>,
<1 ADC3 0x1 0 SWRM_TX1_CH3>,
<1 ADC4 0x2 0 SWRM_TX1_CH4>,
<2 DMIC0 0x1 0 SWRM_TX2_CH1>,
<2 DMIC1 0x2 0 SWRM_TX2_CH2>,
<2 MBHC 0x4 0 SWRM_TX2_CH3>,
<2 DMIC2 0x4 0 SWRM_TX2_CH3>,
<2 DMIC3 0x8 0 SWRM_TX2_CH4>,
<3 DMIC4 0x1 0 SWRM_TX3_CH1>,
<3 DMIC5 0x2 0 SWRM_TX3_CH2>,
<3 DMIC6 0x4 0 SWRM_TX3_CH3>,
<3 DMIC7 0x8 0 SWRM_TX3_CH4>;
qcom,wcd-rst-gpio-node = <&wcd937x_rst_gpio>;
qcom,rx-slave = <&wcd938x_rx_slave>;
qcom,tx-slave = <&wcd938x_tx_slave>;
cdc-vdd-rxtx-supply = <&L11A>;
qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
qcom,cdc-vdd-rxtx-current = <30000>;
cdc-vddio-supply = <&L11A>;
qcom,cdc-vddio-voltage = <1800000 1800000>;
qcom,cdc-vddio-current = <30000>;
cdc-vdd-buck-supply = <&L14A>;
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
qcom,cdc-vdd-buck-current = <650000>;
cdc-vdd-mic-bias-supply = <&BOB>;
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
qcom,cdc-vdd-mic-bias-current = <30000>;
qcom,cdc-micbias1-mv = <1800>;
qcom,cdc-micbias2-mv = <1800>;
qcom,cdc-micbias3-mv = <1800>;
qcom,cdc-micbias4-mv = <1800>;
qcom,cdc-static-supplies = "cdc-vdd-rxtx",
"cdc-vddio",
"cdc-vdd-mic-bias";
qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
};
wcd937x_codec: wcd937x-codec {
compatible = "qcom,wcd937x-codec";
qcom,split-codec = <1>;
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
<4 DSD_R 0x2 0 DSD_R>;
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
<1 ADC2 0x1 0 SWRM_TX2_CH1>,
<1 ADC3 0x2 0 SWRM_TX2_CH2>,
<2 DMIC0 0x1 0 SWRM_TX1_CH4>,
<2 DMIC1 0x2 0 SWRM_TX2_CH1>,
<2 MBHC 0x4 0 SWRM_TX2_CH2>,
<3 DMIC2 0x1 0 SWRM_TX2_CH3>,
<3 DMIC3 0x2 0 SWRM_TX2_CH4>,
<3 DMIC4 0x4 0 SWRM_TX3_CH1>,
<3 DMIC5 0x8 0 SWRM_TX3_CH2>;
qcom,wcd-rst-gpio-node = <&wcd937x_rst_gpio>;
qcom,rx-slave = <&wcd937x_rx_slave>;
qcom,tx-slave = <&wcd937x_tx_slave>;
cdc-vdd-rxtx-supply = <&L11A>;
qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
qcom,cdc-vdd-rxtx-current = <30000>;
cdc-vddpx-supply = <&L11A>;
qcom,cdc-vddpx-voltage = <1800000 1800000>;
qcom,cdc-vddpx-current = <30000>;
cdc-vdd-buck-supply = <&L14A>;
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
qcom,cdc-vdd-buck-current = <650000>;
cdc-vdd-mic-bias-supply = <&BOB>;
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
qcom,cdc-vdd-mic-bias-current = <45000>;
qcom,cdc-micbias1-mv = <1800>;
qcom,cdc-micbias2-mv = <1800>;
qcom,cdc-micbias3-mv = <1800>;
qcom,cdc-static-supplies = "cdc-vdd-rxtx",
"cdc-vddpx",
"cdc-vdd-mic-bias";
qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
};
};
&holi_snd {
qcom,model = "holi-mtp-snd-card";
qcom,sku-model = "holi-mtpsku1-snd-card";
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
qcom,wcn-btfm = <1>;
qcom,tdm-max-slots = <4>;
qcom,audio-routing =
"AMIC1", "Analog Mic1",
"Analog Mic1", "MIC BIAS1",
"AMIC2", "Analog Mic2",
"Analog Mic2", "MIC BIAS2",
"AMIC3", "Analog Mic3",
"Analog Mic3", "MIC BIAS3",
"AMIC4", "Analog Mic4",
"Analog Mic4", "MIC BIAS3",
"TX DMIC0", "Digital Mic0",
"TX DMIC0", "MIC BIAS1",
"TX DMIC1", "Digital Mic1",
"TX DMIC1", "MIC BIAS1",
"TX DMIC2", "Digital Mic2",
"TX DMIC2", "MIC BIAS3",
"TX DMIC3", "Digital Mic3",
"TX DMIC3", "MIC BIAS3",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"IN3_AUX", "AUX_OUT",
"RX_TX DEC0_INP", "TX DEC0 MUX",
"RX_TX DEC1_INP", "TX DEC1 MUX",
"RX_TX DEC2_INP", "TX DEC2 MUX",
"RX_TX DEC3_INP", "TX DEC3 MUX",
"SpkrMono WSA_IN", "AUX",
"TX SWR_INPUT", "WCD_TX_OUTPUT",
"VA SWR_INPUT", "VA_SWR_CLK",
"VA SWR_INPUT", "WCD_TX_OUTPUT",
"VA_AIF1 CAP", "VA_SWR_CLK",
"VA_AIF2 CAP", "VA_SWR_CLK",
"VA_AIF3 CAP", "VA_SWR_CLK",
"VA DMIC0", "Digital Mic0",
"VA DMIC1", "Digital Mic1",
"VA DMIC2", "Digital Mic2",
"VA DMIC3", "Digital Mic3",
"VA DMIC4", "Digital Mic4",
"VA DMIC5", "Digital Mic5",
"VA DMIC0", "VA MIC BIAS1",
"VA DMIC1", "VA MIC BIAS1",
"VA DMIC2", "VA MIC BIAS3",
"VA DMIC3", "VA MIC BIAS3";
qcom,msm-mbhc-hphl-swh = <1>;
qcom,msm-mbhc-gnd-swh = <1>;
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
nvmem-cells = <&adsp_variant>;
nvmem-cell-names = "adsp_variant";
asoc-codec = <&stub_codec>, <&bolero>,
<&wcd937x_codec>, <&wsa881x_i2c_e>,
<&wsa881x_i2c_f>;
asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
"wcd937x_codec", "wsa-codec0",
"wsa-codec1";
qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
<&bolero>;
};
&qupv3_se10_i2c {
wsa881x_i2c_e: wsa881x-i2c-codec@e {
compatible = "qcom,wsa881x-i2c-codec";
reg = <0x0e>;
clock-names = "wsa_mclk";
clocks = <&wsa881x_analog_clk 0>;
qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>;
qcom,wsa-analog-reset-gpio = <&wsa881x_analog_reset_gpio>;
cdc-vdd-1p8-supply = <&L11A>;
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
qcom,cdc-vdd-1p8-current = <10000>;
qcom,cdc-static-supplies = "cdc-vdd-1p8";
qcom,wsa-prefix = "SpkrMono";
};
wsa881x_i2c_44: wsa881x-i2c-codec@44 {
compatible = "qcom,wsa881x-i2c-codec";
reg = <0x044>;
};
wsa881x_i2c_f: wsa881x-i2c-codec@f {
status = "disabled";
compatible = "qcom,wsa881x-i2c-codec";
reg = <0x0f>;
clock-names = "wsa_mclk";
clocks = <&wsa881x_analog_clk 0>;
qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>;
qcom,wsa-analog-reset-gpio = <&wsa881x_analog_reset_gpio>;
cdc-vdd-1p8-supply = <&L11A>;
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
qcom,cdc-vdd-1p8-current = <10000>;
qcom,cdc-static-supplies = "cdc-vdd-1p8";
qcom,wsa-prefix = "SpkrMono";
};
wsa881x_i2c_45: wsa881x-i2c-codec@45 {
status = "disabled";
compatible = "qcom,wsa881x-i2c-codec";
reg = <0x045>;
};
};
&va_cdc_dma_0_tx {
qcom,msm-dai-is-island-supported = <1>;
};
&soc {
wcd937x_rst_gpio: msm_cdc_pinctrl@32 {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&wcd937x_reset_active>;
pinctrl-1 = <&wcd937x_reset_sleep>;
};
wsa881x_analog_reset_gpio: wsa_reset_gpio {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&spkr_2_sd_n_active>;
pinctrl-1 = <&spkr_2_sd_n_sleep>;
#gpio-cells = <0>;
};
wsa881x_analog_clk: wsa_ana_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
qcom,codec-lpass-ext-clk-freq = <9600000>;
qcom,codec-lpass-clk-id = <0x301>;
#clock-cells = <1>;
};
clock_audio_rx_1: rx_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
qcom,codec-lpass-ext-clk-freq = <22579200>;
qcom,codec-lpass-clk-id = <0x30E>;
#clock-cells = <1>;
};
clock_audio_rx_2: rx_npl_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>;
qcom,codec-lpass-ext-clk-freq = <22579200>;
qcom,codec-lpass-clk-id = <0x30F>;
#clock-cells = <1>;
};
clock_audio_tx_1: tx_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x30C>;
#clock-cells = <1>;
};
clock_audio_tx_2: tx_npl_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x30D>;
#clock-cells = <1>;
};
clock_audio_va_1: va_core_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x30B>;
#clock-cells = <1>;
};
clock_audio_va_2: va_npl_clk {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_8>;
qcom,codec-lpass-ext-clk-freq = <19200000>;
qcom,codec-lpass-clk-id = <0x310>;
#clock-cells = <1>;
};
};
&adsp_loader {
nvmem-cells = <&adsp_variant>;
nvmem-cell-names = "adsp_variant";
adsp-fw-names = "adsp2";
adsp-fw-bit-values = <0x1>;
};

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qcom/holi-audio.dtsi Normal file
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#include <dt-bindings/clock/qcom,audio-ext-clk.h>
#include "msm-audio-lpass.dtsi"
&msm_audio_ion {
iommus = <&apps_smmu 0x00A1 0x0>;
qcom,smmu-sid-mask = /bits/ 64 <0xf>;
};
&audio_apr {
q6core: qcom,q6core-audio {
compatible = "qcom,q6core-audio";
#address-cells = <1>;
#size-cells = <1>;
lpass_audio_hw_vote: vote_lpass_audio_hw {
compatible = "qcom,audio-ref-clk";
qcom,codec-ext-clk-src = <AUDIO_LPASS_AUDIO_HW_VOTE>;
#clock-cells = <1>;
};
lpi_tlmm: lpi_pinctrl@a7c0000 {
compatible = "qcom,lpi-pinctrl";
reg = <0xa7c0000 0x0>;
qcom,slew-reg = <0x0a95a000 0x0>;
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
qcom,gpios-count = <19>;
gpio-controller;
#gpio-cells = <2>;
qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
<0x00002000>, <0x00003000>,
<0x00004000>, <0x00005000>,
<0x00006000>, <0x00007000>,
<0x00008000>, <0x00009000>,
<0x0000A000>, <0x0000B000>,
<0x0000C000>, <0x0000D000>,
<0x0000E000>, <0x0000F0000>,
<0x00010000>, <0x00011000>,
<0x00012000>;
qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>,
<0x00000004>, <0x00000008>,
<0x0000000A>, <0x0000000C>,
<0x00000000>, <0x00000000>,
<0x00000000>, <0x00000000>,
<0x00000010>, <0x00000012>,
<0x00000000>, <0x00000000>,
<0x00000000>, <0x00000000>,
<0x00000000>, <0x00000000>,
<0x00000014>;
};
};
};
#include "holi-lpi.dtsi"
&q6core {
rx_swr_gpios: rx_swr_clk_data_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
&rx_swr_data1_active>;
pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
&rx_swr_data1_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <131>;
#gpio-cells = <0>;
};
va_swr_gpios: va_swr_clk_data_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&tx_swr_clk_active &tx_swr_data0_active
&tx_swr_data1_active &tx_swr_data2_active>;
pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data0_sleep
&tx_swr_data1_sleep &tx_swr_data2_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <128 129>;
#gpio-cells = <0>;
};
cdc_dmic01_gpios: cdc_dmic01_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <133 134>;
#gpio-cells = <0>;
};
cdc_dmic23_gpios: cdc_dmic23_pinctrl {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
qcom,lpi-gpios;
qcom,tlmm-pins = <136>;
#gpio-cells = <0>;
};
wsa881x_analog_clk_gpio: wsa_clk {
compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&wsa_mclk_active>;
pinctrl-1 = <&wsa_mclk_sleep>;
qcom,lpi-gpios;
#gpio-cells = <0>;
};
};
&q6core {
bolero: bolero-cdc {
compatible = "qcom,bolero-codec";
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
bolero-clk-rsc-mngr {
compatible = "qcom,bolero-clk-rsc-mngr";
};
va_macro: va-macro@A730000 {
swr0: va_swr_master {
};
};
rx_macro: rx-macro@A600000 {
swr1: rx_swr_master {
};
};
};
};
&q6core {
holi_snd: sound {
compatible = "qcom,holi-asoc-snd";
qcom,mi2s-audio-intf = <1>;
qcom,auxpcm-audio-intf = <1>;
qcom,wcn-btfm = <0>;
qcom,afe-rxtx-lb = <0>;
qcom,is-wcd937x-codec = <1>;
clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>;
asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
<&loopback>, <&compress>, <&hostless>,
<&afe>, <&lsm>, <&routing>, <&compr>,
<&pcm_noirq>;
asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
"msm-pcm-dsp.2", "msm-voip-dsp",
"msm-pcm-voice", "msm-pcm-loopback",
"msm-compress-dsp", "msm-pcm-hostless",
"msm-pcm-afe", "msm-lsm-client",
"msm-pcm-routing", "msm-compr-dsp",
"msm-pcm-dsp-noirq";
asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>,
<&dai_mi2s2>, <&dai_mi2s3>,
<&dai_pri_auxpcm>,
<&dai_sec_auxpcm>, <&dai_tert_auxpcm>,
<&dai_quat_auxpcm>,
<&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>,
<&afe_proxy_tx>, <&incall_record_rx>,
<&incall_record_tx>, <&incall_music_rx>,
<&incall_music_2_rx>,
<&afe_proxy_tx_1>,
<&proxy_rx>, <&proxy_tx>,
<&usb_audio_rx>, <&usb_audio_tx>,
<&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>,
<&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>,
<&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>,
<&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>,
<&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>,
<&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>,
<&va_cdc_dma_2_tx>,
<&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>,
<&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>,
<&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>,
<&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>,
<&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>,
<&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>,
<&rx_cdc_dma_7_rx>,<&afe_loopback_tx>;
asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",
"msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",
"msm-dai-q6-auxpcm.1",
"msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3",
"msm-dai-q6-auxpcm.4",
"msm-dai-q6-dev.224",
"msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
"msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
"msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
"msm-dai-q6-dev.32770",
"msm-dai-q6-dev.242",
"msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195",
"msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673",
"msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399",
"msm-dai-q6-dev.16401",
"msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865",
"msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881",
"msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897",
"msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913",
"msm-dai-cdc-dma-dev.45089",
"msm-dai-cdc-dma-dev.45091",
"msm-dai-cdc-dma-dev.45093",
"msm-dai-cdc-dma-dev.45104",
"msm-dai-cdc-dma-dev.45105",
"msm-dai-cdc-dma-dev.45106",
"msm-dai-cdc-dma-dev.45107",
"msm-dai-cdc-dma-dev.45108",
"msm-dai-cdc-dma-dev.45109",
"msm-dai-cdc-dma-dev.45110",
"msm-dai-cdc-dma-dev.45111",
"msm-dai-cdc-dma-dev.45112",
"msm-dai-cdc-dma-dev.45113",
"msm-dai-cdc-dma-dev.45114",
"msm-dai-cdc-dma-dev.45115",
"msm-dai-cdc-dma-dev.45118",
"msm-dai-q6-dev.24577";
};
};

16
qcom/holi-cdp-lcd-overlay.dts Normal file
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@@ -0,0 +1,16 @@
/dts-v1/;
/plugin/;
#include "holi-cdp-lcd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Holi CDP-LCD attached";
compatible = "qcom,holi-cdp", "qcom,holi", "qcom,cdp";
qcom,msm-id = <454 0x10000>, <472 0x10000>;
qcom,board-id = <1 1>;
};
&wsa881x_analog_reset_gpio {
pinctrl-0 = <&spkr_1_sd_n_active>;
pinctrl-1 = <&spkr_1_sd_n_sleep>;
};

10
qcom/holi-cdp-lcd.dts Normal file
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@@ -0,0 +1,10 @@
/dts-v1/;
#include "holi.dtsi"
#include "holi-cdp-lcd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Holi CDP-LCD attach";
compatible = "qcom,holi-cdp", "qcom,holi", "qcom,cdp";
qcom,board-id = <1 1>;
};

16
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@@ -0,0 +1,16 @@
#include "holi-cdp.dtsi"
&pm6150a_amoled {
status = "disabled";
};
&pm6150l_lcdb {
status = "ok";
};
&pm6150l_wled {
status = "ok";
qcom,string-cfg = <15>;
qcom,leds-per-string = <4>;
};

16
qcom/holi-cdp-overlay.dts Normal file
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@@ -0,0 +1,16 @@
/dts-v1/;
/plugin/;
#include "holi-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Holi CDP";
compatible = "qcom,holi-cdp", "qcom,holi", "qcom,cdp";
qcom,msm-id = <454 0x10000>, <472 0x10000>;
qcom,board-id = <1 0>;
};
&wsa881x_analog_reset_gpio {
pinctrl-0 = <&spkr_1_sd_n_active>;
pinctrl-1 = <&spkr_1_sd_n_sleep>;
};

10
qcom/holi-cdp.dts Normal file
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@@ -0,0 +1,10 @@
/dts-v1/;
#include "holi.dtsi"
#include "holi-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Holi CDP";
compatible = "qcom,holi-cdp", "qcom,holi", "qcom,cdp";
qcom,board-id = <1 0>;
};

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qcom/holi-cdp.dtsi Normal file
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@@ -0,0 +1,287 @@
#include "holi-audio-overlay.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include "holi-pmic-overlay.dtsi"
#include "holi-thermal-overlay.dtsi"
#include <dt-bindings/iio/qti_power_supply_iio.h>
&sdhc_1 {
status = "ok";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
vdd-supply = <&L7E>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L12A>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 325000>;
};
&sdhc_2 {
status = "ok";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
vdd-supply = <&L9E>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&L6E>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v3";
vdda-phy-supply = <&L18A>;
vdda-pll-supply = <&L22A>;
vdda-phy-max-microamp = <62900>;
vdda-pll-max-microamp = <18300>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vdd-hba-fixed-regulator;
vcc-supply = <&L7E>;
vcc-voltage-level = <2950000 2960000>;
vcc-max-microamp = <800000>;
vccq2-supply = <&L12A>;
vccq2-max-microamp = <800000>;
vccq2-voltage-level = <1800000 1800000>;
qcom,vddp-ref-clk-supply = <&L22A>;
qcom,vddp-ref-clk-max-microamp = <100>;
status = "ok";
};
&qupv3_se0_i2c {
status = "ok";
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 9 0x00>;
qcom,sn-ven = <&tlmm 6 0x00>;
qcom,sn-firm = <&tlmm 8 0x00>;
qcom,sn-clkreq = <&tlmm 7 0x00>;
qcom,sn-vdd-1p8-supply = <&L11A>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <9 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};
&soc {
gpio_keys {
compatible = "gpio-keys";
label = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_vol_up_default>;
vol_up {
label = "volume_up";
gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
gpio-key,wakeup;
debounce-interval = <15>;
linux,can-disable;
};
};
};
&pm6150a_amoled {
status = "ok";
};
&pm7250b_charger {
status = "ok";
#io-channel-cells = <1>;
io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>,
<&pm7250b_vadc ADC5_USB_IN_I>,
<&pm7250b_vadc ADC5_CHG_TEMP>,
<&pm7250b_vadc ADC5_DIE_TEMP>,
<&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>,
<&pm7250b_vadc ADC5_SBUx>,
<&pm7250b_vadc ADC5_VPH_PWR>,
<&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>,
<&pm7250b_qg PSY_IIO_RESISTANCE_ID>,
<&pm7250b_qg PSY_IIO_VOLTAGE_NOW>,
<&pm7250b_qg PSY_IIO_TEMP>,
<&pm7250b_qg PSY_IIO_CAPACITY>,
<&pm7250b_qg PSY_IIO_VOLTAGE_OCV>,
<&pm7250b_qg PSY_IIO_VOLTAGE_AVG>,
<&pm7250b_qg PSY_IIO_DEBUG_BATTERY>,
<&pm7250b_qg PSY_IIO_REAL_CAPACITY>,
<&pm7250b_qg PSY_IIO_CC_SOC>,
<&pm7250b_qg PSY_IIO_CURRENT_NOW>,
<&pm7250b_qg PSY_IIO_VOLTAGE_MAX>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL>,
<&pm7250b_qg PSY_IIO_CHARGE_COUNTER>,
<&pm7250b_qg PSY_IIO_CYCLE_COUNT>,
<&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>,
<&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>;
io-channel-names = "usb_in_voltage",
"usb_in_current",
"chg_temp",
"die_temp",
"conn_temp",
"sbux_res",
"vph_voltage",
"skin_temp",
"resistance_id",
"voltage_now",
"temp",
"capacity",
"voltage_ocv",
"voltage_avg",
"debug_battery",
"real_capacity",
"cc_soc",
"current_now",
"voltage_max",
"charge_full",
"charge_counter",
"cycle_count",
"charge_full_design",
"time_to_full_now";
qcom,batteryless-platform;
qcom,sec-charger-config = <0>;
qcom,auto-recharge-soc = <98>;
qcom,step-charging-enable;
qcom,sw-jeita-enable;
qcom,charger-temp-max = <800>;
qcom,smb-temp-max = <800>;
qcom,suspend-input-on-debug-batt;
};
&pm7250b_qg {
status = "ok";
#io-channel-cells = <1>;
io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>,
<&pm7250b_vadc ADC5_BAT_ID_100K_PU>,
<&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>,
<&pm7250b_charger PSY_IIO_RECHARGE_SOC>,
<&pm7250b_charger PSY_IIO_FORCE_RECHARGE>,
<&pm7250b_charger PSY_IIO_CHARGE_DONE>;
io-channel-names = "batt-therm",
"batt-id",
"input_current_limited",
"recharge_soc",
"force_recharge",
"charge_done";
qcom,qg-iterm-ma = <100>;
qcom,hold-soc-while-full;
qcom,linearize-soc;
qcom,cl-feedback-on;
};
&qupv3_se8_i2c {
status = "okay";
qcom,i2c-touch-active="synaptics,tcm-i2c";
synaptics_tcm@20 {
compatible = "synaptics,tcm-i2c";
reg = <0x20>;
interrupt-parent = <&tlmm>;
interrupts = <22 0x2008>;
pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
"pmx_ts_release";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&pmx_ts_release>;
vdd-supply = <&L11A>;
avdd-supply = <&L6A>;
synaptics,pwr-reg-name = "avdd";
synaptics,bus-reg-name = "vdd";
synaptics,irq-gpio = <&tlmm 22 0x2008>;
synaptics,irq-on-state = <0>;
synaptics,reset-gpio = <&tlmm 21 0x00>;
synaptics,reset-on-state = <0>;
synaptics,reset-active-ms = <20>;
synaptics,reset-delay-ms = <200>;
synaptics,power-delay-ms = <200>;
synaptics,ubl-i2c-addr = <0x20>;
synaptics,extend_report;
synaptics,firmware-name = "synaptics_firmware.img";
panel = <&dsi_rm69299_visionox_amoled_video
&dsi_rm69299_visionox_amoled_cmd>;
};
};
&pm7250b_charger {
dpdm-supply = <&qusb_phy0>;
smb5_vbus: qcom,smb5-vbus {
regulator-name = "smb5-vbus";
};
smb5_vconn: qcom,smb5-vconn {
regulator-name = "smb5-vconn";
};
};
&pm7250b_pdphy {
vdd-pdphy-supply = <&L3A>;
vbus-supply = <&smb5_vbus>;
vconn-supply = <&smb5_vconn>;
#io-channel-cells = <1>;
io-channels = <&pm7250b_charger PSY_IIO_PD_ACTIVE>,
<&pm7250b_charger PSY_IIO_TYPEC_CC_ORIENTATION>,
<&pm7250b_charger PSY_IIO_CONNECTOR_TYPE>,
<&pm7250b_charger PSY_IIO_TYPEC_POWER_ROLE>,
<&pm7250b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>,
<&pm7250b_charger PSY_IIO_TYPEC_SRC_RP>,
<&pm7250b_charger PSY_IIO_PD_IN_HARD_RESET>,
<&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>,
<&pm7250b_charger PSY_IIO_PR_SWAP>,
<&pm7250b_charger PSY_IIO_PD_VOLTAGE_MIN>,
<&pm7250b_charger PSY_IIO_PD_VOLTAGE_MAX>,
<&pm7250b_charger PSY_IIO_USB_REAL_TYPE>,
<&pm7250b_charger PSY_IIO_TYPEC_MODE>,
<&pm7250b_charger PSY_IIO_PE_START>;
io-channel-names = "pd_active",
"typec_cc_orientation",
"connector_type",
"typec_power_role",
"pd_usb_suspend_supported",
"typec_src_rp",
"pd_in_hard_reset",
"pr_current_max",
"pr_swap",
"pd_voltage_min",
"pd_voltage_max",
"real_type",
"typec_mode",
"pe_start";
};
&usb0 {
extcon = <&pm7250b_pdphy>, <&eud>;
};

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File diff suppressed because it is too large Load Diff

28
qcom/holi-gdsc.dtsi
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@@ -1,75 +1,79 @@
&soc {
/* GDSCs in GCC */
gcc_camss_top_gdsc: qcom,gdsc@1458004 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x1458004 0x4>;
regulator-name = "gcc_camss_top_gdsc";
status = "disabled";
};
gcc_ufs_phy_gdsc: qcom,gdsc@1445004 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x1445004 0x4>;
regulator-name = "gcc_ufs_phy_gdsc";
status = "disabled";
};
gcc_usb30_prim_gdsc: qcom,gdsc@141a004 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x141a004 0x4>;
regulator-name = "gcc_usb30_prim_gdsc";
status = "disabled";
};
gcc_vcodec0_gdsc: qcom,gdsc@1458098 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x1458098 0x4>;
regulator-name = "gcc_vcodec0_gdsc";
status = "disabled";
};
gcc_venus_gdsc: qcom,gdsc@145807c {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x145807c 0x4>;
regulator-name = "gcc_venus_gdsc";
status = "disabled";
};
hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x147d074 0x4>;
regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc";
qcom,gds-timeout = <500>;
qcom,no-status-check-on-disable;
status = "disabled";
};
hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x147d078 0x4>;
regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc";
qcom,gds-timeout = <500>;
qcom,no-status-check-on-disable;
status = "disabled";
};
hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x147d060 0x4>;
regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";
qcom,gds-timeout = <500>;
qcom,no-status-check-on-disable;
status = "disabled";
};
hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@147d07c {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x147d07c 0x4>;
regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";
qcom,gds-timeout = <500>;
qcom,no-status-check-on-disable;
status = "disabled";
};
/* GDSCs in DISPCC */
mdss_core_gdsc: qcom,gdsc@5f01004 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x5f01004 0x4>;
regulator-name = "mdss_core_gdsc";
proxy-supply = <&mdss_core_gdsc>;
@@ -94,7 +98,7 @@
};
gpu_cx_gdsc: qcom,gdsc@599106c {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x599106c 0x4>;
regulator-name = "gpu_cx_gdsc";
hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
@@ -105,7 +109,7 @@
};
gpu_gx_gdsc: qcom,gdsc@599100c {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0x599100c 0x4>;
regulator-name = "gpu_gx_gdsc";
sw-reset = <&gpu_gx_sw_reset>;

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qcom/holi-gpu.dtsi Normal file
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@@ -0,0 +1,336 @@
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
&soc {
pil_gpu: qcom,kgsl-hyp {
compatible = "qcom,pil-tz-generic";
qcom,pas-id = <13>;
qcom,firmware-name = "a615_zap";
memory-region = <&pil_gpu_micro_code_mem>;
};
msm_gpu: qcom,kgsl-3d0@5900000 {
compatible = "qcom,kgsl-3d0", "qcom,adreno-gpu-a619-holi";
status = "ok";
reg = <0x5900000 0x40000>,
<0x5961000 0x800>,
<0x0596A000 0x30000>,
<0x599E000 0x1000>;
reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "gmu_wrapper", "cx_misc";
interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "kgsl_3d0_irq";
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
<&gpucc GPU_CC_CXO_CLK>,
<&gcc GCC_BIMC_GPU_AXI_CLK>,
<&gpucc GPU_CC_AHB_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gpucc GPU_CC_CX_GMU_CLK>;
clock-names = "core_clk", "rbbmtimer_clk", "iface_clk",
"ahb_clk", "mem_clk", "gmu_clk";
vddcx-supply = <&gpu_cx_gdsc>;
vdd-supply = <&gpu_gx_gdsc>;
qcom,chipid = <0x06010900>;
nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
nvmem-cell-names = "speed_bin", "gaming_bin";
qcom,initial-pwrlevel = <4>;
qcom,gpu-quirk-secvid-set-once;
qcom,min-access-length = <32>;
qcom,ubwc-mode = <2>;
/* Enable context aware freq. scaling */
qcom,enable-ca-jump;
/* Context aware jump busy penalty in us */
qcom,ca-busy-penalty = <12000>;
interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI>;
interconnect-names = "gpu_icc_path";
qcom,bus-table-ddr7 =
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
<MHZ_TO_KBPS(451, 4)>, /* index=1 (LOW SVS) */
<MHZ_TO_KBPS(547, 4)>, /* index=2(LOW SVS) */
<MHZ_TO_KBPS(681, 4)>, /* index=3 (SVS) */
<MHZ_TO_KBPS(768, 4)>, /* index=4 (SVS) */
<MHZ_TO_KBPS(1017, 4)>, /* index=5 (SVS) */
<MHZ_TO_KBPS(1353, 4)>, /* index=6 (NOM) */
<MHZ_TO_KBPS(1555, 4)>, /* index=7 (NOM) */
<MHZ_TO_KBPS(1804, 4)>, /* index=8 (TURBO) */
<MHZ_TO_KBPS(2092, 4)>; /* index=9 (TURBO_L1) */
qcom,gpu-mempools {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-mempools";
/* 4K Page Pool configuration */
qcom,gpu-mempool@0 {
reg = <0>;
qcom,mempool-page-size = <4096>;
qcom,mempool-allocate;
};
/* 8K Page Pool configuration */
qcom,gpu-mempool@1 {
reg = <1>;
qcom,mempool-page-size = <8192>;
qcom,mempool-allocate;
};
/* 64K Page Pool configuration */
qcom,gpu-mempool@2 {
reg = <2>;
qcom,mempool-page-size = <65536>;
qcom,mempool-reserved = <256>;
};
/* 1M Page Pool configuration */
qcom,gpu-mempool@3 {
reg = <3>;
qcom,mempool-page-size = <1048576>;
qcom,mempool-reserved = <32>;
};
};
/*
* Speed-bin zero is default speed bin.
* For rest of the speed bins, speed-bin value
* is calulated as FMAX/4.8 MHz (round up to zero
* decimal places) + 2.
*/
qcom,gpu-pwrlevel-bins {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevel-bins";
qcom,gpu-pwrlevels-0 {
#address-cells = <1>;
#size-cells = <0>;
qcom,speed-bin = <0>;
qcom,ca-target-pwrlevel = <5>;
qcom,initial-pwrlevel = <6>;
/* TURBO_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <875000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq-ddr7 = <9>;
qcom,bus-min-ddr7 = <8>;
qcom,bus-max-ddr7 = <9>;
};
/* TURBO */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <800000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq-ddr7 = <8>;
qcom,bus-min-ddr7 = <7>;
qcom,bus-max-ddr7 = <9>;
};
/* NOM_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <650000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq-ddr7 = <7>;
qcom,bus-min-ddr7 = <5>;
qcom,bus-max-ddr7 = <9>;
};
/* NOM */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <565000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq-ddr7 = <6>;
qcom,bus-min-ddr7 = <5>;
qcom,bus-max-ddr7 = <8>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <430000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq-ddr7 = <5>;
qcom,bus-min-ddr7 = <4>;
qcom,bus-max-ddr7 = <7>;
};
/* SVS */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <355000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq-ddr7 = <4>;
qcom,bus-min-ddr7 = <2>;
qcom,bus-max-ddr7= <5>;
};
/* LOW SVS */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <253000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq-ddr7 = <2>;
qcom,bus-min-ddr7 = <1>;
qcom,bus-max-ddr7 = <4>;
};
};
qcom,gpu-pwrlevels-1 {
#address-cells = <1>;
#size-cells = <0>;
qcom,speed-bin = <138>;
qcom,ca-target-pwrlevel = <3>;
qcom,initial-pwrlevel = <4>;
/* NOM_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <650000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq-ddr7 = <7>;
qcom,bus-min-ddr7 = <5>;
qcom,bus-max-ddr7 = <9>;
};
/* NOM */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <565000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq-ddr7 = <6>;
qcom,bus-min-ddr7 = <5>;
qcom,bus-max-ddr7 = <8>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <430000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq-ddr7 = <5>;
qcom,bus-min-ddr7 = <4>;
qcom,bus-max-ddr7 = <7>;
};
/* SVS */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <355000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq-ddr7 = <4>;
qcom,bus-min-ddr7 = <2>;
qcom,bus-max-ddr7= <5>;
};
/* LOW SVS */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <253000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq-ddr7 = <2>;
qcom,bus-min-ddr7 = <1>;
qcom,bus-max-ddr7 = <4>;
};
};
qcom,gpu-pwrlevels-2 {
#address-cells = <1>;
#size-cells = <0>;
qcom,speed-bin = <92>;
qcom,ca-target-pwrlevel = <2>;
qcom,initial-pwrlevel = <1>;
/* SVS_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <430000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq-ddr7 = <5>;
qcom,bus-min-ddr7 = <4>;
qcom,bus-max-ddr7 = <7>;
};
/* SVS */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <355000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq-ddr7 = <4>;
qcom,bus-min-ddr7 = <2>;
qcom,bus-max-ddr7= <5>;
};
/* LOW SVS */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <253000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq-ddr7 = <2>;
qcom,bus-min-ddr7 = <1>;
qcom,bus-max-ddr7 = <4>;
};
};
};
};
kgsl_msm_iommu: qcom,kgsl-iommu@5940000 {
compatible = "qcom,kgsl-smmu-v2";
reg = <0x5940000 0x10000>;
vddcx-supply = <&gpu_cx_gdsc>;
clocks = <&gcc GCC_BIMC_GPU_AXI_CLK>,
<&gpucc GPU_CC_AHB_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
clock-names = "gcc_bimc_gpu_axi", "gpu_cc_ahb",
"gcc_gpu_memnoc_gfx";
gfx3d_user: gfx3d_user {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x0>;
qcom,iommu-dma = "disabled";
};
gfx3d_secure: gfx3d_secure {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x2>;
qcom,iommu-dma = "disabled";
};
};
};

33
qcom/holi-ion.dtsi
View File

@@ -15,5 +15,38 @@
reg = <ION_SECURE_HEAP_ID>;
qcom,ion-heap-type = "SYSTEM_SECURE";
};
qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */
reg = <ION_SECURE_CARVEOUT_HEAP_ID>;
qcom,ion-heap-type = "SECURE_CARVEOUT";
cdsp {
memory-region = <&cdsp_secure_heap_mem>;
token = <0x20000000>;
};
};
qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */
reg = <ION_SECURE_DISPLAY_HEAP_ID>;
memory-region = <&secure_display_memory>;
qcom,ion-heap-type = "HYP_CMA";
};
qcom,ion-heap@26 { /* USER CONTIG HEAP */
reg = <ION_USER_CONTIG_HEAP_ID>;
memory-region = <&user_contig_mem>;
qcom,ion-heap-type = "DMA";
};
qcom,ion-heap@27 { /* QSEECOM HEAP */
reg = <ION_QSECOM_HEAP_ID>;
memory-region = <&qseecom_mem>;
qcom,ion-heap-type = "DMA";
};
qcom,ion-heap@19 { /* QSEECOM TA HEAP */
reg = <ION_QSECOM_TA_HEAP_ID>;
memory-region = <&qseecom_ta_mem>;
qcom,ion-heap-type = "DMA";
};
};
};

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